1*df24e178SHelge Deller/* SPDX-License-Identifier: GPL-2.0 */ 2*df24e178SHelge Deller/* 3*df24e178SHelge Deller * Signal trampolines for 64 bit processes. 4*df24e178SHelge Deller * 5*df24e178SHelge Deller * Copyright (C) 2006 Randolph Chung <tausq@debian.org> 6*df24e178SHelge Deller * Copyright (C) 2018-2022 Helge Deller <deller@gmx.de> 7*df24e178SHelge Deller * Copyright (C) 2022 John David Anglin <dave.anglin@bell.net> 8*df24e178SHelge Deller */ 9*df24e178SHelge Deller#include <asm/unistd.h> 10*df24e178SHelge Deller#include <linux/linkage.h> 11*df24e178SHelge Deller#include <generated/asm-offsets.h> 12*df24e178SHelge Deller 13*df24e178SHelge Deller .text 14*df24e178SHelge Deller 15*df24e178SHelge Deller/* Gdb expects the trampoline is on the stack and the pc is offset from 16*df24e178SHelge Deller a 64-byte boundary by 0, 4 or 5 instructions. Since the vdso trampoline 17*df24e178SHelge Deller is not on the stack, we need a new variant with different offsets and 18*df24e178SHelge Deller data to tell gdb where to find the signal context on the stack. 19*df24e178SHelge Deller 20*df24e178SHelge Deller Here we put the offset to the context data at the start of the trampoline 21*df24e178SHelge Deller region and offset the first trampoline by 2 instructions. Please do 22*df24e178SHelge Deller not change the trampoline as the code in gdb depends on the following 23*df24e178SHelge Deller instruction sequence exactly. 24*df24e178SHelge Deller */ 25*df24e178SHelge Deller .align 64 26*df24e178SHelge Deller .word SIGFRAME_CONTEXT_REGS 27*df24e178SHelge Deller 28*df24e178SHelge Deller/* The nop here is a hack. The dwarf2 unwind routines subtract 1 from 29*df24e178SHelge Deller the return address to get an address in the middle of the presumed 30*df24e178SHelge Deller call instruction. Since we don't have a call here, we artifically 31*df24e178SHelge Deller extend the range covered by the unwind info by adding a nop before 32*df24e178SHelge Deller the real start. 33*df24e178SHelge Deller */ 34*df24e178SHelge Deller nop 35*df24e178SHelge Deller 36*df24e178SHelge Deller .globl __kernel_sigtramp_rt 37*df24e178SHelge Deller .type __kernel_sigtramp_rt, @function 38*df24e178SHelge Deller__kernel_sigtramp_rt: 39*df24e178SHelge Deller .proc 40*df24e178SHelge Deller .callinfo FRAME=ASM_SIGFRAME_SIZE,CALLS,SAVE_RP 41*df24e178SHelge Deller .entry 42*df24e178SHelge Deller 43*df24e178SHelge Deller.Lsigrt_start = . - 4 44*df24e178SHelge Deller0: ldi 0, %r25 /* (in_syscall=0) */ 45*df24e178SHelge Deller ldi __NR_rt_sigreturn, %r20 46*df24e178SHelge Deller ble 0x100(%sr2, %r0) 47*df24e178SHelge Deller nop 48*df24e178SHelge Deller 49*df24e178SHelge Deller1: ldi 1, %r25 /* (in_syscall=1) */ 50*df24e178SHelge Deller ldi __NR_rt_sigreturn, %r20 51*df24e178SHelge Deller ble 0x100(%sr2, %r0) 52*df24e178SHelge Deller nop 53*df24e178SHelge Deller.Lsigrt_end: 54*df24e178SHelge Deller .exit 55*df24e178SHelge Deller .procend 56*df24e178SHelge Deller .size __kernel_sigtramp_rt,.-__kernel_sigtramp_rt 57*df24e178SHelge Deller 58*df24e178SHelge Deller .section .eh_frame,"a",@progbits 59*df24e178SHelge Deller 60*df24e178SHelge Deller/* This is where the mcontext_t struct can be found on the stack. */ 61*df24e178SHelge Deller#define PTREGS SIGFRAME_CONTEXT_REGS /* 64-bit process offset is -720 */ 62*df24e178SHelge Deller 63*df24e178SHelge Deller/* Register REGNO can be found at offset OFS of the mcontext_t structure. */ 64*df24e178SHelge Deller .macro rsave regno,ofs 65*df24e178SHelge Deller .byte 0x05 /* DW_CFA_offset_extended */ 66*df24e178SHelge Deller .uleb128 \regno; /* regno */ 67*df24e178SHelge Deller .uleb128 \ofs /* factored offset */ 68*df24e178SHelge Deller .endm 69*df24e178SHelge Deller 70*df24e178SHelge Deller.Lcie: 71*df24e178SHelge Deller .long .Lcie_end - .Lcie_start 72*df24e178SHelge Deller.Lcie_start: 73*df24e178SHelge Deller .long 0 /* CIE ID */ 74*df24e178SHelge Deller .byte 1 /* Version number */ 75*df24e178SHelge Deller .stringz "zRS" /* NUL-terminated augmentation string */ 76*df24e178SHelge Deller .uleb128 4 /* Code alignment factor */ 77*df24e178SHelge Deller .sleb128 8 /* Data alignment factor */ 78*df24e178SHelge Deller .byte 61 /* Return address register column, iaoq[0] */ 79*df24e178SHelge Deller .uleb128 1 /* Augmentation value length */ 80*df24e178SHelge Deller .byte 0x1b /* DW_EH_PE_pcrel | DW_EH_PE_sdata4. */ 81*df24e178SHelge Deller .byte 0x0f /* DW_CFA_def_cfa_expresion */ 82*df24e178SHelge Deller .uleb128 9f - 1f /* length */ 83*df24e178SHelge Deller1: 84*df24e178SHelge Deller .byte 0x8e /* DW_OP_breg30 */ 85*df24e178SHelge Deller .sleb128 PTREGS 86*df24e178SHelge Deller9: 87*df24e178SHelge Deller .balign 8 88*df24e178SHelge Deller.Lcie_end: 89*df24e178SHelge Deller 90*df24e178SHelge Deller .long .Lfde0_end - .Lfde0_start 91*df24e178SHelge Deller.Lfde0_start: 92*df24e178SHelge Deller .long .Lfde0_start - .Lcie /* CIE pointer. */ 93*df24e178SHelge Deller .long .Lsigrt_start - . /* PC start, length */ 94*df24e178SHelge Deller .long .Lsigrt_end - .Lsigrt_start 95*df24e178SHelge Deller .uleb128 0 /* Augmentation */ 96*df24e178SHelge Deller 97*df24e178SHelge Deller /* General registers */ 98*df24e178SHelge Deller rsave 1, 2 99*df24e178SHelge Deller rsave 2, 3 100*df24e178SHelge Deller rsave 3, 4 101*df24e178SHelge Deller rsave 4, 5 102*df24e178SHelge Deller rsave 5, 6 103*df24e178SHelge Deller rsave 6, 7 104*df24e178SHelge Deller rsave 7, 8 105*df24e178SHelge Deller rsave 8, 9 106*df24e178SHelge Deller rsave 9, 10 107*df24e178SHelge Deller rsave 10, 11 108*df24e178SHelge Deller rsave 11, 12 109*df24e178SHelge Deller rsave 12, 13 110*df24e178SHelge Deller rsave 13, 14 111*df24e178SHelge Deller rsave 14, 15 112*df24e178SHelge Deller rsave 15, 16 113*df24e178SHelge Deller rsave 16, 17 114*df24e178SHelge Deller rsave 17, 18 115*df24e178SHelge Deller rsave 18, 19 116*df24e178SHelge Deller rsave 19, 20 117*df24e178SHelge Deller rsave 20, 21 118*df24e178SHelge Deller rsave 21, 22 119*df24e178SHelge Deller rsave 22, 23 120*df24e178SHelge Deller rsave 23, 24 121*df24e178SHelge Deller rsave 24, 25 122*df24e178SHelge Deller rsave 25, 26 123*df24e178SHelge Deller rsave 26, 27 124*df24e178SHelge Deller rsave 27, 28 125*df24e178SHelge Deller rsave 28, 29 126*df24e178SHelge Deller rsave 29, 30 127*df24e178SHelge Deller rsave 30, 31 128*df24e178SHelge Deller rsave 31, 32 129*df24e178SHelge Deller 130*df24e178SHelge Deller /* Floating-point registers */ 131*df24e178SHelge Deller rsave 32, 36 132*df24e178SHelge Deller rsave 33, 37 133*df24e178SHelge Deller rsave 34, 38 134*df24e178SHelge Deller rsave 35, 39 135*df24e178SHelge Deller rsave 36, 40 136*df24e178SHelge Deller rsave 37, 41 137*df24e178SHelge Deller rsave 38, 42 138*df24e178SHelge Deller rsave 39, 43 139*df24e178SHelge Deller rsave 40, 44 140*df24e178SHelge Deller rsave 41, 45 141*df24e178SHelge Deller rsave 42, 46 142*df24e178SHelge Deller rsave 43, 47 143*df24e178SHelge Deller rsave 44, 48 144*df24e178SHelge Deller rsave 45, 49 145*df24e178SHelge Deller rsave 46, 50 146*df24e178SHelge Deller rsave 47, 51 147*df24e178SHelge Deller rsave 48, 52 148*df24e178SHelge Deller rsave 49, 53 149*df24e178SHelge Deller rsave 50, 54 150*df24e178SHelge Deller rsave 51, 55 151*df24e178SHelge Deller rsave 52, 56 152*df24e178SHelge Deller rsave 53, 57 153*df24e178SHelge Deller rsave 54, 58 154*df24e178SHelge Deller rsave 55, 59 155*df24e178SHelge Deller rsave 56, 60 156*df24e178SHelge Deller rsave 57, 61 157*df24e178SHelge Deller rsave 58, 62 158*df24e178SHelge Deller rsave 59, 63 159*df24e178SHelge Deller 160*df24e178SHelge Deller /* SAR register */ 161*df24e178SHelge Deller rsave 60, 67 162*df24e178SHelge Deller 163*df24e178SHelge Deller /* iaoq[0] return address register */ 164*df24e178SHelge Deller rsave 61, 65 165*df24e178SHelge Deller .balign 8 166*df24e178SHelge Deller.Lfde0_end: 167