1*df24e178SHelge Deller/* SPDX-License-Identifier: GPL-2.0 */ 2*df24e178SHelge Deller/* 3*df24e178SHelge Deller * Signal trampolines for 32 bit processes. 4*df24e178SHelge Deller * 5*df24e178SHelge Deller * Copyright (C) 2006 Randolph Chung <tausq@debian.org> 6*df24e178SHelge Deller * Copyright (C) 2018-2022 Helge Deller <deller@gmx.de> 7*df24e178SHelge Deller * Copyright (C) 2022 John David Anglin <dave.anglin@bell.net> 8*df24e178SHelge Deller */ 9*df24e178SHelge Deller#include <asm/unistd.h> 10*df24e178SHelge Deller#include <linux/linkage.h> 11*df24e178SHelge Deller#include <generated/asm-offsets.h> 12*df24e178SHelge Deller 13*df24e178SHelge Deller .text 14*df24e178SHelge Deller 15*df24e178SHelge Deller/* Gdb expects the trampoline is on the stack and the pc is offset from 16*df24e178SHelge Deller a 64-byte boundary by 0, 4 or 5 instructions. Since the vdso trampoline 17*df24e178SHelge Deller is not on the stack, we need a new variant with different offsets and 18*df24e178SHelge Deller data to tell gdb where to find the signal context on the stack. 19*df24e178SHelge Deller 20*df24e178SHelge Deller Here we put the offset to the context data at the start of the trampoline 21*df24e178SHelge Deller region and offset the first trampoline by 2 instructions. Please do 22*df24e178SHelge Deller not change the trampoline as the code in gdb depends on the following 23*df24e178SHelge Deller instruction sequence exactly. 24*df24e178SHelge Deller */ 25*df24e178SHelge Deller .align 64 26*df24e178SHelge Deller .word SIGFRAME_CONTEXT_REGS32 27*df24e178SHelge Deller 28*df24e178SHelge Deller/* The nop here is a hack. The dwarf2 unwind routines subtract 1 from 29*df24e178SHelge Deller the return address to get an address in the middle of the presumed 30*df24e178SHelge Deller call instruction. Since we don't have a call here, we artifically 31*df24e178SHelge Deller extend the range covered by the unwind info by adding a nop before 32*df24e178SHelge Deller the real start. 33*df24e178SHelge Deller */ 34*df24e178SHelge Deller nop 35*df24e178SHelge Deller 36*df24e178SHelge Deller .globl __kernel_sigtramp_rt 37*df24e178SHelge Deller .type __kernel_sigtramp_rt, @function 38*df24e178SHelge Deller__kernel_sigtramp_rt: 39*df24e178SHelge Deller .proc 40*df24e178SHelge Deller .callinfo FRAME=ASM_SIGFRAME_SIZE32,CALLS,SAVE_RP 41*df24e178SHelge Deller .entry 42*df24e178SHelge Deller 43*df24e178SHelge Deller.Lsigrt_start = . - 4 44*df24e178SHelge Deller0: ldi 0, %r25 /* (in_syscall=0) */ 45*df24e178SHelge Deller ldi __NR_rt_sigreturn, %r20 46*df24e178SHelge Deller ble 0x100(%sr2, %r0) 47*df24e178SHelge Deller nop 48*df24e178SHelge Deller 49*df24e178SHelge Deller1: ldi 1, %r25 /* (in_syscall=1) */ 50*df24e178SHelge Deller ldi __NR_rt_sigreturn, %r20 51*df24e178SHelge Deller ble 0x100(%sr2, %r0) 52*df24e178SHelge Deller nop 53*df24e178SHelge Deller.Lsigrt_end: 54*df24e178SHelge Deller .exit 55*df24e178SHelge Deller .procend 56*df24e178SHelge Deller .size __kernel_sigtramp_rt,.-__kernel_sigtramp_rt 57*df24e178SHelge Deller 58*df24e178SHelge Deller 59*df24e178SHelge Deller .section .eh_frame,"a",@progbits 60*df24e178SHelge Deller 61*df24e178SHelge Deller/* This is where the mcontext_t struct can be found on the stack. */ 62*df24e178SHelge Deller#define PTREGS SIGFRAME_CONTEXT_REGS32 /* 32-bit process offset is -672 */ 63*df24e178SHelge Deller 64*df24e178SHelge Deller/* Register REGNO can be found at offset OFS of the mcontext_t structure. */ 65*df24e178SHelge Deller .macro rsave regno,ofs 66*df24e178SHelge Deller .byte 0x05 /* DW_CFA_offset_extended */ 67*df24e178SHelge Deller .uleb128 \regno; /* regno */ 68*df24e178SHelge Deller .uleb128 \ofs /* factored offset */ 69*df24e178SHelge Deller .endm 70*df24e178SHelge Deller 71*df24e178SHelge Deller.Lcie: 72*df24e178SHelge Deller .long .Lcie_end - .Lcie_start 73*df24e178SHelge Deller.Lcie_start: 74*df24e178SHelge Deller .long 0 /* CIE ID */ 75*df24e178SHelge Deller .byte 1 /* Version number */ 76*df24e178SHelge Deller .stringz "zRS" /* NUL-terminated augmentation string */ 77*df24e178SHelge Deller .uleb128 4 /* Code alignment factor */ 78*df24e178SHelge Deller .sleb128 4 /* Data alignment factor */ 79*df24e178SHelge Deller .byte 89 /* Return address register column, iaoq[0] */ 80*df24e178SHelge Deller .uleb128 1 /* Augmentation value length */ 81*df24e178SHelge Deller .byte 0x1b /* DW_EH_PE_pcrel | DW_EH_PE_sdata4. */ 82*df24e178SHelge Deller .byte 0x0f /* DW_CFA_def_cfa_expresion */ 83*df24e178SHelge Deller .uleb128 9f - 1f /* length */ 84*df24e178SHelge Deller1: 85*df24e178SHelge Deller .byte 0x8e /* DW_OP_breg30 */ 86*df24e178SHelge Deller .sleb128 PTREGS 87*df24e178SHelge Deller9: 88*df24e178SHelge Deller .balign 4 89*df24e178SHelge Deller.Lcie_end: 90*df24e178SHelge Deller 91*df24e178SHelge Deller .long .Lfde0_end - .Lfde0_start 92*df24e178SHelge Deller.Lfde0_start: 93*df24e178SHelge Deller .long .Lfde0_start - .Lcie /* CIE pointer. */ 94*df24e178SHelge Deller .long .Lsigrt_start - . /* PC start, length */ 95*df24e178SHelge Deller .long .Lsigrt_end - .Lsigrt_start 96*df24e178SHelge Deller .uleb128 0 /* Augmentation */ 97*df24e178SHelge Deller 98*df24e178SHelge Deller /* General registers */ 99*df24e178SHelge Deller rsave 1, 2 100*df24e178SHelge Deller rsave 2, 3 101*df24e178SHelge Deller rsave 3, 4 102*df24e178SHelge Deller rsave 4, 5 103*df24e178SHelge Deller rsave 5, 6 104*df24e178SHelge Deller rsave 6, 7 105*df24e178SHelge Deller rsave 7, 8 106*df24e178SHelge Deller rsave 8, 9 107*df24e178SHelge Deller rsave 9, 10 108*df24e178SHelge Deller rsave 10, 11 109*df24e178SHelge Deller rsave 11, 12 110*df24e178SHelge Deller rsave 12, 13 111*df24e178SHelge Deller rsave 13, 14 112*df24e178SHelge Deller rsave 14, 15 113*df24e178SHelge Deller rsave 15, 16 114*df24e178SHelge Deller rsave 16, 17 115*df24e178SHelge Deller rsave 17, 18 116*df24e178SHelge Deller rsave 18, 19 117*df24e178SHelge Deller rsave 19, 20 118*df24e178SHelge Deller rsave 20, 21 119*df24e178SHelge Deller rsave 21, 22 120*df24e178SHelge Deller rsave 22, 23 121*df24e178SHelge Deller rsave 23, 24 122*df24e178SHelge Deller rsave 24, 25 123*df24e178SHelge Deller rsave 25, 26 124*df24e178SHelge Deller rsave 26, 27 125*df24e178SHelge Deller rsave 27, 28 126*df24e178SHelge Deller rsave 28, 29 127*df24e178SHelge Deller rsave 29, 30 128*df24e178SHelge Deller rsave 30, 31 129*df24e178SHelge Deller rsave 31, 32 130*df24e178SHelge Deller 131*df24e178SHelge Deller /* Floating-point registers */ 132*df24e178SHelge Deller rsave 32, 42 133*df24e178SHelge Deller rsave 33, 43 134*df24e178SHelge Deller rsave 34, 44 135*df24e178SHelge Deller rsave 35, 45 136*df24e178SHelge Deller rsave 36, 46 137*df24e178SHelge Deller rsave 37, 47 138*df24e178SHelge Deller rsave 38, 48 139*df24e178SHelge Deller rsave 39, 49 140*df24e178SHelge Deller rsave 40, 50 141*df24e178SHelge Deller rsave 41, 51 142*df24e178SHelge Deller rsave 42, 52 143*df24e178SHelge Deller rsave 43, 53 144*df24e178SHelge Deller rsave 44, 54 145*df24e178SHelge Deller rsave 45, 55 146*df24e178SHelge Deller rsave 46, 56 147*df24e178SHelge Deller rsave 47, 57 148*df24e178SHelge Deller rsave 48, 58 149*df24e178SHelge Deller rsave 49, 59 150*df24e178SHelge Deller rsave 50, 60 151*df24e178SHelge Deller rsave 51, 61 152*df24e178SHelge Deller rsave 52, 62 153*df24e178SHelge Deller rsave 53, 63 154*df24e178SHelge Deller rsave 54, 64 155*df24e178SHelge Deller rsave 55, 65 156*df24e178SHelge Deller rsave 56, 66 157*df24e178SHelge Deller rsave 57, 67 158*df24e178SHelge Deller rsave 58, 68 159*df24e178SHelge Deller rsave 59, 69 160*df24e178SHelge Deller rsave 60, 70 161*df24e178SHelge Deller rsave 61, 71 162*df24e178SHelge Deller rsave 62, 72 163*df24e178SHelge Deller rsave 63, 73 164*df24e178SHelge Deller rsave 64, 74 165*df24e178SHelge Deller rsave 65, 75 166*df24e178SHelge Deller rsave 66, 76 167*df24e178SHelge Deller rsave 67, 77 168*df24e178SHelge Deller rsave 68, 78 169*df24e178SHelge Deller rsave 69, 79 170*df24e178SHelge Deller rsave 70, 80 171*df24e178SHelge Deller rsave 71, 81 172*df24e178SHelge Deller rsave 72, 82 173*df24e178SHelge Deller rsave 73, 83 174*df24e178SHelge Deller rsave 74, 84 175*df24e178SHelge Deller rsave 75, 85 176*df24e178SHelge Deller rsave 76, 86 177*df24e178SHelge Deller rsave 77, 87 178*df24e178SHelge Deller rsave 78, 88 179*df24e178SHelge Deller rsave 79, 89 180*df24e178SHelge Deller rsave 80, 90 181*df24e178SHelge Deller rsave 81, 91 182*df24e178SHelge Deller rsave 82, 92 183*df24e178SHelge Deller rsave 83, 93 184*df24e178SHelge Deller rsave 84, 94 185*df24e178SHelge Deller rsave 85, 95 186*df24e178SHelge Deller rsave 86, 96 187*df24e178SHelge Deller rsave 87, 97 188*df24e178SHelge Deller 189*df24e178SHelge Deller /* SAR register */ 190*df24e178SHelge Deller rsave 88, 102 191*df24e178SHelge Deller 192*df24e178SHelge Deller /* iaoq[0] return address register */ 193*df24e178SHelge Deller rsave 89, 100 194*df24e178SHelge Deller .balign 4 195*df24e178SHelge Deller.Lfde0_end: 196