1 /* 2 * Unaligned memory access handler 3 * 4 * Copyright (C) 2001 Randolph Chung <tausq@debian.org> 5 * Significantly tweaked by LaMont Jones <lamont@debian.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2, or (at your option) 10 * any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 * 21 */ 22 23 #include <linux/jiffies.h> 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/sched.h> 27 #include <linux/signal.h> 28 #include <linux/ratelimit.h> 29 #include <asm/uaccess.h> 30 #include <asm/hardirq.h> 31 32 /* #define DEBUG_UNALIGNED 1 */ 33 34 #ifdef DEBUG_UNALIGNED 35 #define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __func__ ); printk(KERN_DEBUG fmt, ##args ); } while (0) 36 #else 37 #define DPRINTF(fmt, args...) 38 #endif 39 40 #ifdef CONFIG_64BIT 41 #define RFMT "%016lx" 42 #else 43 #define RFMT "%08lx" 44 #endif 45 46 #define FIXUP_BRANCH(lbl) \ 47 "\tldil L%%" #lbl ", %%r1\n" \ 48 "\tldo R%%" #lbl "(%%r1), %%r1\n" \ 49 "\tbv,n %%r0(%%r1)\n" 50 /* If you use FIXUP_BRANCH, then you must list this clobber */ 51 #define FIXUP_BRANCH_CLOBBER "r1" 52 53 /* 1111 1100 0000 0000 0001 0011 1100 0000 */ 54 #define OPCODE1(a,b,c) ((a)<<26|(b)<<12|(c)<<6) 55 #define OPCODE2(a,b) ((a)<<26|(b)<<1) 56 #define OPCODE3(a,b) ((a)<<26|(b)<<2) 57 #define OPCODE4(a) ((a)<<26) 58 #define OPCODE1_MASK OPCODE1(0x3f,1,0xf) 59 #define OPCODE2_MASK OPCODE2(0x3f,1) 60 #define OPCODE3_MASK OPCODE3(0x3f,1) 61 #define OPCODE4_MASK OPCODE4(0x3f) 62 63 /* skip LDB - never unaligned (index) */ 64 #define OPCODE_LDH_I OPCODE1(0x03,0,0x1) 65 #define OPCODE_LDW_I OPCODE1(0x03,0,0x2) 66 #define OPCODE_LDD_I OPCODE1(0x03,0,0x3) 67 #define OPCODE_LDDA_I OPCODE1(0x03,0,0x4) 68 #define OPCODE_LDCD_I OPCODE1(0x03,0,0x5) 69 #define OPCODE_LDWA_I OPCODE1(0x03,0,0x6) 70 #define OPCODE_LDCW_I OPCODE1(0x03,0,0x7) 71 /* skip LDB - never unaligned (short) */ 72 #define OPCODE_LDH_S OPCODE1(0x03,1,0x1) 73 #define OPCODE_LDW_S OPCODE1(0x03,1,0x2) 74 #define OPCODE_LDD_S OPCODE1(0x03,1,0x3) 75 #define OPCODE_LDDA_S OPCODE1(0x03,1,0x4) 76 #define OPCODE_LDCD_S OPCODE1(0x03,1,0x5) 77 #define OPCODE_LDWA_S OPCODE1(0x03,1,0x6) 78 #define OPCODE_LDCW_S OPCODE1(0x03,1,0x7) 79 /* skip STB - never unaligned */ 80 #define OPCODE_STH OPCODE1(0x03,1,0x9) 81 #define OPCODE_STW OPCODE1(0x03,1,0xa) 82 #define OPCODE_STD OPCODE1(0x03,1,0xb) 83 /* skip STBY - never unaligned */ 84 /* skip STDBY - never unaligned */ 85 #define OPCODE_STWA OPCODE1(0x03,1,0xe) 86 #define OPCODE_STDA OPCODE1(0x03,1,0xf) 87 88 #define OPCODE_FLDWX OPCODE1(0x09,0,0x0) 89 #define OPCODE_FLDWXR OPCODE1(0x09,0,0x1) 90 #define OPCODE_FSTWX OPCODE1(0x09,0,0x8) 91 #define OPCODE_FSTWXR OPCODE1(0x09,0,0x9) 92 #define OPCODE_FLDWS OPCODE1(0x09,1,0x0) 93 #define OPCODE_FLDWSR OPCODE1(0x09,1,0x1) 94 #define OPCODE_FSTWS OPCODE1(0x09,1,0x8) 95 #define OPCODE_FSTWSR OPCODE1(0x09,1,0x9) 96 #define OPCODE_FLDDX OPCODE1(0x0b,0,0x0) 97 #define OPCODE_FSTDX OPCODE1(0x0b,0,0x8) 98 #define OPCODE_FLDDS OPCODE1(0x0b,1,0x0) 99 #define OPCODE_FSTDS OPCODE1(0x0b,1,0x8) 100 101 #define OPCODE_LDD_L OPCODE2(0x14,0) 102 #define OPCODE_FLDD_L OPCODE2(0x14,1) 103 #define OPCODE_STD_L OPCODE2(0x1c,0) 104 #define OPCODE_FSTD_L OPCODE2(0x1c,1) 105 106 #define OPCODE_LDW_M OPCODE3(0x17,1) 107 #define OPCODE_FLDW_L OPCODE3(0x17,0) 108 #define OPCODE_FSTW_L OPCODE3(0x1f,0) 109 #define OPCODE_STW_M OPCODE3(0x1f,1) 110 111 #define OPCODE_LDH_L OPCODE4(0x11) 112 #define OPCODE_LDW_L OPCODE4(0x12) 113 #define OPCODE_LDWM OPCODE4(0x13) 114 #define OPCODE_STH_L OPCODE4(0x19) 115 #define OPCODE_STW_L OPCODE4(0x1A) 116 #define OPCODE_STWM OPCODE4(0x1B) 117 118 #define MAJOR_OP(i) (((i)>>26)&0x3f) 119 #define R1(i) (((i)>>21)&0x1f) 120 #define R2(i) (((i)>>16)&0x1f) 121 #define R3(i) ((i)&0x1f) 122 #define FR3(i) ((((i)<<1)&0x1f)|(((i)>>6)&1)) 123 #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0)) 124 #define IM5_2(i) IM((i)>>16,5) 125 #define IM5_3(i) IM((i),5) 126 #define IM14(i) IM((i),14) 127 128 #define ERR_NOTHANDLED -1 129 #define ERR_PAGEFAULT -2 130 131 int unaligned_enabled __read_mostly = 1; 132 133 void die_if_kernel (char *str, struct pt_regs *regs, long err); 134 135 static int emulate_ldh(struct pt_regs *regs, int toreg) 136 { 137 unsigned long saddr = regs->ior; 138 unsigned long val = 0; 139 int ret; 140 141 DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n", 142 regs->isr, regs->ior, toreg); 143 144 __asm__ __volatile__ ( 145 " mtsp %4, %%sr1\n" 146 "1: ldbs 0(%%sr1,%3), %%r20\n" 147 "2: ldbs 1(%%sr1,%3), %0\n" 148 " depw %%r20, 23, 24, %0\n" 149 " copy %%r0, %1\n" 150 "3: \n" 151 " .section .fixup,\"ax\"\n" 152 "4: ldi -2, %1\n" 153 FIXUP_BRANCH(3b) 154 " .previous\n" 155 ASM_EXCEPTIONTABLE_ENTRY(1b, 4b) 156 ASM_EXCEPTIONTABLE_ENTRY(2b, 4b) 157 : "=r" (val), "=r" (ret) 158 : "0" (val), "r" (saddr), "r" (regs->isr) 159 : "r20", FIXUP_BRANCH_CLOBBER ); 160 161 DPRINTF("val = 0x" RFMT "\n", val); 162 163 if (toreg) 164 regs->gr[toreg] = val; 165 166 return ret; 167 } 168 169 static int emulate_ldw(struct pt_regs *regs, int toreg, int flop) 170 { 171 unsigned long saddr = regs->ior; 172 unsigned long val = 0; 173 int ret; 174 175 DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n", 176 regs->isr, regs->ior, toreg); 177 178 __asm__ __volatile__ ( 179 " zdep %3,28,2,%%r19\n" /* r19=(ofs&3)*8 */ 180 " mtsp %4, %%sr1\n" 181 " depw %%r0,31,2,%3\n" 182 "1: ldw 0(%%sr1,%3),%0\n" 183 "2: ldw 4(%%sr1,%3),%%r20\n" 184 " subi 32,%%r19,%%r19\n" 185 " mtctl %%r19,11\n" 186 " vshd %0,%%r20,%0\n" 187 " copy %%r0, %1\n" 188 "3: \n" 189 " .section .fixup,\"ax\"\n" 190 "4: ldi -2, %1\n" 191 FIXUP_BRANCH(3b) 192 " .previous\n" 193 ASM_EXCEPTIONTABLE_ENTRY(1b, 4b) 194 ASM_EXCEPTIONTABLE_ENTRY(2b, 4b) 195 : "=r" (val), "=r" (ret) 196 : "0" (val), "r" (saddr), "r" (regs->isr) 197 : "r19", "r20", FIXUP_BRANCH_CLOBBER ); 198 199 DPRINTF("val = 0x" RFMT "\n", val); 200 201 if (flop) 202 ((__u32*)(regs->fr))[toreg] = val; 203 else if (toreg) 204 regs->gr[toreg] = val; 205 206 return ret; 207 } 208 static int emulate_ldd(struct pt_regs *regs, int toreg, int flop) 209 { 210 unsigned long saddr = regs->ior; 211 __u64 val = 0; 212 int ret; 213 214 DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n", 215 regs->isr, regs->ior, toreg); 216 #ifdef CONFIG_PA20 217 218 #ifndef CONFIG_64BIT 219 if (!flop) 220 return -1; 221 #endif 222 __asm__ __volatile__ ( 223 " depd,z %3,60,3,%%r19\n" /* r19=(ofs&7)*8 */ 224 " mtsp %4, %%sr1\n" 225 " depd %%r0,63,3,%3\n" 226 "1: ldd 0(%%sr1,%3),%0\n" 227 "2: ldd 8(%%sr1,%3),%%r20\n" 228 " subi 64,%%r19,%%r19\n" 229 " mtsar %%r19\n" 230 " shrpd %0,%%r20,%%sar,%0\n" 231 " copy %%r0, %1\n" 232 "3: \n" 233 " .section .fixup,\"ax\"\n" 234 "4: ldi -2, %1\n" 235 FIXUP_BRANCH(3b) 236 " .previous\n" 237 ASM_EXCEPTIONTABLE_ENTRY(1b,4b) 238 ASM_EXCEPTIONTABLE_ENTRY(2b,4b) 239 : "=r" (val), "=r" (ret) 240 : "0" (val), "r" (saddr), "r" (regs->isr) 241 : "r19", "r20", FIXUP_BRANCH_CLOBBER ); 242 #else 243 { 244 unsigned long valh=0,vall=0; 245 __asm__ __volatile__ ( 246 " zdep %5,29,2,%%r19\n" /* r19=(ofs&3)*8 */ 247 " mtsp %6, %%sr1\n" 248 " dep %%r0,31,2,%5\n" 249 "1: ldw 0(%%sr1,%5),%0\n" 250 "2: ldw 4(%%sr1,%5),%1\n" 251 "3: ldw 8(%%sr1,%5),%%r20\n" 252 " subi 32,%%r19,%%r19\n" 253 " mtsar %%r19\n" 254 " vshd %0,%1,%0\n" 255 " vshd %1,%%r20,%1\n" 256 " copy %%r0, %2\n" 257 "4: \n" 258 " .section .fixup,\"ax\"\n" 259 "5: ldi -2, %2\n" 260 FIXUP_BRANCH(4b) 261 " .previous\n" 262 ASM_EXCEPTIONTABLE_ENTRY(1b,5b) 263 ASM_EXCEPTIONTABLE_ENTRY(2b,5b) 264 ASM_EXCEPTIONTABLE_ENTRY(3b,5b) 265 : "=r" (valh), "=r" (vall), "=r" (ret) 266 : "0" (valh), "1" (vall), "r" (saddr), "r" (regs->isr) 267 : "r19", "r20", FIXUP_BRANCH_CLOBBER ); 268 val=((__u64)valh<<32)|(__u64)vall; 269 } 270 #endif 271 272 DPRINTF("val = 0x%llx\n", val); 273 274 if (flop) 275 regs->fr[toreg] = val; 276 else if (toreg) 277 regs->gr[toreg] = val; 278 279 return ret; 280 } 281 282 static int emulate_sth(struct pt_regs *regs, int frreg) 283 { 284 unsigned long val = regs->gr[frreg]; 285 int ret; 286 287 if (!frreg) 288 val = 0; 289 290 DPRINTF("store r%d (0x" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg, 291 val, regs->isr, regs->ior); 292 293 __asm__ __volatile__ ( 294 " mtsp %3, %%sr1\n" 295 " extrw,u %1, 23, 8, %%r19\n" 296 "1: stb %1, 1(%%sr1, %2)\n" 297 "2: stb %%r19, 0(%%sr1, %2)\n" 298 " copy %%r0, %0\n" 299 "3: \n" 300 " .section .fixup,\"ax\"\n" 301 "4: ldi -2, %0\n" 302 FIXUP_BRANCH(3b) 303 " .previous\n" 304 ASM_EXCEPTIONTABLE_ENTRY(1b,4b) 305 ASM_EXCEPTIONTABLE_ENTRY(2b,4b) 306 : "=r" (ret) 307 : "r" (val), "r" (regs->ior), "r" (regs->isr) 308 : "r19", FIXUP_BRANCH_CLOBBER ); 309 310 return ret; 311 } 312 313 static int emulate_stw(struct pt_regs *regs, int frreg, int flop) 314 { 315 unsigned long val; 316 int ret; 317 318 if (flop) 319 val = ((__u32*)(regs->fr))[frreg]; 320 else if (frreg) 321 val = regs->gr[frreg]; 322 else 323 val = 0; 324 325 DPRINTF("store r%d (0x" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg, 326 val, regs->isr, regs->ior); 327 328 329 __asm__ __volatile__ ( 330 " mtsp %3, %%sr1\n" 331 " zdep %2, 28, 2, %%r19\n" 332 " dep %%r0, 31, 2, %2\n" 333 " mtsar %%r19\n" 334 " depwi,z -2, %%sar, 32, %%r19\n" 335 "1: ldw 0(%%sr1,%2),%%r20\n" 336 "2: ldw 4(%%sr1,%2),%%r21\n" 337 " vshd %%r0, %1, %%r22\n" 338 " vshd %1, %%r0, %%r1\n" 339 " and %%r20, %%r19, %%r20\n" 340 " andcm %%r21, %%r19, %%r21\n" 341 " or %%r22, %%r20, %%r20\n" 342 " or %%r1, %%r21, %%r21\n" 343 " stw %%r20,0(%%sr1,%2)\n" 344 " stw %%r21,4(%%sr1,%2)\n" 345 " copy %%r0, %0\n" 346 "3: \n" 347 " .section .fixup,\"ax\"\n" 348 "4: ldi -2, %0\n" 349 FIXUP_BRANCH(3b) 350 " .previous\n" 351 ASM_EXCEPTIONTABLE_ENTRY(1b,4b) 352 ASM_EXCEPTIONTABLE_ENTRY(2b,4b) 353 : "=r" (ret) 354 : "r" (val), "r" (regs->ior), "r" (regs->isr) 355 : "r19", "r20", "r21", "r22", "r1", FIXUP_BRANCH_CLOBBER ); 356 357 return 0; 358 } 359 static int emulate_std(struct pt_regs *regs, int frreg, int flop) 360 { 361 __u64 val; 362 int ret; 363 364 if (flop) 365 val = regs->fr[frreg]; 366 else if (frreg) 367 val = regs->gr[frreg]; 368 else 369 val = 0; 370 371 DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg, 372 val, regs->isr, regs->ior); 373 374 #ifdef CONFIG_PA20 375 #ifndef CONFIG_64BIT 376 if (!flop) 377 return -1; 378 #endif 379 __asm__ __volatile__ ( 380 " mtsp %3, %%sr1\n" 381 " depd,z %2, 60, 3, %%r19\n" 382 " depd %%r0, 63, 3, %2\n" 383 " mtsar %%r19\n" 384 " depdi,z -2, %%sar, 64, %%r19\n" 385 "1: ldd 0(%%sr1,%2),%%r20\n" 386 "2: ldd 8(%%sr1,%2),%%r21\n" 387 " shrpd %%r0, %1, %%sar, %%r22\n" 388 " shrpd %1, %%r0, %%sar, %%r1\n" 389 " and %%r20, %%r19, %%r20\n" 390 " andcm %%r21, %%r19, %%r21\n" 391 " or %%r22, %%r20, %%r20\n" 392 " or %%r1, %%r21, %%r21\n" 393 "3: std %%r20,0(%%sr1,%2)\n" 394 "4: std %%r21,8(%%sr1,%2)\n" 395 " copy %%r0, %0\n" 396 "5: \n" 397 " .section .fixup,\"ax\"\n" 398 "6: ldi -2, %0\n" 399 FIXUP_BRANCH(5b) 400 " .previous\n" 401 ASM_EXCEPTIONTABLE_ENTRY(1b,6b) 402 ASM_EXCEPTIONTABLE_ENTRY(2b,6b) 403 ASM_EXCEPTIONTABLE_ENTRY(3b,6b) 404 ASM_EXCEPTIONTABLE_ENTRY(4b,6b) 405 : "=r" (ret) 406 : "r" (val), "r" (regs->ior), "r" (regs->isr) 407 : "r19", "r20", "r21", "r22", "r1", FIXUP_BRANCH_CLOBBER ); 408 #else 409 { 410 unsigned long valh=(val>>32),vall=(val&0xffffffffl); 411 __asm__ __volatile__ ( 412 " mtsp %4, %%sr1\n" 413 " zdep %2, 29, 2, %%r19\n" 414 " dep %%r0, 31, 2, %2\n" 415 " mtsar %%r19\n" 416 " zvdepi -2, 32, %%r19\n" 417 "1: ldw 0(%%sr1,%3),%%r20\n" 418 "2: ldw 8(%%sr1,%3),%%r21\n" 419 " vshd %1, %2, %%r1\n" 420 " vshd %%r0, %1, %1\n" 421 " vshd %2, %%r0, %2\n" 422 " and %%r20, %%r19, %%r20\n" 423 " andcm %%r21, %%r19, %%r21\n" 424 " or %1, %%r20, %1\n" 425 " or %2, %%r21, %2\n" 426 "3: stw %1,0(%%sr1,%1)\n" 427 "4: stw %%r1,4(%%sr1,%3)\n" 428 "5: stw %2,8(%%sr1,%3)\n" 429 " copy %%r0, %0\n" 430 "6: \n" 431 " .section .fixup,\"ax\"\n" 432 "7: ldi -2, %0\n" 433 FIXUP_BRANCH(6b) 434 " .previous\n" 435 ASM_EXCEPTIONTABLE_ENTRY(1b,7b) 436 ASM_EXCEPTIONTABLE_ENTRY(2b,7b) 437 ASM_EXCEPTIONTABLE_ENTRY(3b,7b) 438 ASM_EXCEPTIONTABLE_ENTRY(4b,7b) 439 ASM_EXCEPTIONTABLE_ENTRY(5b,7b) 440 : "=r" (ret) 441 : "r" (valh), "r" (vall), "r" (regs->ior), "r" (regs->isr) 442 : "r19", "r20", "r21", "r1", FIXUP_BRANCH_CLOBBER ); 443 } 444 #endif 445 446 return ret; 447 } 448 449 void handle_unaligned(struct pt_regs *regs) 450 { 451 static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5); 452 unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0; 453 int modify = 0; 454 int ret = ERR_NOTHANDLED; 455 struct siginfo si; 456 register int flop=0; /* true if this is a flop */ 457 458 __inc_irq_stat(irq_unaligned_count); 459 460 /* log a message with pacing */ 461 if (user_mode(regs)) { 462 if (current->thread.flags & PARISC_UAC_SIGBUS) { 463 goto force_sigbus; 464 } 465 466 if (!(current->thread.flags & PARISC_UAC_NOPRINT) && 467 __ratelimit(&ratelimit)) { 468 char buf[256]; 469 sprintf(buf, "%s(%d): unaligned access to 0x" RFMT " at ip=0x" RFMT "\n", 470 current->comm, task_pid_nr(current), regs->ior, regs->iaoq[0]); 471 printk(KERN_WARNING "%s", buf); 472 #ifdef DEBUG_UNALIGNED 473 show_regs(regs); 474 #endif 475 } 476 477 if (!unaligned_enabled) 478 goto force_sigbus; 479 } 480 481 /* handle modification - OK, it's ugly, see the instruction manual */ 482 switch (MAJOR_OP(regs->iir)) 483 { 484 case 0x03: 485 case 0x09: 486 case 0x0b: 487 if (regs->iir&0x20) 488 { 489 modify = 1; 490 if (regs->iir&0x1000) /* short loads */ 491 if (regs->iir&0x200) 492 newbase += IM5_3(regs->iir); 493 else 494 newbase += IM5_2(regs->iir); 495 else if (regs->iir&0x2000) /* scaled indexed */ 496 { 497 int shift=0; 498 switch (regs->iir & OPCODE1_MASK) 499 { 500 case OPCODE_LDH_I: 501 shift= 1; break; 502 case OPCODE_LDW_I: 503 shift= 2; break; 504 case OPCODE_LDD_I: 505 case OPCODE_LDDA_I: 506 shift= 3; break; 507 } 508 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift; 509 } else /* simple indexed */ 510 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0); 511 } 512 break; 513 case 0x13: 514 case 0x1b: 515 modify = 1; 516 newbase += IM14(regs->iir); 517 break; 518 case 0x14: 519 case 0x1c: 520 if (regs->iir&8) 521 { 522 modify = 1; 523 newbase += IM14(regs->iir&~0xe); 524 } 525 break; 526 case 0x16: 527 case 0x1e: 528 modify = 1; 529 newbase += IM14(regs->iir&6); 530 break; 531 case 0x17: 532 case 0x1f: 533 if (regs->iir&4) 534 { 535 modify = 1; 536 newbase += IM14(regs->iir&~4); 537 } 538 break; 539 } 540 541 /* TODO: make this cleaner... */ 542 switch (regs->iir & OPCODE1_MASK) 543 { 544 case OPCODE_LDH_I: 545 case OPCODE_LDH_S: 546 ret = emulate_ldh(regs, R3(regs->iir)); 547 break; 548 549 case OPCODE_LDW_I: 550 case OPCODE_LDWA_I: 551 case OPCODE_LDW_S: 552 case OPCODE_LDWA_S: 553 ret = emulate_ldw(regs, R3(regs->iir),0); 554 break; 555 556 case OPCODE_STH: 557 ret = emulate_sth(regs, R2(regs->iir)); 558 break; 559 560 case OPCODE_STW: 561 case OPCODE_STWA: 562 ret = emulate_stw(regs, R2(regs->iir),0); 563 break; 564 565 #ifdef CONFIG_PA20 566 case OPCODE_LDD_I: 567 case OPCODE_LDDA_I: 568 case OPCODE_LDD_S: 569 case OPCODE_LDDA_S: 570 ret = emulate_ldd(regs, R3(regs->iir),0); 571 break; 572 573 case OPCODE_STD: 574 case OPCODE_STDA: 575 ret = emulate_std(regs, R2(regs->iir),0); 576 break; 577 #endif 578 579 case OPCODE_FLDWX: 580 case OPCODE_FLDWS: 581 case OPCODE_FLDWXR: 582 case OPCODE_FLDWSR: 583 flop=1; 584 ret = emulate_ldw(regs,FR3(regs->iir),1); 585 break; 586 587 case OPCODE_FLDDX: 588 case OPCODE_FLDDS: 589 flop=1; 590 ret = emulate_ldd(regs,R3(regs->iir),1); 591 break; 592 593 case OPCODE_FSTWX: 594 case OPCODE_FSTWS: 595 case OPCODE_FSTWXR: 596 case OPCODE_FSTWSR: 597 flop=1; 598 ret = emulate_stw(regs,FR3(regs->iir),1); 599 break; 600 601 case OPCODE_FSTDX: 602 case OPCODE_FSTDS: 603 flop=1; 604 ret = emulate_std(regs,R3(regs->iir),1); 605 break; 606 607 case OPCODE_LDCD_I: 608 case OPCODE_LDCW_I: 609 case OPCODE_LDCD_S: 610 case OPCODE_LDCW_S: 611 ret = ERR_NOTHANDLED; /* "undefined", but lets kill them. */ 612 break; 613 } 614 #ifdef CONFIG_PA20 615 switch (regs->iir & OPCODE2_MASK) 616 { 617 case OPCODE_FLDD_L: 618 flop=1; 619 ret = emulate_ldd(regs,R2(regs->iir),1); 620 break; 621 case OPCODE_FSTD_L: 622 flop=1; 623 ret = emulate_std(regs, R2(regs->iir),1); 624 break; 625 case OPCODE_LDD_L: 626 ret = emulate_ldd(regs, R2(regs->iir),0); 627 break; 628 case OPCODE_STD_L: 629 ret = emulate_std(regs, R2(regs->iir),0); 630 break; 631 } 632 #endif 633 switch (regs->iir & OPCODE3_MASK) 634 { 635 case OPCODE_FLDW_L: 636 flop=1; 637 ret = emulate_ldw(regs, R2(regs->iir),0); 638 break; 639 case OPCODE_LDW_M: 640 ret = emulate_ldw(regs, R2(regs->iir),1); 641 break; 642 643 case OPCODE_FSTW_L: 644 flop=1; 645 ret = emulate_stw(regs, R2(regs->iir),1); 646 break; 647 case OPCODE_STW_M: 648 ret = emulate_stw(regs, R2(regs->iir),0); 649 break; 650 } 651 switch (regs->iir & OPCODE4_MASK) 652 { 653 case OPCODE_LDH_L: 654 ret = emulate_ldh(regs, R2(regs->iir)); 655 break; 656 case OPCODE_LDW_L: 657 case OPCODE_LDWM: 658 ret = emulate_ldw(regs, R2(regs->iir),0); 659 break; 660 case OPCODE_STH_L: 661 ret = emulate_sth(regs, R2(regs->iir)); 662 break; 663 case OPCODE_STW_L: 664 case OPCODE_STWM: 665 ret = emulate_stw(regs, R2(regs->iir),0); 666 break; 667 } 668 669 if (modify && R1(regs->iir)) 670 regs->gr[R1(regs->iir)] = newbase; 671 672 673 if (ret == ERR_NOTHANDLED) 674 printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir); 675 676 DPRINTF("ret = %d\n", ret); 677 678 if (ret) 679 { 680 printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret); 681 die_if_kernel("Unaligned data reference", regs, 28); 682 683 if (ret == ERR_PAGEFAULT) 684 { 685 si.si_signo = SIGSEGV; 686 si.si_errno = 0; 687 si.si_code = SEGV_MAPERR; 688 si.si_addr = (void __user *)regs->ior; 689 force_sig_info(SIGSEGV, &si, current); 690 } 691 else 692 { 693 force_sigbus: 694 /* couldn't handle it ... */ 695 si.si_signo = SIGBUS; 696 si.si_errno = 0; 697 si.si_code = BUS_ADRALN; 698 si.si_addr = (void __user *)regs->ior; 699 force_sig_info(SIGBUS, &si, current); 700 } 701 702 return; 703 } 704 705 /* else we handled it, let life go on. */ 706 regs->gr[0]|=PSW_N; 707 } 708 709 /* 710 * NB: check_unaligned() is only used for PCXS processors right 711 * now, so we only check for PA1.1 encodings at this point. 712 */ 713 714 int 715 check_unaligned(struct pt_regs *regs) 716 { 717 unsigned long align_mask; 718 719 /* Get alignment mask */ 720 721 align_mask = 0UL; 722 switch (regs->iir & OPCODE1_MASK) { 723 724 case OPCODE_LDH_I: 725 case OPCODE_LDH_S: 726 case OPCODE_STH: 727 align_mask = 1UL; 728 break; 729 730 case OPCODE_LDW_I: 731 case OPCODE_LDWA_I: 732 case OPCODE_LDW_S: 733 case OPCODE_LDWA_S: 734 case OPCODE_STW: 735 case OPCODE_STWA: 736 align_mask = 3UL; 737 break; 738 739 default: 740 switch (regs->iir & OPCODE4_MASK) { 741 case OPCODE_LDH_L: 742 case OPCODE_STH_L: 743 align_mask = 1UL; 744 break; 745 case OPCODE_LDW_L: 746 case OPCODE_LDWM: 747 case OPCODE_STW_L: 748 case OPCODE_STWM: 749 align_mask = 3UL; 750 break; 751 } 752 break; 753 } 754 755 return (int)(regs->ior & align_mask); 756 } 757 758