1 /* 2 * Unaligned memory access handler 3 * 4 * Copyright (C) 2001 Randolph Chung <tausq@debian.org> 5 * Significantly tweaked by LaMont Jones <lamont@debian.org> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2, or (at your option) 10 * any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 * 21 */ 22 23 #include <linux/jiffies.h> 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/sched.h> 27 #include <linux/signal.h> 28 #include <linux/ratelimit.h> 29 #include <asm/uaccess.h> 30 #include <asm/hardirq.h> 31 #include <asm/traps.h> 32 33 /* #define DEBUG_UNALIGNED 1 */ 34 35 #ifdef DEBUG_UNALIGNED 36 #define DPRINTF(fmt, args...) do { printk(KERN_DEBUG "%s:%d:%s ", __FILE__, __LINE__, __func__ ); printk(KERN_DEBUG fmt, ##args ); } while (0) 37 #else 38 #define DPRINTF(fmt, args...) 39 #endif 40 41 #ifdef CONFIG_64BIT 42 #define RFMT "%016lx" 43 #else 44 #define RFMT "%08lx" 45 #endif 46 47 #define FIXUP_BRANCH(lbl) \ 48 "\tldil L%%" #lbl ", %%r1\n" \ 49 "\tldo R%%" #lbl "(%%r1), %%r1\n" \ 50 "\tbv,n %%r0(%%r1)\n" 51 /* If you use FIXUP_BRANCH, then you must list this clobber */ 52 #define FIXUP_BRANCH_CLOBBER "r1" 53 54 /* 1111 1100 0000 0000 0001 0011 1100 0000 */ 55 #define OPCODE1(a,b,c) ((a)<<26|(b)<<12|(c)<<6) 56 #define OPCODE2(a,b) ((a)<<26|(b)<<1) 57 #define OPCODE3(a,b) ((a)<<26|(b)<<2) 58 #define OPCODE4(a) ((a)<<26) 59 #define OPCODE1_MASK OPCODE1(0x3f,1,0xf) 60 #define OPCODE2_MASK OPCODE2(0x3f,1) 61 #define OPCODE3_MASK OPCODE3(0x3f,1) 62 #define OPCODE4_MASK OPCODE4(0x3f) 63 64 /* skip LDB - never unaligned (index) */ 65 #define OPCODE_LDH_I OPCODE1(0x03,0,0x1) 66 #define OPCODE_LDW_I OPCODE1(0x03,0,0x2) 67 #define OPCODE_LDD_I OPCODE1(0x03,0,0x3) 68 #define OPCODE_LDDA_I OPCODE1(0x03,0,0x4) 69 #define OPCODE_LDCD_I OPCODE1(0x03,0,0x5) 70 #define OPCODE_LDWA_I OPCODE1(0x03,0,0x6) 71 #define OPCODE_LDCW_I OPCODE1(0x03,0,0x7) 72 /* skip LDB - never unaligned (short) */ 73 #define OPCODE_LDH_S OPCODE1(0x03,1,0x1) 74 #define OPCODE_LDW_S OPCODE1(0x03,1,0x2) 75 #define OPCODE_LDD_S OPCODE1(0x03,1,0x3) 76 #define OPCODE_LDDA_S OPCODE1(0x03,1,0x4) 77 #define OPCODE_LDCD_S OPCODE1(0x03,1,0x5) 78 #define OPCODE_LDWA_S OPCODE1(0x03,1,0x6) 79 #define OPCODE_LDCW_S OPCODE1(0x03,1,0x7) 80 /* skip STB - never unaligned */ 81 #define OPCODE_STH OPCODE1(0x03,1,0x9) 82 #define OPCODE_STW OPCODE1(0x03,1,0xa) 83 #define OPCODE_STD OPCODE1(0x03,1,0xb) 84 /* skip STBY - never unaligned */ 85 /* skip STDBY - never unaligned */ 86 #define OPCODE_STWA OPCODE1(0x03,1,0xe) 87 #define OPCODE_STDA OPCODE1(0x03,1,0xf) 88 89 #define OPCODE_FLDWX OPCODE1(0x09,0,0x0) 90 #define OPCODE_FLDWXR OPCODE1(0x09,0,0x1) 91 #define OPCODE_FSTWX OPCODE1(0x09,0,0x8) 92 #define OPCODE_FSTWXR OPCODE1(0x09,0,0x9) 93 #define OPCODE_FLDWS OPCODE1(0x09,1,0x0) 94 #define OPCODE_FLDWSR OPCODE1(0x09,1,0x1) 95 #define OPCODE_FSTWS OPCODE1(0x09,1,0x8) 96 #define OPCODE_FSTWSR OPCODE1(0x09,1,0x9) 97 #define OPCODE_FLDDX OPCODE1(0x0b,0,0x0) 98 #define OPCODE_FSTDX OPCODE1(0x0b,0,0x8) 99 #define OPCODE_FLDDS OPCODE1(0x0b,1,0x0) 100 #define OPCODE_FSTDS OPCODE1(0x0b,1,0x8) 101 102 #define OPCODE_LDD_L OPCODE2(0x14,0) 103 #define OPCODE_FLDD_L OPCODE2(0x14,1) 104 #define OPCODE_STD_L OPCODE2(0x1c,0) 105 #define OPCODE_FSTD_L OPCODE2(0x1c,1) 106 107 #define OPCODE_LDW_M OPCODE3(0x17,1) 108 #define OPCODE_FLDW_L OPCODE3(0x17,0) 109 #define OPCODE_FSTW_L OPCODE3(0x1f,0) 110 #define OPCODE_STW_M OPCODE3(0x1f,1) 111 112 #define OPCODE_LDH_L OPCODE4(0x11) 113 #define OPCODE_LDW_L OPCODE4(0x12) 114 #define OPCODE_LDWM OPCODE4(0x13) 115 #define OPCODE_STH_L OPCODE4(0x19) 116 #define OPCODE_STW_L OPCODE4(0x1A) 117 #define OPCODE_STWM OPCODE4(0x1B) 118 119 #define MAJOR_OP(i) (((i)>>26)&0x3f) 120 #define R1(i) (((i)>>21)&0x1f) 121 #define R2(i) (((i)>>16)&0x1f) 122 #define R3(i) ((i)&0x1f) 123 #define FR3(i) ((((i)<<1)&0x1f)|(((i)>>6)&1)) 124 #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0)) 125 #define IM5_2(i) IM((i)>>16,5) 126 #define IM5_3(i) IM((i),5) 127 #define IM14(i) IM((i),14) 128 129 #define ERR_NOTHANDLED -1 130 #define ERR_PAGEFAULT -2 131 132 int unaligned_enabled __read_mostly = 1; 133 134 static int emulate_ldh(struct pt_regs *regs, int toreg) 135 { 136 unsigned long saddr = regs->ior; 137 unsigned long val = 0; 138 int ret; 139 140 DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n", 141 regs->isr, regs->ior, toreg); 142 143 __asm__ __volatile__ ( 144 " mtsp %4, %%sr1\n" 145 "1: ldbs 0(%%sr1,%3), %%r20\n" 146 "2: ldbs 1(%%sr1,%3), %0\n" 147 " depw %%r20, 23, 24, %0\n" 148 " copy %%r0, %1\n" 149 "3: \n" 150 " .section .fixup,\"ax\"\n" 151 "4: ldi -2, %1\n" 152 FIXUP_BRANCH(3b) 153 " .previous\n" 154 ASM_EXCEPTIONTABLE_ENTRY(1b, 4b) 155 ASM_EXCEPTIONTABLE_ENTRY(2b, 4b) 156 : "=r" (val), "=r" (ret) 157 : "0" (val), "r" (saddr), "r" (regs->isr) 158 : "r20", FIXUP_BRANCH_CLOBBER ); 159 160 DPRINTF("val = 0x" RFMT "\n", val); 161 162 if (toreg) 163 regs->gr[toreg] = val; 164 165 return ret; 166 } 167 168 static int emulate_ldw(struct pt_regs *regs, int toreg, int flop) 169 { 170 unsigned long saddr = regs->ior; 171 unsigned long val = 0; 172 int ret; 173 174 DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n", 175 regs->isr, regs->ior, toreg); 176 177 __asm__ __volatile__ ( 178 " zdep %3,28,2,%%r19\n" /* r19=(ofs&3)*8 */ 179 " mtsp %4, %%sr1\n" 180 " depw %%r0,31,2,%3\n" 181 "1: ldw 0(%%sr1,%3),%0\n" 182 "2: ldw 4(%%sr1,%3),%%r20\n" 183 " subi 32,%%r19,%%r19\n" 184 " mtctl %%r19,11\n" 185 " vshd %0,%%r20,%0\n" 186 " copy %%r0, %1\n" 187 "3: \n" 188 " .section .fixup,\"ax\"\n" 189 "4: ldi -2, %1\n" 190 FIXUP_BRANCH(3b) 191 " .previous\n" 192 ASM_EXCEPTIONTABLE_ENTRY(1b, 4b) 193 ASM_EXCEPTIONTABLE_ENTRY(2b, 4b) 194 : "=r" (val), "=r" (ret) 195 : "0" (val), "r" (saddr), "r" (regs->isr) 196 : "r19", "r20", FIXUP_BRANCH_CLOBBER ); 197 198 DPRINTF("val = 0x" RFMT "\n", val); 199 200 if (flop) 201 ((__u32*)(regs->fr))[toreg] = val; 202 else if (toreg) 203 regs->gr[toreg] = val; 204 205 return ret; 206 } 207 static int emulate_ldd(struct pt_regs *regs, int toreg, int flop) 208 { 209 unsigned long saddr = regs->ior; 210 __u64 val = 0; 211 int ret; 212 213 DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n", 214 regs->isr, regs->ior, toreg); 215 #ifdef CONFIG_PA20 216 217 #ifndef CONFIG_64BIT 218 if (!flop) 219 return -1; 220 #endif 221 __asm__ __volatile__ ( 222 " depd,z %3,60,3,%%r19\n" /* r19=(ofs&7)*8 */ 223 " mtsp %4, %%sr1\n" 224 " depd %%r0,63,3,%3\n" 225 "1: ldd 0(%%sr1,%3),%0\n" 226 "2: ldd 8(%%sr1,%3),%%r20\n" 227 " subi 64,%%r19,%%r19\n" 228 " mtsar %%r19\n" 229 " shrpd %0,%%r20,%%sar,%0\n" 230 " copy %%r0, %1\n" 231 "3: \n" 232 " .section .fixup,\"ax\"\n" 233 "4: ldi -2, %1\n" 234 FIXUP_BRANCH(3b) 235 " .previous\n" 236 ASM_EXCEPTIONTABLE_ENTRY(1b,4b) 237 ASM_EXCEPTIONTABLE_ENTRY(2b,4b) 238 : "=r" (val), "=r" (ret) 239 : "0" (val), "r" (saddr), "r" (regs->isr) 240 : "r19", "r20", FIXUP_BRANCH_CLOBBER ); 241 #else 242 { 243 unsigned long valh=0,vall=0; 244 __asm__ __volatile__ ( 245 " zdep %5,29,2,%%r19\n" /* r19=(ofs&3)*8 */ 246 " mtsp %6, %%sr1\n" 247 " dep %%r0,31,2,%5\n" 248 "1: ldw 0(%%sr1,%5),%0\n" 249 "2: ldw 4(%%sr1,%5),%1\n" 250 "3: ldw 8(%%sr1,%5),%%r20\n" 251 " subi 32,%%r19,%%r19\n" 252 " mtsar %%r19\n" 253 " vshd %0,%1,%0\n" 254 " vshd %1,%%r20,%1\n" 255 " copy %%r0, %2\n" 256 "4: \n" 257 " .section .fixup,\"ax\"\n" 258 "5: ldi -2, %2\n" 259 FIXUP_BRANCH(4b) 260 " .previous\n" 261 ASM_EXCEPTIONTABLE_ENTRY(1b,5b) 262 ASM_EXCEPTIONTABLE_ENTRY(2b,5b) 263 ASM_EXCEPTIONTABLE_ENTRY(3b,5b) 264 : "=r" (valh), "=r" (vall), "=r" (ret) 265 : "0" (valh), "1" (vall), "r" (saddr), "r" (regs->isr) 266 : "r19", "r20", FIXUP_BRANCH_CLOBBER ); 267 val=((__u64)valh<<32)|(__u64)vall; 268 } 269 #endif 270 271 DPRINTF("val = 0x%llx\n", val); 272 273 if (flop) 274 regs->fr[toreg] = val; 275 else if (toreg) 276 regs->gr[toreg] = val; 277 278 return ret; 279 } 280 281 static int emulate_sth(struct pt_regs *regs, int frreg) 282 { 283 unsigned long val = regs->gr[frreg]; 284 int ret; 285 286 if (!frreg) 287 val = 0; 288 289 DPRINTF("store r%d (0x" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg, 290 val, regs->isr, regs->ior); 291 292 __asm__ __volatile__ ( 293 " mtsp %3, %%sr1\n" 294 " extrw,u %1, 23, 8, %%r19\n" 295 "1: stb %1, 1(%%sr1, %2)\n" 296 "2: stb %%r19, 0(%%sr1, %2)\n" 297 " copy %%r0, %0\n" 298 "3: \n" 299 " .section .fixup,\"ax\"\n" 300 "4: ldi -2, %0\n" 301 FIXUP_BRANCH(3b) 302 " .previous\n" 303 ASM_EXCEPTIONTABLE_ENTRY(1b,4b) 304 ASM_EXCEPTIONTABLE_ENTRY(2b,4b) 305 : "=r" (ret) 306 : "r" (val), "r" (regs->ior), "r" (regs->isr) 307 : "r19", FIXUP_BRANCH_CLOBBER ); 308 309 return ret; 310 } 311 312 static int emulate_stw(struct pt_regs *regs, int frreg, int flop) 313 { 314 unsigned long val; 315 int ret; 316 317 if (flop) 318 val = ((__u32*)(regs->fr))[frreg]; 319 else if (frreg) 320 val = regs->gr[frreg]; 321 else 322 val = 0; 323 324 DPRINTF("store r%d (0x" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg, 325 val, regs->isr, regs->ior); 326 327 328 __asm__ __volatile__ ( 329 " mtsp %3, %%sr1\n" 330 " zdep %2, 28, 2, %%r19\n" 331 " dep %%r0, 31, 2, %2\n" 332 " mtsar %%r19\n" 333 " depwi,z -2, %%sar, 32, %%r19\n" 334 "1: ldw 0(%%sr1,%2),%%r20\n" 335 "2: ldw 4(%%sr1,%2),%%r21\n" 336 " vshd %%r0, %1, %%r22\n" 337 " vshd %1, %%r0, %%r1\n" 338 " and %%r20, %%r19, %%r20\n" 339 " andcm %%r21, %%r19, %%r21\n" 340 " or %%r22, %%r20, %%r20\n" 341 " or %%r1, %%r21, %%r21\n" 342 " stw %%r20,0(%%sr1,%2)\n" 343 " stw %%r21,4(%%sr1,%2)\n" 344 " copy %%r0, %0\n" 345 "3: \n" 346 " .section .fixup,\"ax\"\n" 347 "4: ldi -2, %0\n" 348 FIXUP_BRANCH(3b) 349 " .previous\n" 350 ASM_EXCEPTIONTABLE_ENTRY(1b,4b) 351 ASM_EXCEPTIONTABLE_ENTRY(2b,4b) 352 : "=r" (ret) 353 : "r" (val), "r" (regs->ior), "r" (regs->isr) 354 : "r19", "r20", "r21", "r22", "r1", FIXUP_BRANCH_CLOBBER ); 355 356 return 0; 357 } 358 static int emulate_std(struct pt_regs *regs, int frreg, int flop) 359 { 360 __u64 val; 361 int ret; 362 363 if (flop) 364 val = regs->fr[frreg]; 365 else if (frreg) 366 val = regs->gr[frreg]; 367 else 368 val = 0; 369 370 DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg, 371 val, regs->isr, regs->ior); 372 373 #ifdef CONFIG_PA20 374 #ifndef CONFIG_64BIT 375 if (!flop) 376 return -1; 377 #endif 378 __asm__ __volatile__ ( 379 " mtsp %3, %%sr1\n" 380 " depd,z %2, 60, 3, %%r19\n" 381 " depd %%r0, 63, 3, %2\n" 382 " mtsar %%r19\n" 383 " depdi,z -2, %%sar, 64, %%r19\n" 384 "1: ldd 0(%%sr1,%2),%%r20\n" 385 "2: ldd 8(%%sr1,%2),%%r21\n" 386 " shrpd %%r0, %1, %%sar, %%r22\n" 387 " shrpd %1, %%r0, %%sar, %%r1\n" 388 " and %%r20, %%r19, %%r20\n" 389 " andcm %%r21, %%r19, %%r21\n" 390 " or %%r22, %%r20, %%r20\n" 391 " or %%r1, %%r21, %%r21\n" 392 "3: std %%r20,0(%%sr1,%2)\n" 393 "4: std %%r21,8(%%sr1,%2)\n" 394 " copy %%r0, %0\n" 395 "5: \n" 396 " .section .fixup,\"ax\"\n" 397 "6: ldi -2, %0\n" 398 FIXUP_BRANCH(5b) 399 " .previous\n" 400 ASM_EXCEPTIONTABLE_ENTRY(1b,6b) 401 ASM_EXCEPTIONTABLE_ENTRY(2b,6b) 402 ASM_EXCEPTIONTABLE_ENTRY(3b,6b) 403 ASM_EXCEPTIONTABLE_ENTRY(4b,6b) 404 : "=r" (ret) 405 : "r" (val), "r" (regs->ior), "r" (regs->isr) 406 : "r19", "r20", "r21", "r22", "r1", FIXUP_BRANCH_CLOBBER ); 407 #else 408 { 409 unsigned long valh=(val>>32),vall=(val&0xffffffffl); 410 __asm__ __volatile__ ( 411 " mtsp %4, %%sr1\n" 412 " zdep %2, 29, 2, %%r19\n" 413 " dep %%r0, 31, 2, %2\n" 414 " mtsar %%r19\n" 415 " zvdepi -2, 32, %%r19\n" 416 "1: ldw 0(%%sr1,%3),%%r20\n" 417 "2: ldw 8(%%sr1,%3),%%r21\n" 418 " vshd %1, %2, %%r1\n" 419 " vshd %%r0, %1, %1\n" 420 " vshd %2, %%r0, %2\n" 421 " and %%r20, %%r19, %%r20\n" 422 " andcm %%r21, %%r19, %%r21\n" 423 " or %1, %%r20, %1\n" 424 " or %2, %%r21, %2\n" 425 "3: stw %1,0(%%sr1,%1)\n" 426 "4: stw %%r1,4(%%sr1,%3)\n" 427 "5: stw %2,8(%%sr1,%3)\n" 428 " copy %%r0, %0\n" 429 "6: \n" 430 " .section .fixup,\"ax\"\n" 431 "7: ldi -2, %0\n" 432 FIXUP_BRANCH(6b) 433 " .previous\n" 434 ASM_EXCEPTIONTABLE_ENTRY(1b,7b) 435 ASM_EXCEPTIONTABLE_ENTRY(2b,7b) 436 ASM_EXCEPTIONTABLE_ENTRY(3b,7b) 437 ASM_EXCEPTIONTABLE_ENTRY(4b,7b) 438 ASM_EXCEPTIONTABLE_ENTRY(5b,7b) 439 : "=r" (ret) 440 : "r" (valh), "r" (vall), "r" (regs->ior), "r" (regs->isr) 441 : "r19", "r20", "r21", "r1", FIXUP_BRANCH_CLOBBER ); 442 } 443 #endif 444 445 return ret; 446 } 447 448 void handle_unaligned(struct pt_regs *regs) 449 { 450 static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5); 451 unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0; 452 int modify = 0; 453 int ret = ERR_NOTHANDLED; 454 struct siginfo si; 455 register int flop=0; /* true if this is a flop */ 456 457 __inc_irq_stat(irq_unaligned_count); 458 459 /* log a message with pacing */ 460 if (user_mode(regs)) { 461 if (current->thread.flags & PARISC_UAC_SIGBUS) { 462 goto force_sigbus; 463 } 464 465 if (!(current->thread.flags & PARISC_UAC_NOPRINT) && 466 __ratelimit(&ratelimit)) { 467 char buf[256]; 468 sprintf(buf, "%s(%d): unaligned access to 0x" RFMT " at ip=0x" RFMT "\n", 469 current->comm, task_pid_nr(current), regs->ior, regs->iaoq[0]); 470 printk(KERN_WARNING "%s", buf); 471 #ifdef DEBUG_UNALIGNED 472 show_regs(regs); 473 #endif 474 } 475 476 if (!unaligned_enabled) 477 goto force_sigbus; 478 } 479 480 /* handle modification - OK, it's ugly, see the instruction manual */ 481 switch (MAJOR_OP(regs->iir)) 482 { 483 case 0x03: 484 case 0x09: 485 case 0x0b: 486 if (regs->iir&0x20) 487 { 488 modify = 1; 489 if (regs->iir&0x1000) /* short loads */ 490 if (regs->iir&0x200) 491 newbase += IM5_3(regs->iir); 492 else 493 newbase += IM5_2(regs->iir); 494 else if (regs->iir&0x2000) /* scaled indexed */ 495 { 496 int shift=0; 497 switch (regs->iir & OPCODE1_MASK) 498 { 499 case OPCODE_LDH_I: 500 shift= 1; break; 501 case OPCODE_LDW_I: 502 shift= 2; break; 503 case OPCODE_LDD_I: 504 case OPCODE_LDDA_I: 505 shift= 3; break; 506 } 507 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift; 508 } else /* simple indexed */ 509 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0); 510 } 511 break; 512 case 0x13: 513 case 0x1b: 514 modify = 1; 515 newbase += IM14(regs->iir); 516 break; 517 case 0x14: 518 case 0x1c: 519 if (regs->iir&8) 520 { 521 modify = 1; 522 newbase += IM14(regs->iir&~0xe); 523 } 524 break; 525 case 0x16: 526 case 0x1e: 527 modify = 1; 528 newbase += IM14(regs->iir&6); 529 break; 530 case 0x17: 531 case 0x1f: 532 if (regs->iir&4) 533 { 534 modify = 1; 535 newbase += IM14(regs->iir&~4); 536 } 537 break; 538 } 539 540 /* TODO: make this cleaner... */ 541 switch (regs->iir & OPCODE1_MASK) 542 { 543 case OPCODE_LDH_I: 544 case OPCODE_LDH_S: 545 ret = emulate_ldh(regs, R3(regs->iir)); 546 break; 547 548 case OPCODE_LDW_I: 549 case OPCODE_LDWA_I: 550 case OPCODE_LDW_S: 551 case OPCODE_LDWA_S: 552 ret = emulate_ldw(regs, R3(regs->iir),0); 553 break; 554 555 case OPCODE_STH: 556 ret = emulate_sth(regs, R2(regs->iir)); 557 break; 558 559 case OPCODE_STW: 560 case OPCODE_STWA: 561 ret = emulate_stw(regs, R2(regs->iir),0); 562 break; 563 564 #ifdef CONFIG_PA20 565 case OPCODE_LDD_I: 566 case OPCODE_LDDA_I: 567 case OPCODE_LDD_S: 568 case OPCODE_LDDA_S: 569 ret = emulate_ldd(regs, R3(regs->iir),0); 570 break; 571 572 case OPCODE_STD: 573 case OPCODE_STDA: 574 ret = emulate_std(regs, R2(regs->iir),0); 575 break; 576 #endif 577 578 case OPCODE_FLDWX: 579 case OPCODE_FLDWS: 580 case OPCODE_FLDWXR: 581 case OPCODE_FLDWSR: 582 flop=1; 583 ret = emulate_ldw(regs,FR3(regs->iir),1); 584 break; 585 586 case OPCODE_FLDDX: 587 case OPCODE_FLDDS: 588 flop=1; 589 ret = emulate_ldd(regs,R3(regs->iir),1); 590 break; 591 592 case OPCODE_FSTWX: 593 case OPCODE_FSTWS: 594 case OPCODE_FSTWXR: 595 case OPCODE_FSTWSR: 596 flop=1; 597 ret = emulate_stw(regs,FR3(regs->iir),1); 598 break; 599 600 case OPCODE_FSTDX: 601 case OPCODE_FSTDS: 602 flop=1; 603 ret = emulate_std(regs,R3(regs->iir),1); 604 break; 605 606 case OPCODE_LDCD_I: 607 case OPCODE_LDCW_I: 608 case OPCODE_LDCD_S: 609 case OPCODE_LDCW_S: 610 ret = ERR_NOTHANDLED; /* "undefined", but lets kill them. */ 611 break; 612 } 613 #ifdef CONFIG_PA20 614 switch (regs->iir & OPCODE2_MASK) 615 { 616 case OPCODE_FLDD_L: 617 flop=1; 618 ret = emulate_ldd(regs,R2(regs->iir),1); 619 break; 620 case OPCODE_FSTD_L: 621 flop=1; 622 ret = emulate_std(regs, R2(regs->iir),1); 623 break; 624 case OPCODE_LDD_L: 625 ret = emulate_ldd(regs, R2(regs->iir),0); 626 break; 627 case OPCODE_STD_L: 628 ret = emulate_std(regs, R2(regs->iir),0); 629 break; 630 } 631 #endif 632 switch (regs->iir & OPCODE3_MASK) 633 { 634 case OPCODE_FLDW_L: 635 flop=1; 636 ret = emulate_ldw(regs, R2(regs->iir),0); 637 break; 638 case OPCODE_LDW_M: 639 ret = emulate_ldw(regs, R2(regs->iir),1); 640 break; 641 642 case OPCODE_FSTW_L: 643 flop=1; 644 ret = emulate_stw(regs, R2(regs->iir),1); 645 break; 646 case OPCODE_STW_M: 647 ret = emulate_stw(regs, R2(regs->iir),0); 648 break; 649 } 650 switch (regs->iir & OPCODE4_MASK) 651 { 652 case OPCODE_LDH_L: 653 ret = emulate_ldh(regs, R2(regs->iir)); 654 break; 655 case OPCODE_LDW_L: 656 case OPCODE_LDWM: 657 ret = emulate_ldw(regs, R2(regs->iir),0); 658 break; 659 case OPCODE_STH_L: 660 ret = emulate_sth(regs, R2(regs->iir)); 661 break; 662 case OPCODE_STW_L: 663 case OPCODE_STWM: 664 ret = emulate_stw(regs, R2(regs->iir),0); 665 break; 666 } 667 668 if (ret == 0 && modify && R1(regs->iir)) 669 regs->gr[R1(regs->iir)] = newbase; 670 671 672 if (ret == ERR_NOTHANDLED) 673 printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir); 674 675 DPRINTF("ret = %d\n", ret); 676 677 if (ret) 678 { 679 /* 680 * The unaligned handler failed. 681 * If we were called by __get_user() or __put_user() jump 682 * to it's exception fixup handler instead of crashing. 683 */ 684 if (!user_mode(regs) && fixup_exception(regs)) 685 return; 686 687 printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret); 688 die_if_kernel("Unaligned data reference", regs, 28); 689 690 if (ret == ERR_PAGEFAULT) 691 { 692 si.si_signo = SIGSEGV; 693 si.si_errno = 0; 694 si.si_code = SEGV_MAPERR; 695 si.si_addr = (void __user *)regs->ior; 696 force_sig_info(SIGSEGV, &si, current); 697 } 698 else 699 { 700 force_sigbus: 701 /* couldn't handle it ... */ 702 si.si_signo = SIGBUS; 703 si.si_errno = 0; 704 si.si_code = BUS_ADRALN; 705 si.si_addr = (void __user *)regs->ior; 706 force_sig_info(SIGBUS, &si, current); 707 } 708 709 return; 710 } 711 712 /* else we handled it, let life go on. */ 713 regs->gr[0]|=PSW_N; 714 } 715 716 /* 717 * NB: check_unaligned() is only used for PCXS processors right 718 * now, so we only check for PA1.1 encodings at this point. 719 */ 720 721 int 722 check_unaligned(struct pt_regs *regs) 723 { 724 unsigned long align_mask; 725 726 /* Get alignment mask */ 727 728 align_mask = 0UL; 729 switch (regs->iir & OPCODE1_MASK) { 730 731 case OPCODE_LDH_I: 732 case OPCODE_LDH_S: 733 case OPCODE_STH: 734 align_mask = 1UL; 735 break; 736 737 case OPCODE_LDW_I: 738 case OPCODE_LDWA_I: 739 case OPCODE_LDW_S: 740 case OPCODE_LDWA_S: 741 case OPCODE_STW: 742 case OPCODE_STWA: 743 align_mask = 3UL; 744 break; 745 746 default: 747 switch (regs->iir & OPCODE4_MASK) { 748 case OPCODE_LDH_L: 749 case OPCODE_STH_L: 750 align_mask = 1UL; 751 break; 752 case OPCODE_LDW_L: 753 case OPCODE_LDWM: 754 case OPCODE_STW_L: 755 case OPCODE_STWM: 756 align_mask = 3UL; 757 break; 758 } 759 break; 760 } 761 762 return (int)(regs->ior & align_mask); 763 } 764 765