1 /* 2 * linux/arch/parisc/kernel/time.c 3 * 4 * Copyright (C) 1991, 1992, 1995 Linus Torvalds 5 * Modifications for ARM (C) 1994, 1995, 1996,1997 Russell King 6 * Copyright (C) 1999 SuSE GmbH, (Philipp Rumpf, prumpf@tux.org) 7 * 8 * 1994-07-02 Alan Modra 9 * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime 10 * 1998-12-20 Updated NTP code according to technical memorandum Jan '96 11 * "A Kernel Model for Precision Timekeeping" by Dave Mills 12 */ 13 #include <linux/errno.h> 14 #include <linux/module.h> 15 #include <linux/sched.h> 16 #include <linux/kernel.h> 17 #include <linux/param.h> 18 #include <linux/string.h> 19 #include <linux/mm.h> 20 #include <linux/interrupt.h> 21 #include <linux/time.h> 22 #include <linux/init.h> 23 #include <linux/smp.h> 24 #include <linux/profile.h> 25 #include <linux/clocksource.h> 26 #include <linux/platform_device.h> 27 28 #include <asm/uaccess.h> 29 #include <asm/io.h> 30 #include <asm/irq.h> 31 #include <asm/param.h> 32 #include <asm/pdc.h> 33 #include <asm/led.h> 34 35 #include <linux/timex.h> 36 37 static unsigned long clocktick __read_mostly; /* timer cycles per tick */ 38 39 /* 40 * We keep time on PA-RISC Linux by using the Interval Timer which is 41 * a pair of registers; one is read-only and one is write-only; both 42 * accessed through CR16. The read-only register is 32 or 64 bits wide, 43 * and increments by 1 every CPU clock tick. The architecture only 44 * guarantees us a rate between 0.5 and 2, but all implementations use a 45 * rate of 1. The write-only register is 32-bits wide. When the lowest 46 * 32 bits of the read-only register compare equal to the write-only 47 * register, it raises a maskable external interrupt. Each processor has 48 * an Interval Timer of its own and they are not synchronised. 49 * 50 * We want to generate an interrupt every 1/HZ seconds. So we program 51 * CR16 to interrupt every @clocktick cycles. The it_value in cpu_data 52 * is programmed with the intended time of the next tick. We can be 53 * held off for an arbitrarily long period of time by interrupts being 54 * disabled, so we may miss one or more ticks. 55 */ 56 irqreturn_t timer_interrupt(int irq, void *dev_id) 57 { 58 unsigned long now; 59 unsigned long next_tick; 60 unsigned long cycles_elapsed, ticks_elapsed; 61 unsigned long cycles_remainder; 62 unsigned int cpu = smp_processor_id(); 63 struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu); 64 65 /* gcc can optimize for "read-only" case with a local clocktick */ 66 unsigned long cpt = clocktick; 67 68 profile_tick(CPU_PROFILING); 69 70 /* Initialize next_tick to the expected tick time. */ 71 next_tick = cpuinfo->it_value; 72 73 /* Get current interval timer. 74 * CR16 reads as 64 bits in CPU wide mode. 75 * CR16 reads as 32 bits in CPU narrow mode. 76 */ 77 now = mfctl(16); 78 79 cycles_elapsed = now - next_tick; 80 81 if ((cycles_elapsed >> 5) < cpt) { 82 /* use "cheap" math (add/subtract) instead 83 * of the more expensive div/mul method 84 */ 85 cycles_remainder = cycles_elapsed; 86 ticks_elapsed = 1; 87 while (cycles_remainder > cpt) { 88 cycles_remainder -= cpt; 89 ticks_elapsed++; 90 } 91 } else { 92 cycles_remainder = cycles_elapsed % cpt; 93 ticks_elapsed = 1 + cycles_elapsed / cpt; 94 } 95 96 /* Can we differentiate between "early CR16" (aka Scenario 1) and 97 * "long delay" (aka Scenario 3)? I don't think so. 98 * 99 * We expected timer_interrupt to be delivered at least a few hundred 100 * cycles after the IT fires. But it's arbitrary how much time passes 101 * before we call it "late". I've picked one second. 102 */ 103 if (unlikely(ticks_elapsed > HZ)) { 104 /* Scenario 3: very long delay? bad in any case */ 105 printk (KERN_CRIT "timer_interrupt(CPU %d): delayed!" 106 " cycles %lX rem %lX " 107 " next/now %lX/%lX\n", 108 cpu, 109 cycles_elapsed, cycles_remainder, 110 next_tick, now ); 111 } 112 113 /* convert from "division remainder" to "remainder of clock tick" */ 114 cycles_remainder = cpt - cycles_remainder; 115 116 /* Determine when (in CR16 cycles) next IT interrupt will fire. 117 * We want IT to fire modulo clocktick even if we miss/skip some. 118 * But those interrupts don't in fact get delivered that regularly. 119 */ 120 next_tick = now + cycles_remainder; 121 122 cpuinfo->it_value = next_tick; 123 124 /* Skip one clocktick on purpose if we are likely to miss next_tick. 125 * We want to avoid the new next_tick being less than CR16. 126 * If that happened, itimer wouldn't fire until CR16 wrapped. 127 * We'll catch the tick we missed on the tick after that. 128 */ 129 if (!(cycles_remainder >> 13)) 130 next_tick += cpt; 131 132 /* Program the IT when to deliver the next interrupt. */ 133 /* Only bottom 32-bits of next_tick are written to cr16. */ 134 mtctl(next_tick, 16); 135 136 137 /* Done mucking with unreliable delivery of interrupts. 138 * Go do system house keeping. 139 */ 140 141 if (!--cpuinfo->prof_counter) { 142 cpuinfo->prof_counter = cpuinfo->prof_multiplier; 143 update_process_times(user_mode(get_irq_regs())); 144 } 145 146 if (cpu == 0) { 147 write_seqlock(&xtime_lock); 148 do_timer(ticks_elapsed); 149 write_sequnlock(&xtime_lock); 150 } 151 152 return IRQ_HANDLED; 153 } 154 155 156 unsigned long profile_pc(struct pt_regs *regs) 157 { 158 unsigned long pc = instruction_pointer(regs); 159 160 if (regs->gr[0] & PSW_N) 161 pc -= 4; 162 163 #ifdef CONFIG_SMP 164 if (in_lock_functions(pc)) 165 pc = regs->gr[2]; 166 #endif 167 168 return pc; 169 } 170 EXPORT_SYMBOL(profile_pc); 171 172 173 /* clock source code */ 174 175 static cycle_t read_cr16(void) 176 { 177 return get_cycles(); 178 } 179 180 static struct clocksource clocksource_cr16 = { 181 .name = "cr16", 182 .rating = 300, 183 .read = read_cr16, 184 .mask = CLOCKSOURCE_MASK(BITS_PER_LONG), 185 .mult = 0, /* to be set */ 186 .shift = 22, 187 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 188 }; 189 190 #ifdef CONFIG_SMP 191 int update_cr16_clocksource(void) 192 { 193 /* since the cr16 cycle counters are not synchronized across CPUs, 194 we'll check if we should switch to a safe clocksource: */ 195 if (clocksource_cr16.rating != 0 && num_online_cpus() > 1) { 196 clocksource_change_rating(&clocksource_cr16, 0); 197 return 1; 198 } 199 200 return 0; 201 } 202 #else 203 int update_cr16_clocksource(void) 204 { 205 return 0; /* no change */ 206 } 207 #endif /*CONFIG_SMP*/ 208 209 void __init start_cpu_itimer(void) 210 { 211 unsigned int cpu = smp_processor_id(); 212 unsigned long next_tick = mfctl(16) + clocktick; 213 214 mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */ 215 216 per_cpu(cpu_data, cpu).it_value = next_tick; 217 } 218 219 static struct platform_device rtc_parisc_dev = { 220 .name = "rtc-parisc", 221 .id = -1, 222 }; 223 224 static int __init rtc_init(void) 225 { 226 if (platform_device_register(&rtc_parisc_dev) < 0) 227 printk(KERN_ERR "unable to register rtc device...\n"); 228 229 /* not necessarily an error */ 230 return 0; 231 } 232 module_init(rtc_init); 233 234 void __init time_init(void) 235 { 236 static struct pdc_tod tod_data; 237 unsigned long current_cr16_khz; 238 239 clocktick = (100 * PAGE0->mem_10msec) / HZ; 240 241 start_cpu_itimer(); /* get CPU 0 started */ 242 243 /* register at clocksource framework */ 244 current_cr16_khz = PAGE0->mem_10msec/10; /* kHz */ 245 clocksource_cr16.mult = clocksource_khz2mult(current_cr16_khz, 246 clocksource_cr16.shift); 247 clocksource_register(&clocksource_cr16); 248 249 if (pdc_tod_read(&tod_data) == 0) { 250 unsigned long flags; 251 252 write_seqlock_irqsave(&xtime_lock, flags); 253 xtime.tv_sec = tod_data.tod_sec; 254 xtime.tv_nsec = tod_data.tod_usec * 1000; 255 set_normalized_timespec(&wall_to_monotonic, 256 -xtime.tv_sec, -xtime.tv_nsec); 257 write_sequnlock_irqrestore(&xtime_lock, flags); 258 } else { 259 printk(KERN_ERR "Error reading tod clock\n"); 260 xtime.tv_sec = 0; 261 xtime.tv_nsec = 0; 262 } 263 } 264