1 /* 2 * linux/arch/parisc/kernel/time.c 3 * 4 * Copyright (C) 1991, 1992, 1995 Linus Torvalds 5 * Modifications for ARM (C) 1994, 1995, 1996,1997 Russell King 6 * Copyright (C) 1999 SuSE GmbH, (Philipp Rumpf, prumpf@tux.org) 7 * 8 * 1994-07-02 Alan Modra 9 * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime 10 * 1998-12-20 Updated NTP code according to technical memorandum Jan '96 11 * "A Kernel Model for Precision Timekeeping" by Dave Mills 12 */ 13 #include <linux/errno.h> 14 #include <linux/module.h> 15 #include <linux/sched.h> 16 #include <linux/kernel.h> 17 #include <linux/param.h> 18 #include <linux/string.h> 19 #include <linux/mm.h> 20 #include <linux/interrupt.h> 21 #include <linux/time.h> 22 #include <linux/init.h> 23 #include <linux/smp.h> 24 #include <linux/profile.h> 25 #include <linux/clocksource.h> 26 #include <linux/platform_device.h> 27 #include <linux/ftrace.h> 28 29 #include <asm/uaccess.h> 30 #include <asm/io.h> 31 #include <asm/irq.h> 32 #include <asm/page.h> 33 #include <asm/param.h> 34 #include <asm/pdc.h> 35 #include <asm/led.h> 36 37 #include <linux/timex.h> 38 39 static unsigned long clocktick __read_mostly; /* timer cycles per tick */ 40 41 /* 42 * We keep time on PA-RISC Linux by using the Interval Timer which is 43 * a pair of registers; one is read-only and one is write-only; both 44 * accessed through CR16. The read-only register is 32 or 64 bits wide, 45 * and increments by 1 every CPU clock tick. The architecture only 46 * guarantees us a rate between 0.5 and 2, but all implementations use a 47 * rate of 1. The write-only register is 32-bits wide. When the lowest 48 * 32 bits of the read-only register compare equal to the write-only 49 * register, it raises a maskable external interrupt. Each processor has 50 * an Interval Timer of its own and they are not synchronised. 51 * 52 * We want to generate an interrupt every 1/HZ seconds. So we program 53 * CR16 to interrupt every @clocktick cycles. The it_value in cpu_data 54 * is programmed with the intended time of the next tick. We can be 55 * held off for an arbitrarily long period of time by interrupts being 56 * disabled, so we may miss one or more ticks. 57 */ 58 irqreturn_t __irq_entry timer_interrupt(int irq, void *dev_id) 59 { 60 unsigned long now, now2; 61 unsigned long next_tick; 62 unsigned long cycles_elapsed, ticks_elapsed = 1; 63 unsigned long cycles_remainder; 64 unsigned int cpu = smp_processor_id(); 65 struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu); 66 67 /* gcc can optimize for "read-only" case with a local clocktick */ 68 unsigned long cpt = clocktick; 69 70 profile_tick(CPU_PROFILING); 71 72 /* Initialize next_tick to the expected tick time. */ 73 next_tick = cpuinfo->it_value; 74 75 /* Get current cycle counter (Control Register 16). */ 76 now = mfctl(16); 77 78 cycles_elapsed = now - next_tick; 79 80 if ((cycles_elapsed >> 6) < cpt) { 81 /* use "cheap" math (add/subtract) instead 82 * of the more expensive div/mul method 83 */ 84 cycles_remainder = cycles_elapsed; 85 while (cycles_remainder > cpt) { 86 cycles_remainder -= cpt; 87 ticks_elapsed++; 88 } 89 } else { 90 /* TODO: Reduce this to one fdiv op */ 91 cycles_remainder = cycles_elapsed % cpt; 92 ticks_elapsed += cycles_elapsed / cpt; 93 } 94 95 /* convert from "division remainder" to "remainder of clock tick" */ 96 cycles_remainder = cpt - cycles_remainder; 97 98 /* Determine when (in CR16 cycles) next IT interrupt will fire. 99 * We want IT to fire modulo clocktick even if we miss/skip some. 100 * But those interrupts don't in fact get delivered that regularly. 101 */ 102 next_tick = now + cycles_remainder; 103 104 cpuinfo->it_value = next_tick; 105 106 /* Program the IT when to deliver the next interrupt. 107 * Only bottom 32-bits of next_tick are writable in CR16! 108 */ 109 mtctl(next_tick, 16); 110 111 /* Skip one clocktick on purpose if we missed next_tick. 112 * The new CR16 must be "later" than current CR16 otherwise 113 * itimer would not fire until CR16 wrapped - e.g 4 seconds 114 * later on a 1Ghz processor. We'll account for the missed 115 * tick on the next timer interrupt. 116 * 117 * "next_tick - now" will always give the difference regardless 118 * if one or the other wrapped. If "now" is "bigger" we'll end up 119 * with a very large unsigned number. 120 */ 121 now2 = mfctl(16); 122 if (next_tick - now2 > cpt) 123 mtctl(next_tick+cpt, 16); 124 125 #if 1 126 /* 127 * GGG: DEBUG code for how many cycles programming CR16 used. 128 */ 129 if (unlikely(now2 - now > 0x3000)) /* 12K cycles */ 130 printk (KERN_CRIT "timer_interrupt(CPU %d): SLOW! 0x%lx cycles!" 131 " cyc %lX rem %lX " 132 " next/now %lX/%lX\n", 133 cpu, now2 - now, cycles_elapsed, cycles_remainder, 134 next_tick, now ); 135 #endif 136 137 /* Can we differentiate between "early CR16" (aka Scenario 1) and 138 * "long delay" (aka Scenario 3)? I don't think so. 139 * 140 * Timer_interrupt will be delivered at least a few hundred cycles 141 * after the IT fires. But it's arbitrary how much time passes 142 * before we call it "late". I've picked one second. 143 * 144 * It's important NO printk's are between reading CR16 and 145 * setting up the next value. May introduce huge variance. 146 */ 147 if (unlikely(ticks_elapsed > HZ)) { 148 /* Scenario 3: very long delay? bad in any case */ 149 printk (KERN_CRIT "timer_interrupt(CPU %d): delayed!" 150 " cycles %lX rem %lX " 151 " next/now %lX/%lX\n", 152 cpu, 153 cycles_elapsed, cycles_remainder, 154 next_tick, now ); 155 } 156 157 /* Done mucking with unreliable delivery of interrupts. 158 * Go do system house keeping. 159 */ 160 161 if (!--cpuinfo->prof_counter) { 162 cpuinfo->prof_counter = cpuinfo->prof_multiplier; 163 update_process_times(user_mode(get_irq_regs())); 164 } 165 166 if (cpu == 0) 167 xtime_update(ticks_elapsed); 168 169 return IRQ_HANDLED; 170 } 171 172 173 unsigned long profile_pc(struct pt_regs *regs) 174 { 175 unsigned long pc = instruction_pointer(regs); 176 177 if (regs->gr[0] & PSW_N) 178 pc -= 4; 179 180 #ifdef CONFIG_SMP 181 if (in_lock_functions(pc)) 182 pc = regs->gr[2]; 183 #endif 184 185 return pc; 186 } 187 EXPORT_SYMBOL(profile_pc); 188 189 190 /* clock source code */ 191 192 static cycle_t read_cr16(struct clocksource *cs) 193 { 194 return get_cycles(); 195 } 196 197 static struct clocksource clocksource_cr16 = { 198 .name = "cr16", 199 .rating = 300, 200 .read = read_cr16, 201 .mask = CLOCKSOURCE_MASK(BITS_PER_LONG), 202 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 203 }; 204 205 #ifdef CONFIG_SMP 206 int update_cr16_clocksource(void) 207 { 208 /* since the cr16 cycle counters are not synchronized across CPUs, 209 we'll check if we should switch to a safe clocksource: */ 210 if (clocksource_cr16.rating != 0 && num_online_cpus() > 1) { 211 clocksource_change_rating(&clocksource_cr16, 0); 212 return 1; 213 } 214 215 return 0; 216 } 217 #else 218 int update_cr16_clocksource(void) 219 { 220 return 0; /* no change */ 221 } 222 #endif /*CONFIG_SMP*/ 223 224 void __init start_cpu_itimer(void) 225 { 226 unsigned int cpu = smp_processor_id(); 227 unsigned long next_tick = mfctl(16) + clocktick; 228 229 mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */ 230 231 per_cpu(cpu_data, cpu).it_value = next_tick; 232 } 233 234 static struct platform_device rtc_generic_dev = { 235 .name = "rtc-generic", 236 .id = -1, 237 }; 238 239 static int __init rtc_init(void) 240 { 241 if (platform_device_register(&rtc_generic_dev) < 0) 242 printk(KERN_ERR "unable to register rtc device...\n"); 243 244 /* not necessarily an error */ 245 return 0; 246 } 247 module_init(rtc_init); 248 249 void read_persistent_clock(struct timespec *ts) 250 { 251 static struct pdc_tod tod_data; 252 if (pdc_tod_read(&tod_data) == 0) { 253 ts->tv_sec = tod_data.tod_sec; 254 ts->tv_nsec = tod_data.tod_usec * 1000; 255 } else { 256 printk(KERN_ERR "Error reading tod clock\n"); 257 ts->tv_sec = 0; 258 ts->tv_nsec = 0; 259 } 260 } 261 262 void __init time_init(void) 263 { 264 unsigned long current_cr16_khz; 265 266 clocktick = (100 * PAGE0->mem_10msec) / HZ; 267 268 start_cpu_itimer(); /* get CPU 0 started */ 269 270 /* register at clocksource framework */ 271 current_cr16_khz = PAGE0->mem_10msec/10; /* kHz */ 272 clocksource_register_khz(&clocksource_cr16, current_cr16_khz); 273 } 274