1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * linux/arch/parisc/kernel/time.c 4 * 5 * Copyright (C) 1991, 1992, 1995 Linus Torvalds 6 * Modifications for ARM (C) 1994, 1995, 1996,1997 Russell King 7 * Copyright (C) 1999 SuSE GmbH, (Philipp Rumpf, prumpf@tux.org) 8 * 9 * 1994-07-02 Alan Modra 10 * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime 11 * 1998-12-20 Updated NTP code according to technical memorandum Jan '96 12 * "A Kernel Model for Precision Timekeeping" by Dave Mills 13 */ 14 #include <linux/errno.h> 15 #include <linux/module.h> 16 #include <linux/rtc.h> 17 #include <linux/sched.h> 18 #include <linux/sched/clock.h> 19 #include <linux/sched_clock.h> 20 #include <linux/kernel.h> 21 #include <linux/param.h> 22 #include <linux/string.h> 23 #include <linux/mm.h> 24 #include <linux/interrupt.h> 25 #include <linux/time.h> 26 #include <linux/init.h> 27 #include <linux/smp.h> 28 #include <linux/profile.h> 29 #include <linux/clocksource.h> 30 #include <linux/platform_device.h> 31 #include <linux/ftrace.h> 32 33 #include <linux/uaccess.h> 34 #include <asm/io.h> 35 #include <asm/irq.h> 36 #include <asm/page.h> 37 #include <asm/param.h> 38 #include <asm/pdc.h> 39 #include <asm/led.h> 40 41 #include <linux/timex.h> 42 43 static unsigned long clocktick __ro_after_init; /* timer cycles per tick */ 44 45 /* 46 * We keep time on PA-RISC Linux by using the Interval Timer which is 47 * a pair of registers; one is read-only and one is write-only; both 48 * accessed through CR16. The read-only register is 32 or 64 bits wide, 49 * and increments by 1 every CPU clock tick. The architecture only 50 * guarantees us a rate between 0.5 and 2, but all implementations use a 51 * rate of 1. The write-only register is 32-bits wide. When the lowest 52 * 32 bits of the read-only register compare equal to the write-only 53 * register, it raises a maskable external interrupt. Each processor has 54 * an Interval Timer of its own and they are not synchronised. 55 * 56 * We want to generate an interrupt every 1/HZ seconds. So we program 57 * CR16 to interrupt every @clocktick cycles. The it_value in cpu_data 58 * is programmed with the intended time of the next tick. We can be 59 * held off for an arbitrarily long period of time by interrupts being 60 * disabled, so we may miss one or more ticks. 61 */ 62 irqreturn_t __irq_entry timer_interrupt(int irq, void *dev_id) 63 { 64 unsigned long now; 65 unsigned long next_tick; 66 unsigned long ticks_elapsed = 0; 67 unsigned int cpu = smp_processor_id(); 68 struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu); 69 70 /* gcc can optimize for "read-only" case with a local clocktick */ 71 unsigned long cpt = clocktick; 72 73 /* Initialize next_tick to the old expected tick time. */ 74 next_tick = cpuinfo->it_value; 75 76 /* Calculate how many ticks have elapsed. */ 77 now = mfctl(16); 78 do { 79 ++ticks_elapsed; 80 next_tick += cpt; 81 } while (next_tick - now > cpt); 82 83 /* Store (in CR16 cycles) up to when we are accounting right now. */ 84 cpuinfo->it_value = next_tick; 85 86 /* Go do system house keeping. */ 87 if (cpu != 0) 88 ticks_elapsed = 0; 89 legacy_timer_tick(ticks_elapsed); 90 91 /* Skip clockticks on purpose if we know we would miss those. 92 * The new CR16 must be "later" than current CR16 otherwise 93 * itimer would not fire until CR16 wrapped - e.g 4 seconds 94 * later on a 1Ghz processor. We'll account for the missed 95 * ticks on the next timer interrupt. 96 * We want IT to fire modulo clocktick even if we miss/skip some. 97 * But those interrupts don't in fact get delivered that regularly. 98 * 99 * "next_tick - now" will always give the difference regardless 100 * if one or the other wrapped. If "now" is "bigger" we'll end up 101 * with a very large unsigned number. 102 */ 103 now = mfctl(16); 104 while (next_tick - now > cpt) 105 next_tick += cpt; 106 107 /* Program the IT when to deliver the next interrupt. 108 * Only bottom 32-bits of next_tick are writable in CR16! 109 * Timer interrupt will be delivered at least a few hundred cycles 110 * after the IT fires, so if we are too close (<= 8000 cycles) to the 111 * next cycle, simply skip it. 112 */ 113 if (next_tick - now <= 8000) 114 next_tick += cpt; 115 mtctl(next_tick, 16); 116 117 return IRQ_HANDLED; 118 } 119 120 121 unsigned long profile_pc(struct pt_regs *regs) 122 { 123 unsigned long pc = instruction_pointer(regs); 124 125 if (regs->gr[0] & PSW_N) 126 pc -= 4; 127 128 #ifdef CONFIG_SMP 129 if (in_lock_functions(pc)) 130 pc = regs->gr[2]; 131 #endif 132 133 return pc; 134 } 135 EXPORT_SYMBOL(profile_pc); 136 137 138 /* clock source code */ 139 140 static u64 notrace read_cr16(struct clocksource *cs) 141 { 142 return get_cycles(); 143 } 144 145 static struct clocksource clocksource_cr16 = { 146 .name = "cr16", 147 .rating = 300, 148 .read = read_cr16, 149 .mask = CLOCKSOURCE_MASK(BITS_PER_LONG), 150 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 151 }; 152 153 void __init start_cpu_itimer(void) 154 { 155 unsigned int cpu = smp_processor_id(); 156 unsigned long next_tick = mfctl(16) + clocktick; 157 158 mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */ 159 160 per_cpu(cpu_data, cpu).it_value = next_tick; 161 } 162 163 #if IS_ENABLED(CONFIG_RTC_DRV_GENERIC) 164 static int rtc_generic_get_time(struct device *dev, struct rtc_time *tm) 165 { 166 struct pdc_tod tod_data; 167 168 memset(tm, 0, sizeof(*tm)); 169 if (pdc_tod_read(&tod_data) < 0) 170 return -EOPNOTSUPP; 171 172 /* we treat tod_sec as unsigned, so this can work until year 2106 */ 173 rtc_time64_to_tm(tod_data.tod_sec, tm); 174 return 0; 175 } 176 177 static int rtc_generic_set_time(struct device *dev, struct rtc_time *tm) 178 { 179 time64_t secs = rtc_tm_to_time64(tm); 180 int ret; 181 182 /* hppa has Y2K38 problem: pdc_tod_set() takes an u32 value! */ 183 ret = pdc_tod_set(secs, 0); 184 if (ret != 0) { 185 pr_warn("pdc_tod_set(%lld) returned error %d\n", secs, ret); 186 if (ret == PDC_INVALID_ARG) 187 return -EINVAL; 188 return -EOPNOTSUPP; 189 } 190 191 return 0; 192 } 193 194 static const struct rtc_class_ops rtc_generic_ops = { 195 .read_time = rtc_generic_get_time, 196 .set_time = rtc_generic_set_time, 197 }; 198 199 static int __init rtc_init(void) 200 { 201 struct platform_device *pdev; 202 203 pdev = platform_device_register_data(NULL, "rtc-generic", -1, 204 &rtc_generic_ops, 205 sizeof(rtc_generic_ops)); 206 207 return PTR_ERR_OR_ZERO(pdev); 208 } 209 device_initcall(rtc_init); 210 #endif 211 212 void read_persistent_clock64(struct timespec64 *ts) 213 { 214 static struct pdc_tod tod_data; 215 if (pdc_tod_read(&tod_data) == 0) { 216 ts->tv_sec = tod_data.tod_sec; 217 ts->tv_nsec = tod_data.tod_usec * 1000; 218 } else { 219 printk(KERN_ERR "Error reading tod clock\n"); 220 ts->tv_sec = 0; 221 ts->tv_nsec = 0; 222 } 223 } 224 225 226 static u64 notrace read_cr16_sched_clock(void) 227 { 228 return get_cycles(); 229 } 230 231 232 /* 233 * timer interrupt and sched_clock() initialization 234 */ 235 236 void __init time_init(void) 237 { 238 unsigned long cr16_hz; 239 240 clocktick = (100 * PAGE0->mem_10msec) / HZ; 241 start_cpu_itimer(); /* get CPU 0 started */ 242 243 cr16_hz = 100 * PAGE0->mem_10msec; /* Hz */ 244 245 /* register as sched_clock source */ 246 sched_clock_register(read_cr16_sched_clock, BITS_PER_LONG, cr16_hz); 247 } 248 249 static int __init init_cr16_clocksource(void) 250 { 251 /* 252 * The cr16 interval timers are not syncronized across CPUs on 253 * different sockets, so mark them unstable and lower rating on 254 * multi-socket SMP systems. 255 */ 256 if (num_online_cpus() > 1 && !running_on_qemu) { 257 int cpu; 258 unsigned long cpu0_loc; 259 cpu0_loc = per_cpu(cpu_data, 0).cpu_loc; 260 261 for_each_online_cpu(cpu) { 262 if (cpu == 0) 263 continue; 264 if ((cpu0_loc != 0) && 265 (cpu0_loc == per_cpu(cpu_data, cpu).cpu_loc)) 266 continue; 267 268 clocksource_cr16.name = "cr16_unstable"; 269 clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE; 270 clocksource_cr16.rating = 0; 271 break; 272 } 273 } 274 275 /* XXX: We may want to mark sched_clock stable here if cr16 clocks are 276 * in sync: 277 * (clocksource_cr16.flags == CLOCK_SOURCE_IS_CONTINUOUS) */ 278 279 /* register at clocksource framework */ 280 clocksource_register_hz(&clocksource_cr16, 281 100 * PAGE0->mem_10msec); 282 283 return 0; 284 } 285 286 device_initcall(init_cr16_clocksource); 287