1 /* 2 * linux/arch/parisc/kernel/time.c 3 * 4 * Copyright (C) 1991, 1992, 1995 Linus Torvalds 5 * Modifications for ARM (C) 1994, 1995, 1996,1997 Russell King 6 * Copyright (C) 1999 SuSE GmbH, (Philipp Rumpf, prumpf@tux.org) 7 * 8 * 1994-07-02 Alan Modra 9 * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime 10 * 1998-12-20 Updated NTP code according to technical memorandum Jan '96 11 * "A Kernel Model for Precision Timekeeping" by Dave Mills 12 */ 13 #include <linux/errno.h> 14 #include <linux/module.h> 15 #include <linux/sched.h> 16 #include <linux/kernel.h> 17 #include <linux/param.h> 18 #include <linux/string.h> 19 #include <linux/mm.h> 20 #include <linux/interrupt.h> 21 #include <linux/time.h> 22 #include <linux/init.h> 23 #include <linux/smp.h> 24 #include <linux/profile.h> 25 #include <linux/clocksource.h> 26 #include <linux/platform_device.h> 27 #include <linux/ftrace.h> 28 29 #include <asm/uaccess.h> 30 #include <asm/io.h> 31 #include <asm/irq.h> 32 #include <asm/param.h> 33 #include <asm/pdc.h> 34 #include <asm/led.h> 35 36 #include <linux/timex.h> 37 38 static unsigned long clocktick __read_mostly; /* timer cycles per tick */ 39 40 /* 41 * We keep time on PA-RISC Linux by using the Interval Timer which is 42 * a pair of registers; one is read-only and one is write-only; both 43 * accessed through CR16. The read-only register is 32 or 64 bits wide, 44 * and increments by 1 every CPU clock tick. The architecture only 45 * guarantees us a rate between 0.5 and 2, but all implementations use a 46 * rate of 1. The write-only register is 32-bits wide. When the lowest 47 * 32 bits of the read-only register compare equal to the write-only 48 * register, it raises a maskable external interrupt. Each processor has 49 * an Interval Timer of its own and they are not synchronised. 50 * 51 * We want to generate an interrupt every 1/HZ seconds. So we program 52 * CR16 to interrupt every @clocktick cycles. The it_value in cpu_data 53 * is programmed with the intended time of the next tick. We can be 54 * held off for an arbitrarily long period of time by interrupts being 55 * disabled, so we may miss one or more ticks. 56 */ 57 irqreturn_t __irq_entry timer_interrupt(int irq, void *dev_id) 58 { 59 unsigned long now; 60 unsigned long next_tick; 61 unsigned long cycles_elapsed, ticks_elapsed; 62 unsigned long cycles_remainder; 63 unsigned int cpu = smp_processor_id(); 64 struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu); 65 66 /* gcc can optimize for "read-only" case with a local clocktick */ 67 unsigned long cpt = clocktick; 68 69 profile_tick(CPU_PROFILING); 70 71 /* Initialize next_tick to the expected tick time. */ 72 next_tick = cpuinfo->it_value; 73 74 /* Get current interval timer. 75 * CR16 reads as 64 bits in CPU wide mode. 76 * CR16 reads as 32 bits in CPU narrow mode. 77 */ 78 now = mfctl(16); 79 80 cycles_elapsed = now - next_tick; 81 82 if ((cycles_elapsed >> 5) < cpt) { 83 /* use "cheap" math (add/subtract) instead 84 * of the more expensive div/mul method 85 */ 86 cycles_remainder = cycles_elapsed; 87 ticks_elapsed = 1; 88 while (cycles_remainder > cpt) { 89 cycles_remainder -= cpt; 90 ticks_elapsed++; 91 } 92 } else { 93 cycles_remainder = cycles_elapsed % cpt; 94 ticks_elapsed = 1 + cycles_elapsed / cpt; 95 } 96 97 /* Can we differentiate between "early CR16" (aka Scenario 1) and 98 * "long delay" (aka Scenario 3)? I don't think so. 99 * 100 * We expected timer_interrupt to be delivered at least a few hundred 101 * cycles after the IT fires. But it's arbitrary how much time passes 102 * before we call it "late". I've picked one second. 103 */ 104 if (unlikely(ticks_elapsed > HZ)) { 105 /* Scenario 3: very long delay? bad in any case */ 106 printk (KERN_CRIT "timer_interrupt(CPU %d): delayed!" 107 " cycles %lX rem %lX " 108 " next/now %lX/%lX\n", 109 cpu, 110 cycles_elapsed, cycles_remainder, 111 next_tick, now ); 112 } 113 114 /* convert from "division remainder" to "remainder of clock tick" */ 115 cycles_remainder = cpt - cycles_remainder; 116 117 /* Determine when (in CR16 cycles) next IT interrupt will fire. 118 * We want IT to fire modulo clocktick even if we miss/skip some. 119 * But those interrupts don't in fact get delivered that regularly. 120 */ 121 next_tick = now + cycles_remainder; 122 123 cpuinfo->it_value = next_tick; 124 125 /* Skip one clocktick on purpose if we are likely to miss next_tick. 126 * We want to avoid the new next_tick being less than CR16. 127 * If that happened, itimer wouldn't fire until CR16 wrapped. 128 * We'll catch the tick we missed on the tick after that. 129 */ 130 if (!(cycles_remainder >> 13)) 131 next_tick += cpt; 132 133 /* Program the IT when to deliver the next interrupt. */ 134 /* Only bottom 32-bits of next_tick are written to cr16. */ 135 mtctl(next_tick, 16); 136 137 138 /* Done mucking with unreliable delivery of interrupts. 139 * Go do system house keeping. 140 */ 141 142 if (!--cpuinfo->prof_counter) { 143 cpuinfo->prof_counter = cpuinfo->prof_multiplier; 144 update_process_times(user_mode(get_irq_regs())); 145 } 146 147 if (cpu == 0) { 148 write_seqlock(&xtime_lock); 149 do_timer(ticks_elapsed); 150 write_sequnlock(&xtime_lock); 151 } 152 153 return IRQ_HANDLED; 154 } 155 156 157 unsigned long profile_pc(struct pt_regs *regs) 158 { 159 unsigned long pc = instruction_pointer(regs); 160 161 if (regs->gr[0] & PSW_N) 162 pc -= 4; 163 164 #ifdef CONFIG_SMP 165 if (in_lock_functions(pc)) 166 pc = regs->gr[2]; 167 #endif 168 169 return pc; 170 } 171 EXPORT_SYMBOL(profile_pc); 172 173 174 /* clock source code */ 175 176 static cycle_t read_cr16(void) 177 { 178 return get_cycles(); 179 } 180 181 static struct clocksource clocksource_cr16 = { 182 .name = "cr16", 183 .rating = 300, 184 .read = read_cr16, 185 .mask = CLOCKSOURCE_MASK(BITS_PER_LONG), 186 .mult = 0, /* to be set */ 187 .shift = 22, 188 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 189 }; 190 191 #ifdef CONFIG_SMP 192 int update_cr16_clocksource(void) 193 { 194 /* since the cr16 cycle counters are not synchronized across CPUs, 195 we'll check if we should switch to a safe clocksource: */ 196 if (clocksource_cr16.rating != 0 && num_online_cpus() > 1) { 197 clocksource_change_rating(&clocksource_cr16, 0); 198 return 1; 199 } 200 201 return 0; 202 } 203 #else 204 int update_cr16_clocksource(void) 205 { 206 return 0; /* no change */ 207 } 208 #endif /*CONFIG_SMP*/ 209 210 void __init start_cpu_itimer(void) 211 { 212 unsigned int cpu = smp_processor_id(); 213 unsigned long next_tick = mfctl(16) + clocktick; 214 215 mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */ 216 217 per_cpu(cpu_data, cpu).it_value = next_tick; 218 } 219 220 static struct platform_device rtc_generic_dev = { 221 .name = "rtc-generic", 222 .id = -1, 223 }; 224 225 static int __init rtc_init(void) 226 { 227 if (platform_device_register(&rtc_generic_dev) < 0) 228 printk(KERN_ERR "unable to register rtc device...\n"); 229 230 /* not necessarily an error */ 231 return 0; 232 } 233 module_init(rtc_init); 234 235 void __init time_init(void) 236 { 237 static struct pdc_tod tod_data; 238 unsigned long current_cr16_khz; 239 240 clocktick = (100 * PAGE0->mem_10msec) / HZ; 241 242 start_cpu_itimer(); /* get CPU 0 started */ 243 244 /* register at clocksource framework */ 245 current_cr16_khz = PAGE0->mem_10msec/10; /* kHz */ 246 clocksource_cr16.mult = clocksource_khz2mult(current_cr16_khz, 247 clocksource_cr16.shift); 248 clocksource_register(&clocksource_cr16); 249 250 if (pdc_tod_read(&tod_data) == 0) { 251 unsigned long flags; 252 253 write_seqlock_irqsave(&xtime_lock, flags); 254 xtime.tv_sec = tod_data.tod_sec; 255 xtime.tv_nsec = tod_data.tod_usec * 1000; 256 set_normalized_timespec(&wall_to_monotonic, 257 -xtime.tv_sec, -xtime.tv_nsec); 258 write_sequnlock_irqrestore(&xtime_lock, flags); 259 } else { 260 printk(KERN_ERR "Error reading tod clock\n"); 261 xtime.tv_sec = 0; 262 xtime.tv_nsec = 0; 263 } 264 } 265