1 /* 2 * linux/arch/parisc/kernel/time.c 3 * 4 * Copyright (C) 1991, 1992, 1995 Linus Torvalds 5 * Modifications for ARM (C) 1994, 1995, 1996,1997 Russell King 6 * Copyright (C) 1999 SuSE GmbH, (Philipp Rumpf, prumpf@tux.org) 7 * 8 * 1994-07-02 Alan Modra 9 * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime 10 * 1998-12-20 Updated NTP code according to technical memorandum Jan '96 11 * "A Kernel Model for Precision Timekeeping" by Dave Mills 12 */ 13 #include <linux/errno.h> 14 #include <linux/module.h> 15 #include <linux/sched.h> 16 #include <linux/kernel.h> 17 #include <linux/param.h> 18 #include <linux/string.h> 19 #include <linux/mm.h> 20 #include <linux/interrupt.h> 21 #include <linux/time.h> 22 #include <linux/init.h> 23 #include <linux/smp.h> 24 #include <linux/profile.h> 25 #include <linux/clocksource.h> 26 #include <linux/platform_device.h> 27 #include <linux/ftrace.h> 28 29 #include <asm/uaccess.h> 30 #include <asm/io.h> 31 #include <asm/irq.h> 32 #include <asm/param.h> 33 #include <asm/pdc.h> 34 #include <asm/led.h> 35 36 #include <linux/timex.h> 37 38 static unsigned long clocktick __read_mostly; /* timer cycles per tick */ 39 40 /* 41 * We keep time on PA-RISC Linux by using the Interval Timer which is 42 * a pair of registers; one is read-only and one is write-only; both 43 * accessed through CR16. The read-only register is 32 or 64 bits wide, 44 * and increments by 1 every CPU clock tick. The architecture only 45 * guarantees us a rate between 0.5 and 2, but all implementations use a 46 * rate of 1. The write-only register is 32-bits wide. When the lowest 47 * 32 bits of the read-only register compare equal to the write-only 48 * register, it raises a maskable external interrupt. Each processor has 49 * an Interval Timer of its own and they are not synchronised. 50 * 51 * We want to generate an interrupt every 1/HZ seconds. So we program 52 * CR16 to interrupt every @clocktick cycles. The it_value in cpu_data 53 * is programmed with the intended time of the next tick. We can be 54 * held off for an arbitrarily long period of time by interrupts being 55 * disabled, so we may miss one or more ticks. 56 */ 57 irqreturn_t __irq_entry timer_interrupt(int irq, void *dev_id) 58 { 59 unsigned long now, now2; 60 unsigned long next_tick; 61 unsigned long cycles_elapsed, ticks_elapsed = 1; 62 unsigned long cycles_remainder; 63 unsigned int cpu = smp_processor_id(); 64 struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu); 65 66 /* gcc can optimize for "read-only" case with a local clocktick */ 67 unsigned long cpt = clocktick; 68 69 profile_tick(CPU_PROFILING); 70 71 /* Initialize next_tick to the expected tick time. */ 72 next_tick = cpuinfo->it_value; 73 74 /* Get current cycle counter (Control Register 16). */ 75 now = mfctl(16); 76 77 cycles_elapsed = now - next_tick; 78 79 if ((cycles_elapsed >> 6) < cpt) { 80 /* use "cheap" math (add/subtract) instead 81 * of the more expensive div/mul method 82 */ 83 cycles_remainder = cycles_elapsed; 84 while (cycles_remainder > cpt) { 85 cycles_remainder -= cpt; 86 ticks_elapsed++; 87 } 88 } else { 89 /* TODO: Reduce this to one fdiv op */ 90 cycles_remainder = cycles_elapsed % cpt; 91 ticks_elapsed += cycles_elapsed / cpt; 92 } 93 94 /* convert from "division remainder" to "remainder of clock tick" */ 95 cycles_remainder = cpt - cycles_remainder; 96 97 /* Determine when (in CR16 cycles) next IT interrupt will fire. 98 * We want IT to fire modulo clocktick even if we miss/skip some. 99 * But those interrupts don't in fact get delivered that regularly. 100 */ 101 next_tick = now + cycles_remainder; 102 103 cpuinfo->it_value = next_tick; 104 105 /* Program the IT when to deliver the next interrupt. 106 * Only bottom 32-bits of next_tick are writable in CR16! 107 */ 108 mtctl(next_tick, 16); 109 110 /* Skip one clocktick on purpose if we missed next_tick. 111 * The new CR16 must be "later" than current CR16 otherwise 112 * itimer would not fire until CR16 wrapped - e.g 4 seconds 113 * later on a 1Ghz processor. We'll account for the missed 114 * tick on the next timer interrupt. 115 * 116 * "next_tick - now" will always give the difference regardless 117 * if one or the other wrapped. If "now" is "bigger" we'll end up 118 * with a very large unsigned number. 119 */ 120 now2 = mfctl(16); 121 if (next_tick - now2 > cpt) 122 mtctl(next_tick+cpt, 16); 123 124 #if 1 125 /* 126 * GGG: DEBUG code for how many cycles programming CR16 used. 127 */ 128 if (unlikely(now2 - now > 0x3000)) /* 12K cycles */ 129 printk (KERN_CRIT "timer_interrupt(CPU %d): SLOW! 0x%lx cycles!" 130 " cyc %lX rem %lX " 131 " next/now %lX/%lX\n", 132 cpu, now2 - now, cycles_elapsed, cycles_remainder, 133 next_tick, now ); 134 #endif 135 136 /* Can we differentiate between "early CR16" (aka Scenario 1) and 137 * "long delay" (aka Scenario 3)? I don't think so. 138 * 139 * Timer_interrupt will be delivered at least a few hundred cycles 140 * after the IT fires. But it's arbitrary how much time passes 141 * before we call it "late". I've picked one second. 142 * 143 * It's important NO printk's are between reading CR16 and 144 * setting up the next value. May introduce huge variance. 145 */ 146 if (unlikely(ticks_elapsed > HZ)) { 147 /* Scenario 3: very long delay? bad in any case */ 148 printk (KERN_CRIT "timer_interrupt(CPU %d): delayed!" 149 " cycles %lX rem %lX " 150 " next/now %lX/%lX\n", 151 cpu, 152 cycles_elapsed, cycles_remainder, 153 next_tick, now ); 154 } 155 156 /* Done mucking with unreliable delivery of interrupts. 157 * Go do system house keeping. 158 */ 159 160 if (!--cpuinfo->prof_counter) { 161 cpuinfo->prof_counter = cpuinfo->prof_multiplier; 162 update_process_times(user_mode(get_irq_regs())); 163 } 164 165 if (cpu == 0) 166 xtime_update(ticks_elapsed); 167 168 return IRQ_HANDLED; 169 } 170 171 172 unsigned long profile_pc(struct pt_regs *regs) 173 { 174 unsigned long pc = instruction_pointer(regs); 175 176 if (regs->gr[0] & PSW_N) 177 pc -= 4; 178 179 #ifdef CONFIG_SMP 180 if (in_lock_functions(pc)) 181 pc = regs->gr[2]; 182 #endif 183 184 return pc; 185 } 186 EXPORT_SYMBOL(profile_pc); 187 188 189 /* clock source code */ 190 191 static cycle_t read_cr16(struct clocksource *cs) 192 { 193 return get_cycles(); 194 } 195 196 static struct clocksource clocksource_cr16 = { 197 .name = "cr16", 198 .rating = 300, 199 .read = read_cr16, 200 .mask = CLOCKSOURCE_MASK(BITS_PER_LONG), 201 .mult = 0, /* to be set */ 202 .shift = 22, 203 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 204 }; 205 206 #ifdef CONFIG_SMP 207 int update_cr16_clocksource(void) 208 { 209 /* since the cr16 cycle counters are not synchronized across CPUs, 210 we'll check if we should switch to a safe clocksource: */ 211 if (clocksource_cr16.rating != 0 && num_online_cpus() > 1) { 212 clocksource_change_rating(&clocksource_cr16, 0); 213 return 1; 214 } 215 216 return 0; 217 } 218 #else 219 int update_cr16_clocksource(void) 220 { 221 return 0; /* no change */ 222 } 223 #endif /*CONFIG_SMP*/ 224 225 void __init start_cpu_itimer(void) 226 { 227 unsigned int cpu = smp_processor_id(); 228 unsigned long next_tick = mfctl(16) + clocktick; 229 230 mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */ 231 232 per_cpu(cpu_data, cpu).it_value = next_tick; 233 } 234 235 static struct platform_device rtc_generic_dev = { 236 .name = "rtc-generic", 237 .id = -1, 238 }; 239 240 static int __init rtc_init(void) 241 { 242 if (platform_device_register(&rtc_generic_dev) < 0) 243 printk(KERN_ERR "unable to register rtc device...\n"); 244 245 /* not necessarily an error */ 246 return 0; 247 } 248 module_init(rtc_init); 249 250 void read_persistent_clock(struct timespec *ts) 251 { 252 static struct pdc_tod tod_data; 253 if (pdc_tod_read(&tod_data) == 0) { 254 ts->tv_sec = tod_data.tod_sec; 255 ts->tv_nsec = tod_data.tod_usec * 1000; 256 } else { 257 printk(KERN_ERR "Error reading tod clock\n"); 258 ts->tv_sec = 0; 259 ts->tv_nsec = 0; 260 } 261 } 262 263 void __init time_init(void) 264 { 265 unsigned long current_cr16_khz; 266 267 clocktick = (100 * PAGE0->mem_10msec) / HZ; 268 269 start_cpu_itimer(); /* get CPU 0 started */ 270 271 /* register at clocksource framework */ 272 current_cr16_khz = PAGE0->mem_10msec/10; /* kHz */ 273 clocksource_cr16.mult = clocksource_khz2mult(current_cr16_khz, 274 clocksource_cr16.shift); 275 clocksource_register(&clocksource_cr16); 276 } 277