1 /* 2 * Parisc performance counters 3 * Copyright (C) 2001 Randolph Chung <tausq@debian.org> 4 * 5 * This code is derived, with permission, from HP/UX sources. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2, or (at your option) 10 * any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 20 */ 21 22 /* 23 * Edited comment from original sources: 24 * 25 * This driver programs the PCX-U/PCX-W performance counters 26 * on the PA-RISC 2.0 chips. The driver keeps all images now 27 * internally to the kernel to hopefully eliminate the possiblity 28 * of a bad image halting the CPU. Also, there are different 29 * images for the PCX-W and later chips vs the PCX-U chips. 30 * 31 * Only 1 process is allowed to access the driver at any time, 32 * so the only protection that is needed is at open and close. 33 * A variable "perf_enabled" is used to hold the state of the 34 * driver. The spinlock "perf_lock" is used to protect the 35 * modification of the state during open/close operations so 36 * multiple processes don't get into the driver simultaneously. 37 * 38 * This driver accesses the processor directly vs going through 39 * the PDC INTRIGUE calls. This is done to eliminate bugs introduced 40 * in various PDC revisions. The code is much more maintainable 41 * and reliable this way vs having to debug on every version of PDC 42 * on every box. 43 */ 44 45 #include <linux/init.h> 46 #include <linux/proc_fs.h> 47 #include <linux/miscdevice.h> 48 #include <linux/spinlock.h> 49 50 #include <asm/uaccess.h> 51 #include <asm/perf.h> 52 #include <asm/parisc-device.h> 53 #include <asm/processor.h> 54 #include <asm/runway.h> 55 #include <asm/io.h> /* for __raw_read() */ 56 57 #include "perf_images.h" 58 59 #define MAX_RDR_WORDS 24 60 #define PERF_VERSION 2 /* derived from hpux's PI v2 interface */ 61 62 /* definition of RDR regs */ 63 struct rdr_tbl_ent { 64 uint16_t width; 65 uint8_t num_words; 66 uint8_t write_control; 67 }; 68 69 static int perf_processor_interface = UNKNOWN_INTF; 70 static int perf_enabled = 0; 71 static spinlock_t perf_lock; 72 struct parisc_device *cpu_device = NULL; 73 74 /* RDRs to write for PCX-W */ 75 static int perf_rdrs_W[] = 76 { 0, 1, 4, 5, 6, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 }; 77 78 /* RDRs to write for PCX-U */ 79 static int perf_rdrs_U[] = 80 { 0, 1, 4, 5, 6, 7, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 }; 81 82 /* RDR register descriptions for PCX-W */ 83 static struct rdr_tbl_ent perf_rdr_tbl_W[] = { 84 { 19, 1, 8 }, /* RDR 0 */ 85 { 16, 1, 16 }, /* RDR 1 */ 86 { 72, 2, 0 }, /* RDR 2 */ 87 { 81, 2, 0 }, /* RDR 3 */ 88 { 328, 6, 0 }, /* RDR 4 */ 89 { 160, 3, 0 }, /* RDR 5 */ 90 { 336, 6, 0 }, /* RDR 6 */ 91 { 164, 3, 0 }, /* RDR 7 */ 92 { 0, 0, 0 }, /* RDR 8 */ 93 { 35, 1, 0 }, /* RDR 9 */ 94 { 6, 1, 0 }, /* RDR 10 */ 95 { 18, 1, 0 }, /* RDR 11 */ 96 { 13, 1, 0 }, /* RDR 12 */ 97 { 8, 1, 0 }, /* RDR 13 */ 98 { 8, 1, 0 }, /* RDR 14 */ 99 { 8, 1, 0 }, /* RDR 15 */ 100 { 1530, 24, 0 }, /* RDR 16 */ 101 { 16, 1, 0 }, /* RDR 17 */ 102 { 4, 1, 0 }, /* RDR 18 */ 103 { 0, 0, 0 }, /* RDR 19 */ 104 { 152, 3, 24 }, /* RDR 20 */ 105 { 152, 3, 24 }, /* RDR 21 */ 106 { 233, 4, 48 }, /* RDR 22 */ 107 { 233, 4, 48 }, /* RDR 23 */ 108 { 71, 2, 0 }, /* RDR 24 */ 109 { 71, 2, 0 }, /* RDR 25 */ 110 { 11, 1, 0 }, /* RDR 26 */ 111 { 18, 1, 0 }, /* RDR 27 */ 112 { 128, 2, 0 }, /* RDR 28 */ 113 { 0, 0, 0 }, /* RDR 29 */ 114 { 16, 1, 0 }, /* RDR 30 */ 115 { 16, 1, 0 }, /* RDR 31 */ 116 }; 117 118 /* RDR register descriptions for PCX-U */ 119 static struct rdr_tbl_ent perf_rdr_tbl_U[] = { 120 { 19, 1, 8 }, /* RDR 0 */ 121 { 32, 1, 16 }, /* RDR 1 */ 122 { 20, 1, 0 }, /* RDR 2 */ 123 { 0, 0, 0 }, /* RDR 3 */ 124 { 344, 6, 0 }, /* RDR 4 */ 125 { 176, 3, 0 }, /* RDR 5 */ 126 { 336, 6, 0 }, /* RDR 6 */ 127 { 0, 0, 0 }, /* RDR 7 */ 128 { 0, 0, 0 }, /* RDR 8 */ 129 { 0, 0, 0 }, /* RDR 9 */ 130 { 28, 1, 0 }, /* RDR 10 */ 131 { 33, 1, 0 }, /* RDR 11 */ 132 { 0, 0, 0 }, /* RDR 12 */ 133 { 230, 4, 0 }, /* RDR 13 */ 134 { 32, 1, 0 }, /* RDR 14 */ 135 { 128, 2, 0 }, /* RDR 15 */ 136 { 1494, 24, 0 }, /* RDR 16 */ 137 { 18, 1, 0 }, /* RDR 17 */ 138 { 4, 1, 0 }, /* RDR 18 */ 139 { 0, 0, 0 }, /* RDR 19 */ 140 { 158, 3, 24 }, /* RDR 20 */ 141 { 158, 3, 24 }, /* RDR 21 */ 142 { 194, 4, 48 }, /* RDR 22 */ 143 { 194, 4, 48 }, /* RDR 23 */ 144 { 71, 2, 0 }, /* RDR 24 */ 145 { 71, 2, 0 }, /* RDR 25 */ 146 { 28, 1, 0 }, /* RDR 26 */ 147 { 33, 1, 0 }, /* RDR 27 */ 148 { 88, 2, 0 }, /* RDR 28 */ 149 { 32, 1, 0 }, /* RDR 29 */ 150 { 24, 1, 0 }, /* RDR 30 */ 151 { 16, 1, 0 }, /* RDR 31 */ 152 }; 153 154 /* 155 * A non-zero write_control in the above tables is a byte offset into 156 * this array. 157 */ 158 static uint64_t perf_bitmasks[] = { 159 0x0000000000000000ul, /* first dbl word must be zero */ 160 0xfdffe00000000000ul, /* RDR0 bitmask */ 161 0x003f000000000000ul, /* RDR1 bitmask */ 162 0x00fffffffffffffful, /* RDR20-RDR21 bitmask (152 bits) */ 163 0xfffffffffffffffful, 164 0xfffffffc00000000ul, 165 0xfffffffffffffffful, /* RDR22-RDR23 bitmask (233 bits) */ 166 0xfffffffffffffffful, 167 0xfffffffffffffffcul, 168 0xff00000000000000ul 169 }; 170 171 /* 172 * Write control bitmasks for Pa-8700 processor given 173 * somethings have changed slightly. 174 */ 175 static uint64_t perf_bitmasks_piranha[] = { 176 0x0000000000000000ul, /* first dbl word must be zero */ 177 0xfdffe00000000000ul, /* RDR0 bitmask */ 178 0x003f000000000000ul, /* RDR1 bitmask */ 179 0x00fffffffffffffful, /* RDR20-RDR21 bitmask (158 bits) */ 180 0xfffffffffffffffful, 181 0xfffffffc00000000ul, 182 0xfffffffffffffffful, /* RDR22-RDR23 bitmask (210 bits) */ 183 0xfffffffffffffffful, 184 0xfffffffffffffffful, 185 0xfffc000000000000ul 186 }; 187 188 static uint64_t *bitmask_array; /* array of bitmasks to use */ 189 190 /****************************************************************************** 191 * Function Prototypes 192 *****************************************************************************/ 193 static int perf_config(uint32_t *image_ptr); 194 static int perf_release(struct inode *inode, struct file *file); 195 static int perf_open(struct inode *inode, struct file *file); 196 static ssize_t perf_read(struct file *file, char __user *buf, size_t cnt, loff_t *ppos); 197 static ssize_t perf_write(struct file *file, const char __user *buf, size_t count, 198 loff_t *ppos); 199 static int perf_ioctl(struct inode *inode, struct file *file, unsigned int cmd, 200 unsigned long arg); 201 static void perf_start_counters(void); 202 static int perf_stop_counters(uint32_t *raddr); 203 static struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num); 204 static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer); 205 static int perf_rdr_clear(uint32_t rdr_num); 206 static int perf_write_image(uint64_t *memaddr); 207 static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer); 208 209 /* External Assembly Routines */ 210 extern uint64_t perf_rdr_shift_in_W (uint32_t rdr_num, uint16_t width); 211 extern uint64_t perf_rdr_shift_in_U (uint32_t rdr_num, uint16_t width); 212 extern void perf_rdr_shift_out_W (uint32_t rdr_num, uint64_t buffer); 213 extern void perf_rdr_shift_out_U (uint32_t rdr_num, uint64_t buffer); 214 extern void perf_intrigue_enable_perf_counters (void); 215 extern void perf_intrigue_disable_perf_counters (void); 216 217 /****************************************************************************** 218 * Function Definitions 219 *****************************************************************************/ 220 221 222 /* 223 * configure: 224 * 225 * Configure the cpu with a given data image. First turn off the counters, 226 * then download the image, then turn the counters back on. 227 */ 228 static int perf_config(uint32_t *image_ptr) 229 { 230 long error; 231 uint32_t raddr[4]; 232 233 /* Stop the counters*/ 234 error = perf_stop_counters(raddr); 235 if (error != 0) { 236 printk("perf_config: perf_stop_counters = %ld\n", error); 237 return -EINVAL; 238 } 239 240 printk("Preparing to write image\n"); 241 /* Write the image to the chip */ 242 error = perf_write_image((uint64_t *)image_ptr); 243 if (error != 0) { 244 printk("perf_config: DOWNLOAD = %ld\n", error); 245 return -EINVAL; 246 } 247 248 printk("Preparing to start counters\n"); 249 250 /* Start the counters */ 251 perf_start_counters(); 252 253 return sizeof(uint32_t); 254 } 255 256 /* 257 * Open the device and initialize all of its memory. The device is only 258 * opened once, but can be "queried" by multiple processes that know its 259 * file descriptor. 260 */ 261 static int perf_open(struct inode *inode, struct file *file) 262 { 263 spin_lock(&perf_lock); 264 if (perf_enabled) { 265 spin_unlock(&perf_lock); 266 return -EBUSY; 267 } 268 perf_enabled = 1; 269 spin_unlock(&perf_lock); 270 271 return 0; 272 } 273 274 /* 275 * Close the device. 276 */ 277 static int perf_release(struct inode *inode, struct file *file) 278 { 279 spin_lock(&perf_lock); 280 perf_enabled = 0; 281 spin_unlock(&perf_lock); 282 283 return 0; 284 } 285 286 /* 287 * Read does nothing for this driver 288 */ 289 static ssize_t perf_read(struct file *file, char __user *buf, size_t cnt, loff_t *ppos) 290 { 291 return 0; 292 } 293 294 /* 295 * write: 296 * 297 * This routine downloads the image to the chip. It must be 298 * called on the processor that the download should happen 299 * on. 300 */ 301 static ssize_t perf_write(struct file *file, const char __user *buf, size_t count, 302 loff_t *ppos) 303 { 304 int err; 305 size_t image_size; 306 uint32_t image_type; 307 uint32_t interface_type; 308 uint32_t test; 309 310 if (perf_processor_interface == ONYX_INTF) 311 image_size = PCXU_IMAGE_SIZE; 312 else if (perf_processor_interface == CUDA_INTF) 313 image_size = PCXW_IMAGE_SIZE; 314 else 315 return -EFAULT; 316 317 if (!capable(CAP_SYS_ADMIN)) 318 return -EACCES; 319 320 if (count != sizeof(uint32_t)) 321 return -EIO; 322 323 if ((err = copy_from_user(&image_type, buf, sizeof(uint32_t))) != 0) 324 return err; 325 326 /* Get the interface type and test type */ 327 interface_type = (image_type >> 16) & 0xffff; 328 test = (image_type & 0xffff); 329 330 /* Make sure everything makes sense */ 331 332 /* First check the machine type is correct for 333 the requested image */ 334 if (((perf_processor_interface == CUDA_INTF) && 335 (interface_type != CUDA_INTF)) || 336 ((perf_processor_interface == ONYX_INTF) && 337 (interface_type != ONYX_INTF))) 338 return -EINVAL; 339 340 /* Next check to make sure the requested image 341 is valid */ 342 if (((interface_type == CUDA_INTF) && 343 (test >= MAX_CUDA_IMAGES)) || 344 ((interface_type == ONYX_INTF) && 345 (test >= MAX_ONYX_IMAGES))) 346 return -EINVAL; 347 348 /* Copy the image into the processor */ 349 if (interface_type == CUDA_INTF) 350 return perf_config(cuda_images[test]); 351 else 352 return perf_config(onyx_images[test]); 353 354 return count; 355 } 356 357 /* 358 * Patch the images that need to know the IVA addresses. 359 */ 360 static void perf_patch_images(void) 361 { 362 #if 0 /* FIXME!! */ 363 /* 364 * NOTE: this routine is VERY specific to the current TLB image. 365 * If the image is changed, this routine might also need to be changed. 366 */ 367 extern void $i_itlb_miss_2_0(); 368 extern void $i_dtlb_miss_2_0(); 369 extern void PA2_0_iva(); 370 371 /* 372 * We can only use the lower 32-bits, the upper 32-bits should be 0 373 * anyway given this is in the kernel 374 */ 375 uint32_t itlb_addr = (uint32_t)&($i_itlb_miss_2_0); 376 uint32_t dtlb_addr = (uint32_t)&($i_dtlb_miss_2_0); 377 uint32_t IVAaddress = (uint32_t)&PA2_0_iva; 378 379 if (perf_processor_interface == ONYX_INTF) { 380 /* clear last 2 bytes */ 381 onyx_images[TLBMISS][15] &= 0xffffff00; 382 /* set 2 bytes */ 383 onyx_images[TLBMISS][15] |= (0x000000ff&((dtlb_addr) >> 24)); 384 onyx_images[TLBMISS][16] = (dtlb_addr << 8)&0xffffff00; 385 onyx_images[TLBMISS][17] = itlb_addr; 386 387 /* clear last 2 bytes */ 388 onyx_images[TLBHANDMISS][15] &= 0xffffff00; 389 /* set 2 bytes */ 390 onyx_images[TLBHANDMISS][15] |= (0x000000ff&((dtlb_addr) >> 24)); 391 onyx_images[TLBHANDMISS][16] = (dtlb_addr << 8)&0xffffff00; 392 onyx_images[TLBHANDMISS][17] = itlb_addr; 393 394 /* clear last 2 bytes */ 395 onyx_images[BIG_CPI][15] &= 0xffffff00; 396 /* set 2 bytes */ 397 onyx_images[BIG_CPI][15] |= (0x000000ff&((dtlb_addr) >> 24)); 398 onyx_images[BIG_CPI][16] = (dtlb_addr << 8)&0xffffff00; 399 onyx_images[BIG_CPI][17] = itlb_addr; 400 401 onyx_images[PANIC][15] &= 0xffffff00; /* clear last 2 bytes */ 402 onyx_images[PANIC][15] |= (0x000000ff&((IVAaddress) >> 24)); /* set 2 bytes */ 403 onyx_images[PANIC][16] = (IVAaddress << 8)&0xffffff00; 404 405 406 } else if (perf_processor_interface == CUDA_INTF) { 407 /* Cuda interface */ 408 cuda_images[TLBMISS][16] = 409 (cuda_images[TLBMISS][16]&0xffff0000) | 410 ((dtlb_addr >> 8)&0x0000ffff); 411 cuda_images[TLBMISS][17] = 412 ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff); 413 cuda_images[TLBMISS][18] = (itlb_addr << 16)&0xffff0000; 414 415 cuda_images[TLBHANDMISS][16] = 416 (cuda_images[TLBHANDMISS][16]&0xffff0000) | 417 ((dtlb_addr >> 8)&0x0000ffff); 418 cuda_images[TLBHANDMISS][17] = 419 ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff); 420 cuda_images[TLBHANDMISS][18] = (itlb_addr << 16)&0xffff0000; 421 422 cuda_images[BIG_CPI][16] = 423 (cuda_images[BIG_CPI][16]&0xffff0000) | 424 ((dtlb_addr >> 8)&0x0000ffff); 425 cuda_images[BIG_CPI][17] = 426 ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff); 427 cuda_images[BIG_CPI][18] = (itlb_addr << 16)&0xffff0000; 428 } else { 429 /* Unknown type */ 430 } 431 #endif 432 } 433 434 435 /* 436 * ioctl routine 437 * All routines effect the processor that they are executed on. Thus you 438 * must be running on the processor that you wish to change. 439 */ 440 441 static int perf_ioctl(struct inode *inode, struct file *file, unsigned int cmd, 442 unsigned long arg) 443 { 444 long error_start; 445 uint32_t raddr[4]; 446 447 switch (cmd) { 448 449 case PA_PERF_ON: 450 /* Start the counters */ 451 perf_start_counters(); 452 return 0; 453 454 case PA_PERF_OFF: 455 error_start = perf_stop_counters(raddr); 456 if (error_start != 0) { 457 printk(KERN_ERR "perf_off: perf_stop_counters = %ld\n", error_start); 458 return -EFAULT; 459 } 460 461 /* copy out the Counters */ 462 if (copy_to_user((void __user *)arg, raddr, 463 sizeof (raddr)) != 0) { 464 return -EFAULT; 465 } 466 return 0; 467 468 case PA_PERF_VERSION: 469 /* Return the version # */ 470 return put_user(PERF_VERSION, (int *)arg); 471 472 default: 473 break; 474 } 475 return -ENOTTY; 476 } 477 478 static struct file_operations perf_fops = { 479 .llseek = no_llseek, 480 .read = perf_read, 481 .write = perf_write, 482 .ioctl = perf_ioctl, 483 .open = perf_open, 484 .release = perf_release 485 }; 486 487 static struct miscdevice perf_dev = { 488 MISC_DYNAMIC_MINOR, 489 PA_PERF_DEV, 490 &perf_fops 491 }; 492 493 /* 494 * Initialize the module 495 */ 496 static int __init perf_init(void) 497 { 498 int ret; 499 500 /* Determine correct processor interface to use */ 501 bitmask_array = perf_bitmasks; 502 503 if (boot_cpu_data.cpu_type == pcxu || 504 boot_cpu_data.cpu_type == pcxu_) { 505 perf_processor_interface = ONYX_INTF; 506 } else if (boot_cpu_data.cpu_type == pcxw || 507 boot_cpu_data.cpu_type == pcxw_ || 508 boot_cpu_data.cpu_type == pcxw2 || 509 boot_cpu_data.cpu_type == mako) { 510 perf_processor_interface = CUDA_INTF; 511 if (boot_cpu_data.cpu_type == pcxw2 || 512 boot_cpu_data.cpu_type == mako) 513 bitmask_array = perf_bitmasks_piranha; 514 } else { 515 perf_processor_interface = UNKNOWN_INTF; 516 printk("Performance monitoring counters not supported on this processor\n"); 517 return -ENODEV; 518 } 519 520 ret = misc_register(&perf_dev); 521 if (ret) { 522 printk(KERN_ERR "Performance monitoring counters: " 523 "cannot register misc device.\n"); 524 return ret; 525 } 526 527 /* Patch the images to match the system */ 528 perf_patch_images(); 529 530 spin_lock_init(&perf_lock); 531 532 /* TODO: this only lets us access the first cpu.. what to do for SMP? */ 533 cpu_device = cpu_data[0].dev; 534 printk("Performance monitoring counters enabled for %s\n", 535 cpu_data[0].dev->name); 536 537 return 0; 538 } 539 540 /* 541 * perf_start_counters(void) 542 * 543 * Start the counters. 544 */ 545 static void perf_start_counters(void) 546 { 547 /* Enable performance monitor counters */ 548 perf_intrigue_enable_perf_counters(); 549 } 550 551 /* 552 * perf_stop_counters 553 * 554 * Stop the performance counters and save counts 555 * in a per_processor array. 556 */ 557 static int perf_stop_counters(uint32_t *raddr) 558 { 559 uint64_t userbuf[MAX_RDR_WORDS]; 560 561 /* Disable performance counters */ 562 perf_intrigue_disable_perf_counters(); 563 564 if (perf_processor_interface == ONYX_INTF) { 565 uint64_t tmp64; 566 /* 567 * Read the counters 568 */ 569 if (!perf_rdr_read_ubuf(16, userbuf)) 570 return -13; 571 572 /* Counter0 is bits 1398 thru 1429 */ 573 tmp64 = (userbuf[21] << 22) & 0x00000000ffc00000; 574 tmp64 |= (userbuf[22] >> 42) & 0x00000000003fffff; 575 /* OR sticky0 (bit 1430) to counter0 bit 32 */ 576 tmp64 |= (userbuf[22] >> 10) & 0x0000000080000000; 577 raddr[0] = (uint32_t)tmp64; 578 579 /* Counter1 is bits 1431 thru 1462 */ 580 tmp64 = (userbuf[22] >> 9) & 0x00000000ffffffff; 581 /* OR sticky1 (bit 1463) to counter1 bit 32 */ 582 tmp64 |= (userbuf[22] << 23) & 0x0000000080000000; 583 raddr[1] = (uint32_t)tmp64; 584 585 /* Counter2 is bits 1464 thru 1495 */ 586 tmp64 = (userbuf[22] << 24) & 0x00000000ff000000; 587 tmp64 |= (userbuf[23] >> 40) & 0x0000000000ffffff; 588 /* OR sticky2 (bit 1496) to counter2 bit 32 */ 589 tmp64 |= (userbuf[23] >> 8) & 0x0000000080000000; 590 raddr[2] = (uint32_t)tmp64; 591 592 /* Counter3 is bits 1497 thru 1528 */ 593 tmp64 = (userbuf[23] >> 7) & 0x00000000ffffffff; 594 /* OR sticky3 (bit 1529) to counter3 bit 32 */ 595 tmp64 |= (userbuf[23] << 25) & 0x0000000080000000; 596 raddr[3] = (uint32_t)tmp64; 597 598 /* 599 * Zero out the counters 600 */ 601 602 /* 603 * The counters and sticky-bits comprise the last 132 bits 604 * (1398 - 1529) of RDR16 on a U chip. We'll zero these 605 * out the easy way: zero out last 10 bits of dword 21, 606 * all of dword 22 and 58 bits (plus 6 don't care bits) of 607 * dword 23. 608 */ 609 userbuf[21] &= 0xfffffffffffffc00ul; /* 0 to last 10 bits */ 610 userbuf[22] = 0; 611 userbuf[23] = 0; 612 613 /* 614 * Write back the zero'ed bytes + the image given 615 * the read was destructive. 616 */ 617 perf_rdr_write(16, userbuf); 618 } else { 619 620 /* 621 * Read RDR-15 which contains the counters and sticky bits 622 */ 623 if (!perf_rdr_read_ubuf(15, userbuf)) { 624 return -13; 625 } 626 627 /* 628 * Clear out the counters 629 */ 630 perf_rdr_clear(15); 631 632 /* 633 * Copy the counters 634 */ 635 raddr[0] = (uint32_t)((userbuf[0] >> 32) & 0x00000000ffffffffUL); 636 raddr[1] = (uint32_t)(userbuf[0] & 0x00000000ffffffffUL); 637 raddr[2] = (uint32_t)((userbuf[1] >> 32) & 0x00000000ffffffffUL); 638 raddr[3] = (uint32_t)(userbuf[1] & 0x00000000ffffffffUL); 639 } 640 641 return 0; 642 } 643 644 /* 645 * perf_rdr_get_entry 646 * 647 * Retrieve a pointer to the description of what this 648 * RDR contains. 649 */ 650 static struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num) 651 { 652 if (perf_processor_interface == ONYX_INTF) { 653 return &perf_rdr_tbl_U[rdr_num]; 654 } else { 655 return &perf_rdr_tbl_W[rdr_num]; 656 } 657 } 658 659 /* 660 * perf_rdr_read_ubuf 661 * 662 * Read the RDR value into the buffer specified. 663 */ 664 static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer) 665 { 666 uint64_t data, data_mask = 0; 667 uint32_t width, xbits, i; 668 struct rdr_tbl_ent *tentry; 669 670 tentry = perf_rdr_get_entry(rdr_num); 671 if ((width = tentry->width) == 0) 672 return 0; 673 674 /* Clear out buffer */ 675 i = tentry->num_words; 676 while (i--) { 677 buffer[i] = 0; 678 } 679 680 /* Check for bits an even number of 64 */ 681 if ((xbits = width & 0x03f) != 0) { 682 data_mask = 1; 683 data_mask <<= (64 - xbits); 684 data_mask--; 685 } 686 687 /* Grab all of the data */ 688 i = tentry->num_words; 689 while (i--) { 690 691 if (perf_processor_interface == ONYX_INTF) { 692 data = perf_rdr_shift_in_U(rdr_num, width); 693 } else { 694 data = perf_rdr_shift_in_W(rdr_num, width); 695 } 696 if (xbits) { 697 buffer[i] |= (data << (64 - xbits)); 698 if (i) { 699 buffer[i-1] |= ((data >> xbits) & data_mask); 700 } 701 } else { 702 buffer[i] = data; 703 } 704 } 705 706 return 1; 707 } 708 709 /* 710 * perf_rdr_clear 711 * 712 * Zero out the given RDR register 713 */ 714 static int perf_rdr_clear(uint32_t rdr_num) 715 { 716 struct rdr_tbl_ent *tentry; 717 int32_t i; 718 719 tentry = perf_rdr_get_entry(rdr_num); 720 721 if (tentry->width == 0) { 722 return -1; 723 } 724 725 i = tentry->num_words; 726 while (i--) { 727 if (perf_processor_interface == ONYX_INTF) { 728 perf_rdr_shift_out_U(rdr_num, 0UL); 729 } else { 730 perf_rdr_shift_out_W(rdr_num, 0UL); 731 } 732 } 733 734 return 0; 735 } 736 737 738 /* 739 * perf_write_image 740 * 741 * Write the given image out to the processor 742 */ 743 static int perf_write_image(uint64_t *memaddr) 744 { 745 uint64_t buffer[MAX_RDR_WORDS]; 746 uint64_t *bptr; 747 uint32_t dwords; 748 uint32_t *intrigue_rdr; 749 uint64_t *intrigue_bitmask, tmp64, proc_hpa; 750 struct rdr_tbl_ent *tentry; 751 int i; 752 753 /* Clear out counters */ 754 if (perf_processor_interface == ONYX_INTF) { 755 756 perf_rdr_clear(16); 757 758 /* Toggle performance monitor */ 759 perf_intrigue_enable_perf_counters(); 760 perf_intrigue_disable_perf_counters(); 761 762 intrigue_rdr = perf_rdrs_U; 763 } else { 764 perf_rdr_clear(15); 765 intrigue_rdr = perf_rdrs_W; 766 } 767 768 /* Write all RDRs */ 769 while (*intrigue_rdr != -1) { 770 tentry = perf_rdr_get_entry(*intrigue_rdr); 771 perf_rdr_read_ubuf(*intrigue_rdr, buffer); 772 bptr = &buffer[0]; 773 dwords = tentry->num_words; 774 if (tentry->write_control) { 775 intrigue_bitmask = &bitmask_array[tentry->write_control >> 3]; 776 while (dwords--) { 777 tmp64 = *intrigue_bitmask & *memaddr++; 778 tmp64 |= (~(*intrigue_bitmask++)) & *bptr; 779 *bptr++ = tmp64; 780 } 781 } else { 782 while (dwords--) { 783 *bptr++ = *memaddr++; 784 } 785 } 786 787 perf_rdr_write(*intrigue_rdr, buffer); 788 intrigue_rdr++; 789 } 790 791 /* 792 * Now copy out the Runway stuff which is not in RDRs 793 */ 794 795 if (cpu_device == NULL) 796 { 797 printk(KERN_ERR "write_image: cpu_device not yet initialized!\n"); 798 return -1; 799 } 800 801 proc_hpa = cpu_device->hpa; 802 803 /* Merge intrigue bits into Runway STATUS 0 */ 804 tmp64 = __raw_readq(proc_hpa + RUNWAY_STATUS) & 0xffecfffffffffffful; 805 __raw_writeq(tmp64 | (*memaddr++ & 0x0013000000000000ul), proc_hpa + RUNWAY_STATUS); 806 807 /* Write RUNWAY DEBUG registers */ 808 for (i = 0; i < 8; i++) { 809 __raw_writeq(*memaddr++, proc_hpa + RUNWAY_DEBUG + i); 810 } 811 812 return 0; 813 } 814 815 /* 816 * perf_rdr_write 817 * 818 * Write the given RDR register with the contents 819 * of the given buffer. 820 */ 821 static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer) 822 { 823 struct rdr_tbl_ent *tentry; 824 int32_t i; 825 826 printk("perf_rdr_write\n"); 827 tentry = perf_rdr_get_entry(rdr_num); 828 if (tentry->width == 0) { return; } 829 830 i = tentry->num_words; 831 while (i--) { 832 if (perf_processor_interface == ONYX_INTF) { 833 perf_rdr_shift_out_U(rdr_num, buffer[i]); 834 } else { 835 perf_rdr_shift_out_W(rdr_num, buffer[i]); 836 } 837 } 838 printk("perf_rdr_write done\n"); 839 } 840 841 module_init(perf_init); 842