1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1997, 1998 Ralf Baechle 7 * Copyright (C) 1999 SuSE GmbH 8 * Copyright (C) 1999-2001 Hewlett-Packard Company 9 * Copyright (C) 1999-2001 Grant Grundler 10 */ 11 #include <linux/eisa.h> 12 #include <linux/init.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/pci.h> 16 #include <linux/types.h> 17 18 #include <asm/io.h> 19 #include <asm/system.h> 20 #include <asm/superio.h> 21 22 #define DEBUG_RESOURCES 0 23 #define DEBUG_CONFIG 0 24 25 #if DEBUG_CONFIG 26 # define DBGC(x...) printk(KERN_DEBUG x) 27 #else 28 # define DBGC(x...) 29 #endif 30 31 32 #if DEBUG_RESOURCES 33 #define DBG_RES(x...) printk(KERN_DEBUG x) 34 #else 35 #define DBG_RES(x...) 36 #endif 37 38 /* To be used as: mdelay(pci_post_reset_delay); 39 * 40 * post_reset is the time the kernel should stall to prevent anyone from 41 * accessing the PCI bus once #RESET is de-asserted. 42 * PCI spec somewhere says 1 second but with multi-PCI bus systems, 43 * this makes the boot time much longer than necessary. 44 * 20ms seems to work for all the HP PCI implementations to date. 45 * 46 * #define pci_post_reset_delay 50 47 */ 48 49 struct pci_port_ops *pci_port __read_mostly; 50 struct pci_bios_ops *pci_bios __read_mostly; 51 52 static int pci_hba_count __read_mostly; 53 54 /* parisc_pci_hba used by pci_port->in/out() ops to lookup bus data. */ 55 #define PCI_HBA_MAX 32 56 static struct pci_hba_data *parisc_pci_hba[PCI_HBA_MAX] __read_mostly; 57 58 59 /******************************************************************** 60 ** 61 ** I/O port space support 62 ** 63 *********************************************************************/ 64 65 /* EISA port numbers and PCI port numbers share the same interface. Some 66 * machines have both EISA and PCI adapters installed. Rather than turn 67 * pci_port into an array, we reserve bus 0 for EISA and call the EISA 68 * routines if the access is to a port on bus 0. We don't want to fix 69 * EISA and ISA drivers which assume port space is <= 0xffff. 70 */ 71 72 #ifdef CONFIG_EISA 73 #define EISA_IN(size) if (EISA_bus && (b == 0)) return eisa_in##size(addr) 74 #define EISA_OUT(size) if (EISA_bus && (b == 0)) return eisa_out##size(d, addr) 75 #else 76 #define EISA_IN(size) 77 #define EISA_OUT(size) 78 #endif 79 80 #define PCI_PORT_IN(type, size) \ 81 u##size in##type (int addr) \ 82 { \ 83 int b = PCI_PORT_HBA(addr); \ 84 EISA_IN(size); \ 85 if (!parisc_pci_hba[b]) return (u##size) -1; \ 86 return pci_port->in##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr)); \ 87 } \ 88 EXPORT_SYMBOL(in##type); 89 90 PCI_PORT_IN(b, 8) 91 PCI_PORT_IN(w, 16) 92 PCI_PORT_IN(l, 32) 93 94 95 #define PCI_PORT_OUT(type, size) \ 96 void out##type (u##size d, int addr) \ 97 { \ 98 int b = PCI_PORT_HBA(addr); \ 99 EISA_OUT(size); \ 100 if (!parisc_pci_hba[b]) return; \ 101 pci_port->out##type(parisc_pci_hba[b], PCI_PORT_ADDR(addr), d); \ 102 } \ 103 EXPORT_SYMBOL(out##type); 104 105 PCI_PORT_OUT(b, 8) 106 PCI_PORT_OUT(w, 16) 107 PCI_PORT_OUT(l, 32) 108 109 110 111 /* 112 * BIOS32 replacement. 113 */ 114 static int __init pcibios_init(void) 115 { 116 if (!pci_bios) 117 return -1; 118 119 if (pci_bios->init) { 120 pci_bios->init(); 121 } else { 122 printk(KERN_WARNING "pci_bios != NULL but init() is!\n"); 123 } 124 125 /* Set the CLS for PCI as early as possible. */ 126 pci_cache_line_size = pci_dfl_cache_line_size; 127 128 return 0; 129 } 130 131 132 /* Called from pci_do_scan_bus() *after* walking a bus but before walking PPBs. */ 133 void pcibios_fixup_bus(struct pci_bus *bus) 134 { 135 if (pci_bios->fixup_bus) { 136 pci_bios->fixup_bus(bus); 137 } else { 138 printk(KERN_WARNING "pci_bios != NULL but fixup_bus() is!\n"); 139 } 140 } 141 142 143 char *pcibios_setup(char *str) 144 { 145 return str; 146 } 147 148 /* 149 * Called by pci_set_master() - a driver interface. 150 * 151 * Legacy PDC guarantees to set: 152 * Map Memory BAR's into PA IO space. 153 * Map Expansion ROM BAR into one common PA IO space per bus. 154 * Map IO BAR's into PCI IO space. 155 * Command (see below) 156 * Cache Line Size 157 * Latency Timer 158 * Interrupt Line 159 * PPB: secondary latency timer, io/mmio base/limit, 160 * bus numbers, bridge control 161 * 162 */ 163 void pcibios_set_master(struct pci_dev *dev) 164 { 165 u8 lat; 166 167 /* If someone already mucked with this, don't touch it. */ 168 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 169 if (lat >= 16) return; 170 171 /* 172 ** HP generally has fewer devices on the bus than other architectures. 173 ** upper byte is PCI_LATENCY_TIMER. 174 */ 175 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, 176 (0x80 << 8) | pci_cache_line_size); 177 } 178 179 180 void __init pcibios_init_bus(struct pci_bus *bus) 181 { 182 struct pci_dev *dev = bus->self; 183 unsigned short bridge_ctl; 184 185 /* We deal only with pci controllers and pci-pci bridges. */ 186 if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) 187 return; 188 189 /* PCI-PCI bridge - set the cache line and default latency 190 (32) for primary and secondary buses. */ 191 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32); 192 193 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl); 194 bridge_ctl |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; 195 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl); 196 } 197 198 /* called by drivers/pci/setup-bus.c:pci_setup_bridge(). */ 199 void __devinit pcibios_resource_to_bus(struct pci_dev *dev, 200 struct pci_bus_region *region, struct resource *res) 201 { 202 #ifdef CONFIG_64BIT 203 struct pci_hba_data *hba = HBA_DATA(dev->bus->bridge->platform_data); 204 #endif 205 206 if (res->flags & IORESOURCE_IO) { 207 /* 208 ** I/O space may see busnumbers here. Something 209 ** in the form of 0xbbxxxx where bb is the bus num 210 ** and xxxx is the I/O port space address. 211 ** Remaining address translation are done in the 212 ** PCI Host adapter specific code - ie dino_out8. 213 */ 214 region->start = PCI_PORT_ADDR(res->start); 215 region->end = PCI_PORT_ADDR(res->end); 216 } else if (res->flags & IORESOURCE_MEM) { 217 /* Convert MMIO addr to PCI addr (undo global virtualization) */ 218 region->start = PCI_BUS_ADDR(hba, res->start); 219 region->end = PCI_BUS_ADDR(hba, res->end); 220 } 221 222 DBG_RES("pcibios_resource_to_bus(%02x %s [%lx,%lx])\n", 223 dev->bus->number, res->flags & IORESOURCE_IO ? "IO" : "MEM", 224 region->start, region->end); 225 } 226 227 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 228 struct pci_bus_region *region) 229 { 230 #ifdef CONFIG_64BIT 231 struct pci_hba_data *hba = HBA_DATA(dev->bus->bridge->platform_data); 232 #endif 233 234 if (res->flags & IORESOURCE_MEM) { 235 res->start = PCI_HOST_ADDR(hba, region->start); 236 res->end = PCI_HOST_ADDR(hba, region->end); 237 } 238 239 if (res->flags & IORESOURCE_IO) { 240 res->start = region->start; 241 res->end = region->end; 242 } 243 } 244 245 #ifdef CONFIG_HOTPLUG 246 EXPORT_SYMBOL(pcibios_resource_to_bus); 247 EXPORT_SYMBOL(pcibios_bus_to_resource); 248 #endif 249 250 /* 251 * pcibios align resources() is called every time generic PCI code 252 * wants to generate a new address. The process of looking for 253 * an available address, each candidate is first "aligned" and 254 * then checked if the resource is available until a match is found. 255 * 256 * Since we are just checking candidates, don't use any fields other 257 * than res->start. 258 */ 259 resource_size_t pcibios_align_resource(void *data, const struct resource *res, 260 resource_size_t size, resource_size_t alignment) 261 { 262 resource_size_t mask, align, start = res->start; 263 264 DBG_RES("pcibios_align_resource(%s, (%p) [%lx,%lx]/%x, 0x%lx, 0x%lx)\n", 265 pci_name(((struct pci_dev *) data)), 266 res->parent, res->start, res->end, 267 (int) res->flags, size, alignment); 268 269 /* If it's not IO, then it's gotta be MEM */ 270 align = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM; 271 272 /* Align to largest of MIN or input size */ 273 mask = max(alignment, align) - 1; 274 start += mask; 275 start &= ~mask; 276 277 return start; 278 } 279 280 281 /* 282 * A driver is enabling the device. We make sure that all the appropriate 283 * bits are set to allow the device to operate as the driver is expecting. 284 * We enable the port IO and memory IO bits if the device has any BARs of 285 * that type, and we enable the PERR and SERR bits unconditionally. 286 * Drivers that do not need parity (eg graphics and possibly networking) 287 * can clear these bits if they want. 288 */ 289 int pcibios_enable_device(struct pci_dev *dev, int mask) 290 { 291 int err; 292 u16 cmd, old_cmd; 293 294 err = pci_enable_resources(dev, mask); 295 if (err < 0) 296 return err; 297 298 pci_read_config_word(dev, PCI_COMMAND, &cmd); 299 old_cmd = cmd; 300 301 cmd |= (PCI_COMMAND_SERR | PCI_COMMAND_PARITY); 302 303 #if 0 304 /* If bridge/bus controller has FBB enabled, child must too. */ 305 if (dev->bus->bridge_ctl & PCI_BRIDGE_CTL_FAST_BACK) 306 cmd |= PCI_COMMAND_FAST_BACK; 307 #endif 308 309 if (cmd != old_cmd) { 310 dev_info(&dev->dev, "enabling SERR and PARITY (%04x -> %04x)\n", 311 old_cmd, cmd); 312 pci_write_config_word(dev, PCI_COMMAND, cmd); 313 } 314 return 0; 315 } 316 317 318 /* PA-RISC specific */ 319 void pcibios_register_hba(struct pci_hba_data *hba) 320 { 321 if (pci_hba_count >= PCI_HBA_MAX) { 322 printk(KERN_ERR "PCI: Too many Host Bus Adapters\n"); 323 return; 324 } 325 326 parisc_pci_hba[pci_hba_count] = hba; 327 hba->hba_num = pci_hba_count++; 328 } 329 330 subsys_initcall(pcibios_init); 331