1 /* 2 * Code to handle x86 style IRQs plus some generic interrupt stuff. 3 * 4 * Copyright (C) 1992 Linus Torvalds 5 * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle 6 * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org) 7 * Copyright (C) 1999-2000 Grant Grundler 8 * Copyright (c) 2005 Matthew Wilcox 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2, or (at your option) 13 * any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 #include <linux/bitops.h> 25 #include <linux/errno.h> 26 #include <linux/init.h> 27 #include <linux/interrupt.h> 28 #include <linux/kernel_stat.h> 29 #include <linux/seq_file.h> 30 #include <linux/spinlock.h> 31 #include <linux/types.h> 32 #include <asm/io.h> 33 34 #include <asm/smp.h> 35 36 #undef PARISC_IRQ_CR16_COUNTS 37 38 extern irqreturn_t timer_interrupt(int, void *); 39 extern irqreturn_t ipi_interrupt(int, void *); 40 41 #define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq)) 42 43 /* Bits in EIEM correlate with cpu_irq_action[]. 44 ** Numbered *Big Endian*! (ie bit 0 is MSB) 45 */ 46 static volatile unsigned long cpu_eiem = 0; 47 48 /* 49 ** local ACK bitmap ... habitually set to 1, but reset to zero 50 ** between ->ack() and ->end() of the interrupt to prevent 51 ** re-interruption of a processing interrupt. 52 */ 53 static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL; 54 55 static void cpu_mask_irq(unsigned int irq) 56 { 57 unsigned long eirr_bit = EIEM_MASK(irq); 58 59 cpu_eiem &= ~eirr_bit; 60 /* Do nothing on the other CPUs. If they get this interrupt, 61 * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't 62 * handle it, and the set_eiem() at the bottom will ensure it 63 * then gets disabled */ 64 } 65 66 static void cpu_unmask_irq(unsigned int irq) 67 { 68 unsigned long eirr_bit = EIEM_MASK(irq); 69 70 cpu_eiem |= eirr_bit; 71 72 /* This is just a simple NOP IPI. But what it does is cause 73 * all the other CPUs to do a set_eiem(cpu_eiem) at the end 74 * of the interrupt handler */ 75 smp_send_all_nop(); 76 } 77 78 void cpu_ack_irq(unsigned int irq) 79 { 80 unsigned long mask = EIEM_MASK(irq); 81 int cpu = smp_processor_id(); 82 83 /* Clear in EIEM so we can no longer process */ 84 per_cpu(local_ack_eiem, cpu) &= ~mask; 85 86 /* disable the interrupt */ 87 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu)); 88 89 /* and now ack it */ 90 mtctl(mask, 23); 91 } 92 93 void cpu_eoi_irq(unsigned int irq) 94 { 95 unsigned long mask = EIEM_MASK(irq); 96 int cpu = smp_processor_id(); 97 98 /* set it in the eiems---it's no longer in process */ 99 per_cpu(local_ack_eiem, cpu) |= mask; 100 101 /* enable the interrupt */ 102 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu)); 103 } 104 105 #ifdef CONFIG_SMP 106 int cpu_check_affinity(unsigned int irq, const struct cpumask *dest) 107 { 108 int cpu_dest; 109 110 /* timer and ipi have to always be received on all CPUs */ 111 if (CHECK_IRQ_PER_CPU(irq)) { 112 /* Bad linux design decision. The mask has already 113 * been set; we must reset it */ 114 cpumask_setall(irq_desc[irq].affinity); 115 return -EINVAL; 116 } 117 118 /* whatever mask they set, we just allow one CPU */ 119 cpu_dest = first_cpu(*dest); 120 121 return cpu_dest; 122 } 123 124 static int cpu_set_affinity_irq(unsigned int irq, const struct cpumask *dest) 125 { 126 int cpu_dest; 127 128 cpu_dest = cpu_check_affinity(irq, dest); 129 if (cpu_dest < 0) 130 return -1; 131 132 cpumask_copy(irq_desc[irq].affinity, dest); 133 134 return 0; 135 } 136 #endif 137 138 static struct irq_chip cpu_interrupt_type = { 139 .name = "CPU", 140 .mask = cpu_mask_irq, 141 .unmask = cpu_unmask_irq, 142 .ack = cpu_ack_irq, 143 .eoi = cpu_eoi_irq, 144 #ifdef CONFIG_SMP 145 .set_affinity = cpu_set_affinity_irq, 146 #endif 147 /* XXX: Needs to be written. We managed without it so far, but 148 * we really ought to write it. 149 */ 150 .retrigger = NULL, 151 }; 152 153 int show_interrupts(struct seq_file *p, void *v) 154 { 155 int i = *(loff_t *) v, j; 156 unsigned long flags; 157 158 if (i == 0) { 159 seq_puts(p, " "); 160 for_each_online_cpu(j) 161 seq_printf(p, " CPU%d", j); 162 163 #ifdef PARISC_IRQ_CR16_COUNTS 164 seq_printf(p, " [min/avg/max] (CPU cycle counts)"); 165 #endif 166 seq_putc(p, '\n'); 167 } 168 169 if (i < NR_IRQS) { 170 struct irqaction *action; 171 172 raw_spin_lock_irqsave(&irq_desc[i].lock, flags); 173 action = irq_desc[i].action; 174 if (!action) 175 goto skip; 176 seq_printf(p, "%3d: ", i); 177 #ifdef CONFIG_SMP 178 for_each_online_cpu(j) 179 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); 180 #else 181 seq_printf(p, "%10u ", kstat_irqs(i)); 182 #endif 183 184 seq_printf(p, " %14s", irq_desc[i].chip->name); 185 #ifndef PARISC_IRQ_CR16_COUNTS 186 seq_printf(p, " %s", action->name); 187 188 while ((action = action->next)) 189 seq_printf(p, ", %s", action->name); 190 #else 191 for ( ;action; action = action->next) { 192 unsigned int k, avg, min, max; 193 194 min = max = action->cr16_hist[0]; 195 196 for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) { 197 int hist = action->cr16_hist[k]; 198 199 if (hist) { 200 avg += hist; 201 } else 202 break; 203 204 if (hist > max) max = hist; 205 if (hist < min) min = hist; 206 } 207 208 avg /= k; 209 seq_printf(p, " %s[%d/%d/%d]", action->name, 210 min,avg,max); 211 } 212 #endif 213 214 seq_putc(p, '\n'); 215 skip: 216 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); 217 } 218 219 return 0; 220 } 221 222 223 224 /* 225 ** The following form a "set": Virtual IRQ, Transaction Address, Trans Data. 226 ** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit. 227 ** 228 ** To use txn_XXX() interfaces, get a Virtual IRQ first. 229 ** Then use that to get the Transaction address and data. 230 */ 231 232 int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data) 233 { 234 if (irq_desc[irq].action) 235 return -EBUSY; 236 if (irq_desc[irq].chip != &cpu_interrupt_type) 237 return -EBUSY; 238 239 /* for iosapic interrupts */ 240 if (type) { 241 set_irq_chip_and_handler(irq, type, handle_percpu_irq); 242 set_irq_chip_data(irq, data); 243 cpu_unmask_irq(irq); 244 } 245 return 0; 246 } 247 248 int txn_claim_irq(int irq) 249 { 250 return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq; 251 } 252 253 /* 254 * The bits_wide parameter accommodates the limitations of the HW/SW which 255 * use these bits: 256 * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register) 257 * V-class (EPIC): 6 bits 258 * N/L/A-class (iosapic): 8 bits 259 * PCI 2.2 MSI: 16 bits 260 * Some PCI devices: 32 bits (Symbios SCSI/ATM/HyperFabric) 261 * 262 * On the service provider side: 263 * o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register) 264 * o PA 2.0 wide mode 6-bits (per processor) 265 * o IA64 8-bits (0-256 total) 266 * 267 * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported 268 * by the processor...and the N/L-class I/O subsystem supports more bits than 269 * PA2.0 has. The first case is the problem. 270 */ 271 int txn_alloc_irq(unsigned int bits_wide) 272 { 273 int irq; 274 275 /* never return irq 0 cause that's the interval timer */ 276 for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) { 277 if (cpu_claim_irq(irq, NULL, NULL) < 0) 278 continue; 279 if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide)) 280 continue; 281 return irq; 282 } 283 284 /* unlikely, but be prepared */ 285 return -1; 286 } 287 288 289 unsigned long txn_affinity_addr(unsigned int irq, int cpu) 290 { 291 #ifdef CONFIG_SMP 292 cpumask_copy(irq_desc[irq].affinity, cpumask_of(cpu)); 293 #endif 294 295 return per_cpu(cpu_data, cpu).txn_addr; 296 } 297 298 299 unsigned long txn_alloc_addr(unsigned int virt_irq) 300 { 301 static int next_cpu = -1; 302 303 next_cpu++; /* assign to "next" CPU we want this bugger on */ 304 305 /* validate entry */ 306 while ((next_cpu < nr_cpu_ids) && 307 (!per_cpu(cpu_data, next_cpu).txn_addr || 308 !cpu_online(next_cpu))) 309 next_cpu++; 310 311 if (next_cpu >= nr_cpu_ids) 312 next_cpu = 0; /* nothing else, assign monarch */ 313 314 return txn_affinity_addr(virt_irq, next_cpu); 315 } 316 317 318 unsigned int txn_alloc_data(unsigned int virt_irq) 319 { 320 return virt_irq - CPU_IRQ_BASE; 321 } 322 323 static inline int eirr_to_irq(unsigned long eirr) 324 { 325 int bit = fls_long(eirr); 326 return (BITS_PER_LONG - bit) + TIMER_IRQ; 327 } 328 329 /* ONLY called from entry.S:intr_extint() */ 330 void do_cpu_irq_mask(struct pt_regs *regs) 331 { 332 struct pt_regs *old_regs; 333 unsigned long eirr_val; 334 int irq, cpu = smp_processor_id(); 335 #ifdef CONFIG_SMP 336 cpumask_t dest; 337 #endif 338 339 old_regs = set_irq_regs(regs); 340 local_irq_disable(); 341 irq_enter(); 342 343 eirr_val = mfctl(23) & cpu_eiem & per_cpu(local_ack_eiem, cpu); 344 if (!eirr_val) 345 goto set_out; 346 irq = eirr_to_irq(eirr_val); 347 348 #ifdef CONFIG_SMP 349 cpumask_copy(&dest, irq_desc[irq].affinity); 350 if (CHECK_IRQ_PER_CPU(irq_desc[irq].status) && 351 !cpu_isset(smp_processor_id(), dest)) { 352 int cpu = first_cpu(dest); 353 354 printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n", 355 irq, smp_processor_id(), cpu); 356 gsc_writel(irq + CPU_IRQ_BASE, 357 per_cpu(cpu_data, cpu).hpa); 358 goto set_out; 359 } 360 #endif 361 generic_handle_irq(irq); 362 363 out: 364 irq_exit(); 365 set_irq_regs(old_regs); 366 return; 367 368 set_out: 369 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu)); 370 goto out; 371 } 372 373 static struct irqaction timer_action = { 374 .handler = timer_interrupt, 375 .name = "timer", 376 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_PERCPU | IRQF_IRQPOLL, 377 }; 378 379 #ifdef CONFIG_SMP 380 static struct irqaction ipi_action = { 381 .handler = ipi_interrupt, 382 .name = "IPI", 383 .flags = IRQF_DISABLED | IRQF_PERCPU, 384 }; 385 #endif 386 387 static void claim_cpu_irqs(void) 388 { 389 int i; 390 for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) { 391 set_irq_chip_and_handler(i, &cpu_interrupt_type, 392 handle_percpu_irq); 393 } 394 395 set_irq_handler(TIMER_IRQ, handle_percpu_irq); 396 setup_irq(TIMER_IRQ, &timer_action); 397 #ifdef CONFIG_SMP 398 set_irq_handler(IPI_IRQ, handle_percpu_irq); 399 setup_irq(IPI_IRQ, &ipi_action); 400 #endif 401 } 402 403 void __init init_IRQ(void) 404 { 405 local_irq_disable(); /* PARANOID - should already be disabled */ 406 mtctl(~0UL, 23); /* EIRR : clear all pending external intr */ 407 claim_cpu_irqs(); 408 #ifdef CONFIG_SMP 409 if (!cpu_eiem) 410 cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ); 411 #else 412 cpu_eiem = EIEM_MASK(TIMER_IRQ); 413 #endif 414 set_eiem(cpu_eiem); /* EIEM : enable all external intr */ 415 416 } 417 418