1 /* 2 * Code to handle x86 style IRQs plus some generic interrupt stuff. 3 * 4 * Copyright (C) 1992 Linus Torvalds 5 * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle 6 * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org) 7 * Copyright (C) 1999-2000 Grant Grundler 8 * Copyright (c) 2005 Matthew Wilcox 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2, or (at your option) 13 * any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 #include <linux/bitops.h> 25 #include <linux/errno.h> 26 #include <linux/init.h> 27 #include <linux/interrupt.h> 28 #include <linux/kernel_stat.h> 29 #include <linux/seq_file.h> 30 #include <linux/spinlock.h> 31 #include <linux/types.h> 32 #include <asm/io.h> 33 34 #include <asm/smp.h> 35 36 #undef PARISC_IRQ_CR16_COUNTS 37 38 extern irqreturn_t timer_interrupt(int, void *); 39 extern irqreturn_t ipi_interrupt(int, void *); 40 41 #define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq)) 42 43 /* Bits in EIEM correlate with cpu_irq_action[]. 44 ** Numbered *Big Endian*! (ie bit 0 is MSB) 45 */ 46 static volatile unsigned long cpu_eiem = 0; 47 48 /* 49 ** local ACK bitmap ... habitually set to 1, but reset to zero 50 ** between ->ack() and ->end() of the interrupt to prevent 51 ** re-interruption of a processing interrupt. 52 */ 53 static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL; 54 55 static void cpu_disable_irq(unsigned int irq) 56 { 57 unsigned long eirr_bit = EIEM_MASK(irq); 58 59 cpu_eiem &= ~eirr_bit; 60 /* Do nothing on the other CPUs. If they get this interrupt, 61 * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't 62 * handle it, and the set_eiem() at the bottom will ensure it 63 * then gets disabled */ 64 } 65 66 static void cpu_enable_irq(unsigned int irq) 67 { 68 unsigned long eirr_bit = EIEM_MASK(irq); 69 70 cpu_eiem |= eirr_bit; 71 72 /* This is just a simple NOP IPI. But what it does is cause 73 * all the other CPUs to do a set_eiem(cpu_eiem) at the end 74 * of the interrupt handler */ 75 smp_send_all_nop(); 76 } 77 78 static unsigned int cpu_startup_irq(unsigned int irq) 79 { 80 cpu_enable_irq(irq); 81 return 0; 82 } 83 84 void no_ack_irq(unsigned int irq) { } 85 void no_end_irq(unsigned int irq) { } 86 87 void cpu_ack_irq(unsigned int irq) 88 { 89 unsigned long mask = EIEM_MASK(irq); 90 int cpu = smp_processor_id(); 91 92 /* Clear in EIEM so we can no longer process */ 93 per_cpu(local_ack_eiem, cpu) &= ~mask; 94 95 /* disable the interrupt */ 96 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu)); 97 98 /* and now ack it */ 99 mtctl(mask, 23); 100 } 101 102 void cpu_end_irq(unsigned int irq) 103 { 104 unsigned long mask = EIEM_MASK(irq); 105 int cpu = smp_processor_id(); 106 107 /* set it in the eiems---it's no longer in process */ 108 per_cpu(local_ack_eiem, cpu) |= mask; 109 110 /* enable the interrupt */ 111 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu)); 112 } 113 114 #ifdef CONFIG_SMP 115 int cpu_check_affinity(unsigned int irq, const struct cpumask *dest) 116 { 117 int cpu_dest; 118 119 /* timer and ipi have to always be received on all CPUs */ 120 if (CHECK_IRQ_PER_CPU(irq)) { 121 /* Bad linux design decision. The mask has already 122 * been set; we must reset it */ 123 cpumask_setall(irq_desc[irq].affinity); 124 return -EINVAL; 125 } 126 127 /* whatever mask they set, we just allow one CPU */ 128 cpu_dest = first_cpu(*dest); 129 130 return cpu_dest; 131 } 132 133 static int cpu_set_affinity_irq(unsigned int irq, const struct cpumask *dest) 134 { 135 int cpu_dest; 136 137 cpu_dest = cpu_check_affinity(irq, dest); 138 if (cpu_dest < 0) 139 return -1; 140 141 cpumask_copy(irq_desc[irq].affinity, dest); 142 143 return 0; 144 } 145 #endif 146 147 static struct irq_chip cpu_interrupt_type = { 148 .typename = "CPU", 149 .startup = cpu_startup_irq, 150 .shutdown = cpu_disable_irq, 151 .enable = cpu_enable_irq, 152 .disable = cpu_disable_irq, 153 .ack = cpu_ack_irq, 154 .end = cpu_end_irq, 155 #ifdef CONFIG_SMP 156 .set_affinity = cpu_set_affinity_irq, 157 #endif 158 /* XXX: Needs to be written. We managed without it so far, but 159 * we really ought to write it. 160 */ 161 .retrigger = NULL, 162 }; 163 164 int show_interrupts(struct seq_file *p, void *v) 165 { 166 int i = *(loff_t *) v, j; 167 unsigned long flags; 168 169 if (i == 0) { 170 seq_puts(p, " "); 171 for_each_online_cpu(j) 172 seq_printf(p, " CPU%d", j); 173 174 #ifdef PARISC_IRQ_CR16_COUNTS 175 seq_printf(p, " [min/avg/max] (CPU cycle counts)"); 176 #endif 177 seq_putc(p, '\n'); 178 } 179 180 if (i < NR_IRQS) { 181 struct irqaction *action; 182 183 spin_lock_irqsave(&irq_desc[i].lock, flags); 184 action = irq_desc[i].action; 185 if (!action) 186 goto skip; 187 seq_printf(p, "%3d: ", i); 188 #ifdef CONFIG_SMP 189 for_each_online_cpu(j) 190 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); 191 #else 192 seq_printf(p, "%10u ", kstat_irqs(i)); 193 #endif 194 195 seq_printf(p, " %14s", irq_desc[i].chip->typename); 196 #ifndef PARISC_IRQ_CR16_COUNTS 197 seq_printf(p, " %s", action->name); 198 199 while ((action = action->next)) 200 seq_printf(p, ", %s", action->name); 201 #else 202 for ( ;action; action = action->next) { 203 unsigned int k, avg, min, max; 204 205 min = max = action->cr16_hist[0]; 206 207 for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) { 208 int hist = action->cr16_hist[k]; 209 210 if (hist) { 211 avg += hist; 212 } else 213 break; 214 215 if (hist > max) max = hist; 216 if (hist < min) min = hist; 217 } 218 219 avg /= k; 220 seq_printf(p, " %s[%d/%d/%d]", action->name, 221 min,avg,max); 222 } 223 #endif 224 225 seq_putc(p, '\n'); 226 skip: 227 spin_unlock_irqrestore(&irq_desc[i].lock, flags); 228 } 229 230 return 0; 231 } 232 233 234 235 /* 236 ** The following form a "set": Virtual IRQ, Transaction Address, Trans Data. 237 ** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit. 238 ** 239 ** To use txn_XXX() interfaces, get a Virtual IRQ first. 240 ** Then use that to get the Transaction address and data. 241 */ 242 243 int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data) 244 { 245 if (irq_desc[irq].action) 246 return -EBUSY; 247 if (irq_desc[irq].chip != &cpu_interrupt_type) 248 return -EBUSY; 249 250 if (type) { 251 irq_desc[irq].chip = type; 252 irq_desc[irq].chip_data = data; 253 cpu_interrupt_type.enable(irq); 254 } 255 return 0; 256 } 257 258 int txn_claim_irq(int irq) 259 { 260 return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq; 261 } 262 263 /* 264 * The bits_wide parameter accommodates the limitations of the HW/SW which 265 * use these bits: 266 * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register) 267 * V-class (EPIC): 6 bits 268 * N/L/A-class (iosapic): 8 bits 269 * PCI 2.2 MSI: 16 bits 270 * Some PCI devices: 32 bits (Symbios SCSI/ATM/HyperFabric) 271 * 272 * On the service provider side: 273 * o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register) 274 * o PA 2.0 wide mode 6-bits (per processor) 275 * o IA64 8-bits (0-256 total) 276 * 277 * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported 278 * by the processor...and the N/L-class I/O subsystem supports more bits than 279 * PA2.0 has. The first case is the problem. 280 */ 281 int txn_alloc_irq(unsigned int bits_wide) 282 { 283 int irq; 284 285 /* never return irq 0 cause that's the interval timer */ 286 for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) { 287 if (cpu_claim_irq(irq, NULL, NULL) < 0) 288 continue; 289 if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide)) 290 continue; 291 return irq; 292 } 293 294 /* unlikely, but be prepared */ 295 return -1; 296 } 297 298 299 unsigned long txn_affinity_addr(unsigned int irq, int cpu) 300 { 301 #ifdef CONFIG_SMP 302 cpumask_copy(irq_desc[irq].affinity, cpumask_of(cpu)); 303 #endif 304 305 return per_cpu(cpu_data, cpu).txn_addr; 306 } 307 308 309 unsigned long txn_alloc_addr(unsigned int virt_irq) 310 { 311 static int next_cpu = -1; 312 313 next_cpu++; /* assign to "next" CPU we want this bugger on */ 314 315 /* validate entry */ 316 while ((next_cpu < nr_cpu_ids) && 317 (!per_cpu(cpu_data, next_cpu).txn_addr || 318 !cpu_online(next_cpu))) 319 next_cpu++; 320 321 if (next_cpu >= nr_cpu_ids) 322 next_cpu = 0; /* nothing else, assign monarch */ 323 324 return txn_affinity_addr(virt_irq, next_cpu); 325 } 326 327 328 unsigned int txn_alloc_data(unsigned int virt_irq) 329 { 330 return virt_irq - CPU_IRQ_BASE; 331 } 332 333 static inline int eirr_to_irq(unsigned long eirr) 334 { 335 int bit = fls_long(eirr); 336 return (BITS_PER_LONG - bit) + TIMER_IRQ; 337 } 338 339 /* ONLY called from entry.S:intr_extint() */ 340 void do_cpu_irq_mask(struct pt_regs *regs) 341 { 342 struct pt_regs *old_regs; 343 unsigned long eirr_val; 344 int irq, cpu = smp_processor_id(); 345 #ifdef CONFIG_SMP 346 cpumask_t dest; 347 #endif 348 349 old_regs = set_irq_regs(regs); 350 local_irq_disable(); 351 irq_enter(); 352 353 eirr_val = mfctl(23) & cpu_eiem & per_cpu(local_ack_eiem, cpu); 354 if (!eirr_val) 355 goto set_out; 356 irq = eirr_to_irq(eirr_val); 357 358 #ifdef CONFIG_SMP 359 cpumask_copy(&dest, irq_desc[irq].affinity); 360 if (CHECK_IRQ_PER_CPU(irq_desc[irq].status) && 361 !cpu_isset(smp_processor_id(), dest)) { 362 int cpu = first_cpu(dest); 363 364 printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n", 365 irq, smp_processor_id(), cpu); 366 gsc_writel(irq + CPU_IRQ_BASE, 367 per_cpu(cpu_data, cpu).hpa); 368 goto set_out; 369 } 370 #endif 371 __do_IRQ(irq); 372 373 out: 374 irq_exit(); 375 set_irq_regs(old_regs); 376 return; 377 378 set_out: 379 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu)); 380 goto out; 381 } 382 383 static struct irqaction timer_action = { 384 .handler = timer_interrupt, 385 .name = "timer", 386 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_PERCPU | IRQF_IRQPOLL, 387 }; 388 389 #ifdef CONFIG_SMP 390 static struct irqaction ipi_action = { 391 .handler = ipi_interrupt, 392 .name = "IPI", 393 .flags = IRQF_DISABLED | IRQF_PERCPU, 394 }; 395 #endif 396 397 static void claim_cpu_irqs(void) 398 { 399 int i; 400 for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) { 401 irq_desc[i].chip = &cpu_interrupt_type; 402 } 403 404 irq_desc[TIMER_IRQ].action = &timer_action; 405 irq_desc[TIMER_IRQ].status = IRQ_PER_CPU; 406 #ifdef CONFIG_SMP 407 irq_desc[IPI_IRQ].action = &ipi_action; 408 irq_desc[IPI_IRQ].status = IRQ_PER_CPU; 409 #endif 410 } 411 412 void __init init_IRQ(void) 413 { 414 local_irq_disable(); /* PARANOID - should already be disabled */ 415 mtctl(~0UL, 23); /* EIRR : clear all pending external intr */ 416 claim_cpu_irqs(); 417 #ifdef CONFIG_SMP 418 if (!cpu_eiem) 419 cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ); 420 #else 421 cpu_eiem = EIEM_MASK(TIMER_IRQ); 422 #endif 423 set_eiem(cpu_eiem); /* EIEM : enable all external intr */ 424 425 } 426