1 /* 2 * Code to handle x86 style IRQs plus some generic interrupt stuff. 3 * 4 * Copyright (C) 1992 Linus Torvalds 5 * Copyright (C) 1994, 1995, 1996, 1997, 1998 Ralf Baechle 6 * Copyright (C) 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org) 7 * Copyright (C) 1999-2000 Grant Grundler 8 * Copyright (c) 2005 Matthew Wilcox 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2, or (at your option) 13 * any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 #include <linux/bitops.h> 25 #include <linux/errno.h> 26 #include <linux/init.h> 27 #include <linux/interrupt.h> 28 #include <linux/kernel_stat.h> 29 #include <linux/seq_file.h> 30 #include <linux/spinlock.h> 31 #include <linux/types.h> 32 #include <asm/io.h> 33 34 #include <asm/smp.h> 35 36 #undef PARISC_IRQ_CR16_COUNTS 37 38 extern irqreturn_t timer_interrupt(int, void *); 39 extern irqreturn_t ipi_interrupt(int, void *); 40 41 #define EIEM_MASK(irq) (1UL<<(CPU_IRQ_MAX - irq)) 42 43 /* Bits in EIEM correlate with cpu_irq_action[]. 44 ** Numbered *Big Endian*! (ie bit 0 is MSB) 45 */ 46 static volatile unsigned long cpu_eiem = 0; 47 48 /* 49 ** local ACK bitmap ... habitually set to 1, but reset to zero 50 ** between ->ack() and ->end() of the interrupt to prevent 51 ** re-interruption of a processing interrupt. 52 */ 53 static DEFINE_PER_CPU(unsigned long, local_ack_eiem) = ~0UL; 54 55 static void cpu_mask_irq(struct irq_data *d) 56 { 57 unsigned long eirr_bit = EIEM_MASK(d->irq); 58 59 cpu_eiem &= ~eirr_bit; 60 /* Do nothing on the other CPUs. If they get this interrupt, 61 * The & cpu_eiem in the do_cpu_irq_mask() ensures they won't 62 * handle it, and the set_eiem() at the bottom will ensure it 63 * then gets disabled */ 64 } 65 66 static void __cpu_unmask_irq(unsigned int irq) 67 { 68 unsigned long eirr_bit = EIEM_MASK(irq); 69 70 cpu_eiem |= eirr_bit; 71 72 /* This is just a simple NOP IPI. But what it does is cause 73 * all the other CPUs to do a set_eiem(cpu_eiem) at the end 74 * of the interrupt handler */ 75 smp_send_all_nop(); 76 } 77 78 static void cpu_unmask_irq(struct irq_data *d) 79 { 80 __cpu_unmask_irq(d->irq); 81 } 82 83 void cpu_ack_irq(struct irq_data *d) 84 { 85 unsigned long mask = EIEM_MASK(d->irq); 86 int cpu = smp_processor_id(); 87 88 /* Clear in EIEM so we can no longer process */ 89 per_cpu(local_ack_eiem, cpu) &= ~mask; 90 91 /* disable the interrupt */ 92 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu)); 93 94 /* and now ack it */ 95 mtctl(mask, 23); 96 } 97 98 void cpu_eoi_irq(struct irq_data *d) 99 { 100 unsigned long mask = EIEM_MASK(d->irq); 101 int cpu = smp_processor_id(); 102 103 /* set it in the eiems---it's no longer in process */ 104 per_cpu(local_ack_eiem, cpu) |= mask; 105 106 /* enable the interrupt */ 107 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu)); 108 } 109 110 #ifdef CONFIG_SMP 111 int cpu_check_affinity(struct irq_data *d, const struct cpumask *dest) 112 { 113 int cpu_dest; 114 115 /* timer and ipi have to always be received on all CPUs */ 116 if (CHECK_IRQ_PER_CPU(irq_to_desc(d->irq)->status)) { 117 /* Bad linux design decision. The mask has already 118 * been set; we must reset it. Will fix - tglx 119 */ 120 cpumask_setall(d->affinity); 121 return -EINVAL; 122 } 123 124 /* whatever mask they set, we just allow one CPU */ 125 cpu_dest = first_cpu(*dest); 126 127 return cpu_dest; 128 } 129 130 static int cpu_set_affinity_irq(struct irq_data *d, const struct cpumask *dest, 131 bool force) 132 { 133 int cpu_dest; 134 135 cpu_dest = cpu_check_affinity(d, dest); 136 if (cpu_dest < 0) 137 return -1; 138 139 cpumask_copy(d->affinity, dest); 140 141 return 0; 142 } 143 #endif 144 145 static struct irq_chip cpu_interrupt_type = { 146 .name = "CPU", 147 .irq_mask = cpu_mask_irq, 148 .irq_unmask = cpu_unmask_irq, 149 .irq_ack = cpu_ack_irq, 150 .irq_eoi = cpu_eoi_irq, 151 #ifdef CONFIG_SMP 152 .irq_set_affinity = cpu_set_affinity_irq, 153 #endif 154 /* XXX: Needs to be written. We managed without it so far, but 155 * we really ought to write it. 156 */ 157 .irq_retrigger = NULL, 158 }; 159 160 int show_interrupts(struct seq_file *p, void *v) 161 { 162 int i = *(loff_t *) v, j; 163 unsigned long flags; 164 165 if (i == 0) { 166 seq_puts(p, " "); 167 for_each_online_cpu(j) 168 seq_printf(p, " CPU%d", j); 169 170 #ifdef PARISC_IRQ_CR16_COUNTS 171 seq_printf(p, " [min/avg/max] (CPU cycle counts)"); 172 #endif 173 seq_putc(p, '\n'); 174 } 175 176 if (i < NR_IRQS) { 177 struct irqaction *action; 178 179 raw_spin_lock_irqsave(&irq_desc[i].lock, flags); 180 action = irq_desc[i].action; 181 if (!action) 182 goto skip; 183 seq_printf(p, "%3d: ", i); 184 #ifdef CONFIG_SMP 185 for_each_online_cpu(j) 186 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); 187 #else 188 seq_printf(p, "%10u ", kstat_irqs(i)); 189 #endif 190 191 seq_printf(p, " %14s", irq_desc[i].irq_data.chip->name); 192 #ifndef PARISC_IRQ_CR16_COUNTS 193 seq_printf(p, " %s", action->name); 194 195 while ((action = action->next)) 196 seq_printf(p, ", %s", action->name); 197 #else 198 for ( ;action; action = action->next) { 199 unsigned int k, avg, min, max; 200 201 min = max = action->cr16_hist[0]; 202 203 for (avg = k = 0; k < PARISC_CR16_HIST_SIZE; k++) { 204 int hist = action->cr16_hist[k]; 205 206 if (hist) { 207 avg += hist; 208 } else 209 break; 210 211 if (hist > max) max = hist; 212 if (hist < min) min = hist; 213 } 214 215 avg /= k; 216 seq_printf(p, " %s[%d/%d/%d]", action->name, 217 min,avg,max); 218 } 219 #endif 220 221 seq_putc(p, '\n'); 222 skip: 223 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); 224 } 225 226 return 0; 227 } 228 229 230 231 /* 232 ** The following form a "set": Virtual IRQ, Transaction Address, Trans Data. 233 ** Respectively, these map to IRQ region+EIRR, Processor HPA, EIRR bit. 234 ** 235 ** To use txn_XXX() interfaces, get a Virtual IRQ first. 236 ** Then use that to get the Transaction address and data. 237 */ 238 239 int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data) 240 { 241 if (irq_desc[irq].action) 242 return -EBUSY; 243 if (get_irq_chip(irq) != &cpu_interrupt_type) 244 return -EBUSY; 245 246 /* for iosapic interrupts */ 247 if (type) { 248 set_irq_chip_and_handler(irq, type, handle_percpu_irq); 249 set_irq_chip_data(irq, data); 250 __cpu_unmask_irq(irq); 251 } 252 return 0; 253 } 254 255 int txn_claim_irq(int irq) 256 { 257 return cpu_claim_irq(irq, NULL, NULL) ? -1 : irq; 258 } 259 260 /* 261 * The bits_wide parameter accommodates the limitations of the HW/SW which 262 * use these bits: 263 * Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register) 264 * V-class (EPIC): 6 bits 265 * N/L/A-class (iosapic): 8 bits 266 * PCI 2.2 MSI: 16 bits 267 * Some PCI devices: 32 bits (Symbios SCSI/ATM/HyperFabric) 268 * 269 * On the service provider side: 270 * o PA 1.1 (and PA2.0 narrow mode) 5-bits (width of EIR register) 271 * o PA 2.0 wide mode 6-bits (per processor) 272 * o IA64 8-bits (0-256 total) 273 * 274 * So a Legacy PA I/O device on a PA 2.0 box can't use all the bits supported 275 * by the processor...and the N/L-class I/O subsystem supports more bits than 276 * PA2.0 has. The first case is the problem. 277 */ 278 int txn_alloc_irq(unsigned int bits_wide) 279 { 280 int irq; 281 282 /* never return irq 0 cause that's the interval timer */ 283 for (irq = CPU_IRQ_BASE + 1; irq <= CPU_IRQ_MAX; irq++) { 284 if (cpu_claim_irq(irq, NULL, NULL) < 0) 285 continue; 286 if ((irq - CPU_IRQ_BASE) >= (1 << bits_wide)) 287 continue; 288 return irq; 289 } 290 291 /* unlikely, but be prepared */ 292 return -1; 293 } 294 295 296 unsigned long txn_affinity_addr(unsigned int irq, int cpu) 297 { 298 #ifdef CONFIG_SMP 299 struct irq_data *d = irq_get_irq_data(irq); 300 cpumask_copy(d->affinity, cpumask_of(cpu)); 301 #endif 302 303 return per_cpu(cpu_data, cpu).txn_addr; 304 } 305 306 307 unsigned long txn_alloc_addr(unsigned int virt_irq) 308 { 309 static int next_cpu = -1; 310 311 next_cpu++; /* assign to "next" CPU we want this bugger on */ 312 313 /* validate entry */ 314 while ((next_cpu < nr_cpu_ids) && 315 (!per_cpu(cpu_data, next_cpu).txn_addr || 316 !cpu_online(next_cpu))) 317 next_cpu++; 318 319 if (next_cpu >= nr_cpu_ids) 320 next_cpu = 0; /* nothing else, assign monarch */ 321 322 return txn_affinity_addr(virt_irq, next_cpu); 323 } 324 325 326 unsigned int txn_alloc_data(unsigned int virt_irq) 327 { 328 return virt_irq - CPU_IRQ_BASE; 329 } 330 331 static inline int eirr_to_irq(unsigned long eirr) 332 { 333 int bit = fls_long(eirr); 334 return (BITS_PER_LONG - bit) + TIMER_IRQ; 335 } 336 337 /* ONLY called from entry.S:intr_extint() */ 338 void do_cpu_irq_mask(struct pt_regs *regs) 339 { 340 struct pt_regs *old_regs; 341 unsigned long eirr_val; 342 int irq, cpu = smp_processor_id(); 343 #ifdef CONFIG_SMP 344 struct irq_desc *desc; 345 cpumask_t dest; 346 #endif 347 348 old_regs = set_irq_regs(regs); 349 local_irq_disable(); 350 irq_enter(); 351 352 eirr_val = mfctl(23) & cpu_eiem & per_cpu(local_ack_eiem, cpu); 353 if (!eirr_val) 354 goto set_out; 355 irq = eirr_to_irq(eirr_val); 356 357 #ifdef CONFIG_SMP 358 desc = irq_to_desc(irq); 359 cpumask_copy(&dest, desc->irq_data.affinity); 360 if (CHECK_IRQ_PER_CPU(desc->status) && 361 !cpu_isset(smp_processor_id(), dest)) { 362 int cpu = first_cpu(dest); 363 364 printk(KERN_DEBUG "redirecting irq %d from CPU %d to %d\n", 365 irq, smp_processor_id(), cpu); 366 gsc_writel(irq + CPU_IRQ_BASE, 367 per_cpu(cpu_data, cpu).hpa); 368 goto set_out; 369 } 370 #endif 371 generic_handle_irq(irq); 372 373 out: 374 irq_exit(); 375 set_irq_regs(old_regs); 376 return; 377 378 set_out: 379 set_eiem(cpu_eiem & per_cpu(local_ack_eiem, cpu)); 380 goto out; 381 } 382 383 static struct irqaction timer_action = { 384 .handler = timer_interrupt, 385 .name = "timer", 386 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_PERCPU | IRQF_IRQPOLL, 387 }; 388 389 #ifdef CONFIG_SMP 390 static struct irqaction ipi_action = { 391 .handler = ipi_interrupt, 392 .name = "IPI", 393 .flags = IRQF_DISABLED | IRQF_PERCPU, 394 }; 395 #endif 396 397 static void claim_cpu_irqs(void) 398 { 399 int i; 400 for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) { 401 set_irq_chip_and_handler(i, &cpu_interrupt_type, 402 handle_percpu_irq); 403 } 404 405 set_irq_handler(TIMER_IRQ, handle_percpu_irq); 406 setup_irq(TIMER_IRQ, &timer_action); 407 #ifdef CONFIG_SMP 408 set_irq_handler(IPI_IRQ, handle_percpu_irq); 409 setup_irq(IPI_IRQ, &ipi_action); 410 #endif 411 } 412 413 void __init init_IRQ(void) 414 { 415 local_irq_disable(); /* PARANOID - should already be disabled */ 416 mtctl(~0UL, 23); /* EIRR : clear all pending external intr */ 417 claim_cpu_irqs(); 418 #ifdef CONFIG_SMP 419 if (!cpu_eiem) 420 cpu_eiem = EIEM_MASK(IPI_IRQ) | EIEM_MASK(TIMER_IRQ); 421 #else 422 cpu_eiem = EIEM_MASK(TIMER_IRQ); 423 #endif 424 set_eiem(cpu_eiem); /* EIEM : enable all external intr */ 425 426 } 427 428