1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 #ifndef _UAPI_PARISC_PDC_H 3 #define _UAPI_PARISC_PDC_H 4 5 /* 6 * PDC return values ... 7 * All PDC calls return a subset of these errors. 8 */ 9 10 #define PDC_WARN 3 /* Call completed with a warning */ 11 #define PDC_REQ_ERR_1 2 /* See above */ 12 #define PDC_REQ_ERR_0 1 /* Call would generate a requestor error */ 13 #define PDC_OK 0 /* Call completed successfully */ 14 #define PDC_BAD_PROC -1 /* Called non-existent procedure*/ 15 #define PDC_BAD_OPTION -2 /* Called with non-existent option */ 16 #define PDC_ERROR -3 /* Call could not complete without an error */ 17 #define PDC_NE_MOD -5 /* Module not found */ 18 #define PDC_NE_CELL_MOD -7 /* Cell module not found */ 19 #define PDC_NE_BOOTDEV -9 /* Cannot locate a console device or boot device */ 20 #define PDC_INVALID_ARG -10 /* Called with an invalid argument */ 21 #define PDC_BUS_POW_WARN -12 /* Call could not complete in allowed power budget */ 22 #define PDC_NOT_NARROW -17 /* Narrow mode not supported */ 23 24 /* 25 * PDC entry points... 26 */ 27 28 #define PDC_POW_FAIL 1 /* perform a power-fail */ 29 #define PDC_POW_FAIL_PREPARE 0 /* prepare for powerfail */ 30 31 #define PDC_CHASSIS 2 /* PDC-chassis functions */ 32 #define PDC_CHASSIS_DISP 0 /* update chassis display */ 33 #define PDC_CHASSIS_WARN 1 /* return chassis warnings */ 34 #define PDC_CHASSIS_DISPWARN 2 /* update&return chassis status */ 35 #define PDC_RETURN_CHASSIS_INFO 128 /* HVERSION dependent: return chassis LED/LCD info */ 36 37 #define PDC_PIM 3 /* Get PIM data */ 38 #define PDC_PIM_HPMC 0 /* Transfer HPMC data */ 39 #define PDC_PIM_RETURN_SIZE 1 /* Get Max buffer needed for PIM*/ 40 #define PDC_PIM_LPMC 2 /* Transfer HPMC data */ 41 #define PDC_PIM_SOFT_BOOT 3 /* Transfer Soft Boot data */ 42 #define PDC_PIM_TOC 4 /* Transfer TOC data */ 43 44 #define PDC_MODEL 4 /* PDC model information call */ 45 #define PDC_MODEL_INFO 0 /* returns information */ 46 #define PDC_MODEL_BOOTID 1 /* set the BOOT_ID */ 47 #define PDC_MODEL_VERSIONS 2 /* returns cpu-internal versions*/ 48 #define PDC_MODEL_SYSMODEL 3 /* return system model info */ 49 #define PDC_MODEL_ENSPEC 4 /* enable specific option */ 50 #define PDC_MODEL_DISPEC 5 /* disable specific option */ 51 #define PDC_MODEL_CPU_ID 6 /* returns cpu-id (only newer machines!) */ 52 #define PDC_MODEL_CAPABILITIES 7 /* returns OS32/OS64-flags */ 53 /* Values for PDC_MODEL_CAPABILITIES non-equivalent virtual aliasing support */ 54 #define PDC_MODEL_OS64 (1 << 0) 55 #define PDC_MODEL_OS32 (1 << 1) 56 #define PDC_MODEL_IOPDIR_FDC (1 << 2) 57 #define PDC_MODEL_NVA_MASK (3 << 4) 58 #define PDC_MODEL_NVA_SUPPORTED (0 << 4) 59 #define PDC_MODEL_NVA_SLOW (1 << 4) 60 #define PDC_MODEL_NVA_UNSUPPORTED (3 << 4) 61 #define PDC_MODEL_GET_BOOT__OP 8 /* returns boot test options */ 62 #define PDC_MODEL_SET_BOOT__OP 9 /* set boot test options */ 63 #define PDC_MODEL_GET_PLATFORM_INFO 10 /* returns platform info */ 64 #define PDC_MODEL_GET_INSTALL_KERNEL 11 /* returns kernel for installation */ 65 66 #define PA89_INSTRUCTION_SET 0x4 /* capabilities returned */ 67 #define PA90_INSTRUCTION_SET 0x8 68 69 #define PDC_CACHE 5 /* return/set cache (& TLB) info*/ 70 #define PDC_CACHE_INFO 0 /* returns information */ 71 #define PDC_CACHE_SET_COH 1 /* set coherence state */ 72 #define PDC_CACHE_RET_SPID 2 /* returns space-ID bits */ 73 74 #define PDC_HPA 6 /* return HPA of processor */ 75 #define PDC_HPA_PROCESSOR 0 76 #define PDC_HPA_MODULES 1 77 78 #define PDC_COPROC 7 /* Co-Processor (usually FP unit(s)) */ 79 #define PDC_COPROC_CFG 0 /* Co-Processor Cfg (FP unit(s) enabled?) */ 80 81 #define PDC_IODC 8 /* talk to IODC */ 82 #define PDC_IODC_READ 0 /* read IODC entry point */ 83 /* PDC_IODC_RI_ * INDEX parameter of PDC_IODC_READ */ 84 #define PDC_IODC_RI_DATA_BYTES 0 /* IODC Data Bytes */ 85 /* 1, 2 obsolete - HVERSION dependent*/ 86 #define PDC_IODC_RI_INIT 3 /* Initialize module */ 87 #define PDC_IODC_RI_IO 4 /* Module input/output */ 88 #define PDC_IODC_RI_SPA 5 /* Module input/output */ 89 #define PDC_IODC_RI_CONFIG 6 /* Module input/output */ 90 /* 7 obsolete - HVERSION dependent */ 91 #define PDC_IODC_RI_TEST 8 /* Module input/output */ 92 #define PDC_IODC_RI_TLB 9 /* Module input/output */ 93 #define PDC_IODC_NINIT 2 /* non-destructive init */ 94 #define PDC_IODC_DINIT 3 /* destructive init */ 95 #define PDC_IODC_MEMERR 4 /* check for memory errors */ 96 #define PDC_IODC_INDEX_DATA 0 /* get first 16 bytes from mod IODC */ 97 #define PDC_IODC_BUS_ERROR -4 /* bus error return value */ 98 #define PDC_IODC_INVALID_INDEX -5 /* invalid index return value */ 99 #define PDC_IODC_COUNT -6 /* count is too small */ 100 101 #define PDC_TOD 9 /* time-of-day clock (TOD) */ 102 #define PDC_TOD_READ 0 /* read TOD */ 103 #define PDC_TOD_WRITE 1 /* write TOD */ 104 #define PDC_TOD_CALIBRATE 2 /* calibrate timers */ 105 106 #define PDC_STABLE 10 /* stable storage (sprockets) */ 107 #define PDC_STABLE_READ 0 108 #define PDC_STABLE_WRITE 1 109 #define PDC_STABLE_RETURN_SIZE 2 110 #define PDC_STABLE_VERIFY_CONTENTS 3 111 #define PDC_STABLE_INITIALIZE 4 112 113 #define PDC_NVOLATILE 11 /* often not implemented */ 114 #define PDC_NVOLATILE_READ 0 115 #define PDC_NVOLATILE_WRITE 1 116 #define PDC_NVOLATILE_RETURN_SIZE 2 117 #define PDC_NVOLATILE_VERIFY_CONTENTS 3 118 #define PDC_NVOLATILE_INITIALIZE 4 119 120 #define PDC_ADD_VALID 12 /* Memory validation PDC call */ 121 #define PDC_ADD_VALID_VERIFY 0 /* Make PDC_ADD_VALID verify region */ 122 123 #define PDC_DEBUG 14 /* Obsolete */ 124 125 #define PDC_INSTR 15 /* get instr to invoke PDCE_CHECK() */ 126 127 #define PDC_PROC 16 /* (sprockets) */ 128 129 #define PDC_CONFIG 17 /* (sprockets) */ 130 #define PDC_CONFIG_DECONFIG 0 131 #define PDC_CONFIG_DRECONFIG 1 132 #define PDC_CONFIG_DRETURN_CONFIG 2 133 134 #define PDC_BLOCK_TLB 18 /* manage hardware block-TLB */ 135 #define PDC_BTLB_INFO 0 /* returns parameter */ 136 #define PDC_BTLB_INSERT 1 /* insert BTLB entry */ 137 #define PDC_BTLB_PURGE 2 /* purge BTLB entries */ 138 #define PDC_BTLB_PURGE_ALL 3 /* purge all BTLB entries */ 139 140 #define PDC_TLB 19 /* manage hardware TLB miss handling */ 141 #define PDC_TLB_INFO 0 /* returns parameter */ 142 #define PDC_TLB_SETUP 1 /* set up miss handling */ 143 144 #define PDC_MEM 20 /* Manage memory */ 145 #define PDC_MEM_MEMINFO 0 /* Return PDT info */ 146 #define PDC_MEM_ADD_PAGE 1 /* Add page to PDT */ 147 #define PDC_MEM_CLEAR_PDT 2 /* Clear PDT */ 148 #define PDC_MEM_READ_PDT 3 /* Read PDT entry */ 149 #define PDC_MEM_RESET_CLEAR 4 /* Reset PDT clear flag */ 150 #define PDC_MEM_GOODMEM 5 /* Set good_mem value */ 151 #define PDC_MEM_TABLE 128 /* Non contig mem map (sprockets) */ 152 #define PDC_MEM_RETURN_ADDRESS_TABLE PDC_MEM_TABLE 153 #define PDC_MEM_GET_MEMORY_SYSTEM_TABLES_SIZE 131 154 #define PDC_MEM_GET_MEMORY_SYSTEM_TABLES 132 155 #define PDC_MEM_GET_PHYSICAL_LOCATION_FROM_MEMORY_ADDRESS 133 156 157 #define PDC_MEM_RET_SBE_REPLACED 5 /* PDC_MEM return values */ 158 #define PDC_MEM_RET_DUPLICATE_ENTRY 4 159 #define PDC_MEM_RET_BUF_SIZE_SMALL 1 160 #define PDC_MEM_RET_PDT_FULL -11 161 #define PDC_MEM_RET_INVALID_PHYSICAL_LOCATION ~0ULL 162 163 #define PDC_PSW 21 /* Get/Set default System Mask */ 164 #define PDC_PSW_MASK 0 /* Return mask */ 165 #define PDC_PSW_GET_DEFAULTS 1 /* Return defaults */ 166 #define PDC_PSW_SET_DEFAULTS 2 /* Set default */ 167 #define PDC_PSW_ENDIAN_BIT 1 /* set for big endian */ 168 #define PDC_PSW_WIDE_BIT 2 /* set for wide mode */ 169 170 #define PDC_SYSTEM_MAP 22 /* find system modules */ 171 #define PDC_FIND_MODULE 0 172 #define PDC_FIND_ADDRESS 1 173 #define PDC_TRANSLATE_PATH 2 174 175 #define PDC_SOFT_POWER 23 /* soft power switch */ 176 #define PDC_SOFT_POWER_INFO 0 /* return info about the soft power switch */ 177 #define PDC_SOFT_POWER_ENABLE 1 /* enable/disable soft power switch */ 178 179 #define PDC_ALLOC 24 /* allocate static storage for PDC & IODC */ 180 181 #define PDC_CRASH_PREP 25 /* Prepare system for crash dump */ 182 #define PDC_CRASH_DUMP 0 /* Do platform specific preparations for dump */ 183 #define PDC_CRASH_LOG_CEC_ERROR 1 /* Dump hardware registers */ 184 185 #define PDC_SCSI_PARMS 26 /* Get and set SCSI parameters */ 186 #define PDC_SCSI_GET_PARMS 0 /* Get SCSI parameters for I/O device */ 187 #define PDC_SCSI_SET_PARMS 1 /* Set SCSI parameters for I/O device */ 188 189 /* HVERSION dependent */ 190 191 /* The PDC_MEM_MAP calls */ 192 #define PDC_MEM_MAP 128 /* on s700: return page info */ 193 #define PDC_MEM_MAP_HPA 0 /* returns hpa of a module */ 194 195 #define PDC_EEPROM 129 /* EEPROM access */ 196 #define PDC_EEPROM_READ_WORD 0 197 #define PDC_EEPROM_WRITE_WORD 1 198 #define PDC_EEPROM_READ_BYTE 2 199 #define PDC_EEPROM_WRITE_BYTE 3 200 #define PDC_EEPROM_EEPROM_PASSWORD -1000 201 202 #define PDC_NVM 130 /* NVM (non-volatile memory) access */ 203 #define PDC_NVM_READ_WORD 0 204 #define PDC_NVM_WRITE_WORD 1 205 #define PDC_NVM_READ_BYTE 2 206 #define PDC_NVM_WRITE_BYTE 3 207 208 #define PDC_SEED_ERROR 132 /* (sprockets) */ 209 210 #define PDC_IO 135 /* log error info, reset IO system */ 211 #define PDC_IO_READ_AND_CLEAR_ERRORS 0 212 #define PDC_IO_RESET 1 213 #define PDC_IO_RESET_DEVICES 2 214 /* sets bits 6&7 (little endian) of the HcControl Register */ 215 #define PDC_IO_USB_SUSPEND 0xC000000000000000 216 #define PDC_IO_EEPROM_IO_ERR_TABLE_FULL -5 /* return value */ 217 #define PDC_IO_NO_SUSPEND -6 /* return value */ 218 219 #define PDC_BROADCAST_RESET 136 /* reset all processors */ 220 #define PDC_DO_RESET 0 /* option: perform a broadcast reset */ 221 #define PDC_DO_FIRM_TEST_RESET 1 /* Do broadcast reset with bitmap */ 222 #define PDC_BR_RECONFIGURATION 2 /* reset w/reconfiguration */ 223 #define PDC_FIRM_TEST_MAGIC 0xab9ec36fUL /* for this reboot only */ 224 225 #define PDC_LAN_STATION_ID 138 /* Hversion dependent mechanism for */ 226 #define PDC_LAN_STATION_ID_READ 0 /* getting the lan station address */ 227 228 #define PDC_LAN_STATION_ID_SIZE 6 229 230 #define PDC_CHECK_RANGES 139 /* (sprockets) */ 231 232 #define PDC_NV_SECTIONS 141 /* (sprockets) */ 233 234 #define PDC_PERFORMANCE 142 /* performance monitoring */ 235 236 #define PDC_SYSTEM_INFO 143 /* system information */ 237 #define PDC_SYSINFO_RETURN_INFO_SIZE 0 238 #define PDC_SYSINFO_RRETURN_SYS_INFO 1 239 #define PDC_SYSINFO_RRETURN_ERRORS 2 240 #define PDC_SYSINFO_RRETURN_WARNINGS 3 241 #define PDC_SYSINFO_RETURN_REVISIONS 4 242 #define PDC_SYSINFO_RRETURN_DIAGNOSE 5 243 #define PDC_SYSINFO_RRETURN_HV_DIAGNOSE 1005 244 245 #define PDC_RDR 144 /* (sprockets) */ 246 #define PDC_RDR_READ_BUFFER 0 247 #define PDC_RDR_READ_SINGLE 1 248 #define PDC_RDR_WRITE_SINGLE 2 249 250 #define PDC_INTRIGUE 145 /* (sprockets) */ 251 #define PDC_INTRIGUE_WRITE_BUFFER 0 252 #define PDC_INTRIGUE_GET_SCRATCH_BUFSIZE 1 253 #define PDC_INTRIGUE_START_CPU_COUNTERS 2 254 #define PDC_INTRIGUE_STOP_CPU_COUNTERS 3 255 256 #define PDC_STI 146 /* STI access */ 257 /* same as PDC_PCI_XXX values (see below) */ 258 259 /* Legacy PDC definitions for same stuff */ 260 #define PDC_PCI_INDEX 147 261 #define PDC_PCI_INTERFACE_INFO 0 262 #define PDC_PCI_SLOT_INFO 1 263 #define PDC_PCI_INFLIGHT_BYTES 2 264 #define PDC_PCI_READ_CONFIG 3 265 #define PDC_PCI_WRITE_CONFIG 4 266 #define PDC_PCI_READ_PCI_IO 5 267 #define PDC_PCI_WRITE_PCI_IO 6 268 #define PDC_PCI_READ_CONFIG_DELAY 7 269 #define PDC_PCI_UPDATE_CONFIG_DELAY 8 270 #define PDC_PCI_PCI_PATH_TO_PCI_HPA 9 271 #define PDC_PCI_PCI_HPA_TO_PCI_PATH 10 272 #define PDC_PCI_PCI_PATH_TO_PCI_BUS 11 273 #define PDC_PCI_PCI_RESERVED 12 274 #define PDC_PCI_PCI_INT_ROUTE_SIZE 13 275 #define PDC_PCI_GET_INT_TBL_SIZE PDC_PCI_PCI_INT_ROUTE_SIZE 276 #define PDC_PCI_PCI_INT_ROUTE 14 277 #define PDC_PCI_GET_INT_TBL PDC_PCI_PCI_INT_ROUTE 278 #define PDC_PCI_READ_MON_TYPE 15 279 #define PDC_PCI_WRITE_MON_TYPE 16 280 281 #define PDC_RELOCATE 149 /* (sprockets) */ 282 #define PDC_RELOCATE_GET_RELOCINFO 0 283 #define PDC_RELOCATE_CHECKSUM 1 284 #define PDC_RELOCATE_RELOCATE 2 285 286 /* Get SCSI Interface Card info: SDTR, SCSI ID, mode (SE vs LVD) */ 287 #define PDC_INITIATOR 163 288 #define PDC_GET_INITIATOR 0 289 #define PDC_SET_INITIATOR 1 290 #define PDC_DELETE_INITIATOR 2 291 #define PDC_RETURN_TABLE_SIZE 3 292 #define PDC_RETURN_TABLE 4 293 294 #define PDC_LINK 165 /* (sprockets) */ 295 #define PDC_LINK_PCI_ENTRY_POINTS 0 /* list (Arg1) = 0 */ 296 #define PDC_LINK_USB_ENTRY_POINTS 1 /* list (Arg1) = 1 */ 297 298 /* cl_class 299 * page 3-33 of IO-Firmware ARS 300 * IODC ENTRY_INIT(Search first) RET[1] 301 */ 302 #define CL_NULL 0 /* invalid */ 303 #define CL_RANDOM 1 /* random access (as disk) */ 304 #define CL_SEQU 2 /* sequential access (as tape) */ 305 #define CL_DUPLEX 7 /* full-duplex point-to-point (RS-232, Net) */ 306 #define CL_KEYBD 8 /* half-duplex console (HIL Keyboard) */ 307 #define CL_DISPL 9 /* half-duplex console (display) */ 308 #define CL_FC 10 /* FiberChannel access media */ 309 310 /* IODC ENTRY_INIT() */ 311 #define ENTRY_INIT_SRCH_FRST 2 312 #define ENTRY_INIT_SRCH_NEXT 3 313 #define ENTRY_INIT_MOD_DEV 4 314 #define ENTRY_INIT_DEV 5 315 #define ENTRY_INIT_MOD 6 316 #define ENTRY_INIT_MSG 9 317 318 /* IODC ENTRY_IO() */ 319 #define ENTRY_IO_BOOTIN 0 320 #define ENTRY_IO_BOOTOUT 1 321 #define ENTRY_IO_CIN 2 322 #define ENTRY_IO_COUT 3 323 #define ENTRY_IO_CLOSE 4 324 #define ENTRY_IO_GETMSG 9 325 #define ENTRY_IO_BBLOCK_IN 16 326 #define ENTRY_IO_BBLOCK_OUT 17 327 328 /* IODC ENTRY_SPA() */ 329 330 /* IODC ENTRY_CONFIG() */ 331 332 /* IODC ENTRY_TEST() */ 333 334 /* IODC ENTRY_TLB() */ 335 336 /* constants for OS (NVM...) */ 337 #define OS_ID_NONE 0 /* Undefined OS ID */ 338 #define OS_ID_HPUX 1 /* HP-UX OS */ 339 #define OS_ID_MPEXL 2 /* MPE XL OS */ 340 #define OS_ID_OSF 3 /* OSF OS */ 341 #define OS_ID_HPRT 4 /* HP-RT OS */ 342 #define OS_ID_NOVEL 5 /* NOVELL OS */ 343 #define OS_ID_LINUX 6 /* Linux */ 344 345 346 /* constants for PDC_CHASSIS */ 347 #define OSTAT_OFF 0 348 #define OSTAT_FLT 1 349 #define OSTAT_TEST 2 350 #define OSTAT_INIT 3 351 #define OSTAT_SHUT 4 352 #define OSTAT_WARN 5 353 #define OSTAT_RUN 6 354 #define OSTAT_ON 7 355 356 /* Page Zero constant offsets used by the HPMC handler */ 357 #define BOOT_CONSOLE_HPA_OFFSET 0x3c0 358 #define BOOT_CONSOLE_SPA_OFFSET 0x3c4 359 #define BOOT_CONSOLE_PATH_OFFSET 0x3a8 360 361 /* size of the pdc_result buffer for firmware.c */ 362 #define NUM_PDC_RESULT 32 363 364 #if !defined(__ASSEMBLY__) 365 366 /* flags for hardware_path */ 367 #define PF_AUTOBOOT 0x80 368 #define PF_AUTOSEARCH 0x40 369 #define PF_TIMER 0x0F 370 371 struct hardware_path { 372 unsigned char flags; /* see bit definitions below */ 373 signed char bc[6]; /* Bus Converter routing info to a specific */ 374 /* I/O adaptor (< 0 means none, > 63 resvd) */ 375 signed char mod; /* fixed field of specified module */ 376 }; 377 378 struct pdc_module_path { /* page 1-69 */ 379 struct hardware_path path; 380 unsigned int layers[6]; /* device-specific info (ctlr #, unit # ...) */ 381 } __attribute__((aligned(8))); 382 383 struct pz_device { 384 struct pdc_module_path dp; /* see above */ 385 /* struct iomod *hpa; */ 386 unsigned int hpa; /* HPA base address */ 387 /* char *spa; */ 388 unsigned int spa; /* SPA base address */ 389 /* int (*iodc_io)(struct iomod*, ...); */ 390 unsigned int iodc_io; /* device entry point */ 391 short pad; /* reserved */ 392 unsigned short cl_class;/* see below */ 393 } __attribute__((aligned(8))) ; 394 395 struct zeropage { 396 /* [0x000] initialize vectors (VEC) */ 397 unsigned int vec_special; /* must be zero */ 398 /* int (*vec_pow_fail)(void);*/ 399 unsigned int vec_pow_fail; /* power failure handler */ 400 /* int (*vec_toc)(void); */ 401 unsigned int vec_toc; 402 unsigned int vec_toclen; 403 /* int (*vec_rendz)(void); */ 404 unsigned int vec_rendz; 405 int vec_pow_fail_flen; 406 int vec_pad0[3]; 407 unsigned int vec_toc_hi; 408 int vec_pad1[6]; 409 410 /* [0x040] reserved processor dependent */ 411 int pad0[112]; /* in QEMU pad0[0] holds "SeaBIOS\0" */ 412 413 /* [0x200] reserved */ 414 int pad1[84]; 415 416 /* [0x350] memory configuration (MC) */ 417 int memc_cont; /* contiguous mem size (bytes) */ 418 int memc_phsize; /* physical memory size */ 419 int memc_adsize; /* additional mem size, bytes of SPA space used by PDC */ 420 unsigned int mem_pdc_hi; /* used for 64-bit */ 421 422 /* [0x360] various parameters for the boot-CPU */ 423 /* unsigned int *mem_booterr[8]; */ 424 unsigned int mem_booterr[8]; /* ptr to boot errors */ 425 unsigned int mem_free; /* first location, where OS can be loaded */ 426 /* struct iomod *mem_hpa; */ 427 unsigned int mem_hpa; /* HPA of the boot-CPU */ 428 /* int (*mem_pdc)(int, ...); */ 429 unsigned int mem_pdc; /* PDC entry point */ 430 unsigned int mem_10msec; /* number of clock ticks in 10msec */ 431 432 /* [0x390] initial memory module (IMM) */ 433 /* struct iomod *imm_hpa; */ 434 unsigned int imm_hpa; /* HPA of the IMM */ 435 int imm_soft_boot; /* 0 = was hard boot, 1 = was soft boot */ 436 unsigned int imm_spa_size; /* SPA size of the IMM in bytes */ 437 unsigned int imm_max_mem; /* bytes of mem in IMM */ 438 439 /* [0x3A0] boot console, display device and keyboard */ 440 struct pz_device mem_cons; /* description of console device */ 441 struct pz_device mem_boot; /* description of boot device */ 442 struct pz_device mem_kbd; /* description of keyboard device */ 443 444 /* [0x430] reserved */ 445 int pad430[116]; 446 447 /* [0x600] processor dependent */ 448 unsigned int pad600[1]; 449 unsigned int proc_sti; /* pointer to STI ROM */ 450 unsigned int pad608[126]; 451 }; 452 453 struct pdc_chassis_info { /* for PDC_CHASSIS_INFO */ 454 unsigned long actcnt; /* actual number of bytes returned */ 455 unsigned long maxcnt; /* maximum number of bytes that could be returned */ 456 }; 457 458 struct pdc_coproc_cfg { /* for PDC_COPROC_CFG */ 459 unsigned long ccr_functional; 460 unsigned long ccr_present; 461 unsigned long revision; 462 unsigned long model; 463 }; 464 465 struct pdc_model { /* for PDC_MODEL */ 466 unsigned long hversion; 467 unsigned long sversion; 468 unsigned long hw_id; 469 unsigned long boot_id; 470 unsigned long sw_id; 471 unsigned long sw_cap; 472 unsigned long arch_rev; 473 unsigned long pot_key; 474 unsigned long curr_key; 475 }; 476 477 struct pdc_cache_cf { /* for PDC_CACHE (I/D-caches) */ 478 unsigned long 479 #ifdef __LP64__ 480 cc_padW:32, 481 #endif 482 cc_alias: 4, /* alias boundaries for virtual addresses */ 483 cc_block: 4, /* to determine most efficient stride */ 484 cc_line : 3, /* maximum amount written back as a result of store (multiple of 16 bytes) */ 485 cc_shift: 2, /* how much to shift cc_block left */ 486 cc_wt : 1, /* 0 = WT-Dcache, 1 = WB-Dcache */ 487 cc_sh : 2, /* 0 = separate I/D-cache, else shared I/D-cache */ 488 cc_cst : 3, /* 0 = incoherent D-cache, 1=coherent D-cache */ 489 cc_pad1 : 10, /* reserved */ 490 cc_hv : 3; /* hversion dependent */ 491 }; 492 493 struct pdc_tlb_cf { /* for PDC_CACHE (I/D-TLB's) */ 494 unsigned long tc_pad0:12, /* reserved */ 495 #ifdef __LP64__ 496 tc_padW:32, 497 #endif 498 tc_sh : 2, /* 0 = separate I/D-TLB, else shared I/D-TLB */ 499 tc_hv : 1, /* HV */ 500 tc_page : 1, /* 0 = 2K page-size-machine, 1 = 4k page size */ 501 tc_cst : 3, /* 0 = incoherent operations, else coherent operations */ 502 tc_aid : 5, /* ITLB: width of access ids of processor (encoded!) */ 503 tc_sr : 8; /* ITLB: width of space-registers (encoded) */ 504 }; 505 506 struct pdc_cache_info { /* main-PDC_CACHE-structure (caches & TLB's) */ 507 /* I-cache */ 508 unsigned long ic_size; /* size in bytes */ 509 struct pdc_cache_cf ic_conf; /* configuration */ 510 unsigned long ic_base; /* base-addr */ 511 unsigned long ic_stride; 512 unsigned long ic_count; 513 unsigned long ic_loop; 514 /* D-cache */ 515 unsigned long dc_size; /* size in bytes */ 516 struct pdc_cache_cf dc_conf; /* configuration */ 517 unsigned long dc_base; /* base-addr */ 518 unsigned long dc_stride; 519 unsigned long dc_count; 520 unsigned long dc_loop; 521 /* Instruction-TLB */ 522 unsigned long it_size; /* number of entries in I-TLB */ 523 struct pdc_tlb_cf it_conf; /* I-TLB-configuration */ 524 unsigned long it_sp_base; 525 unsigned long it_sp_stride; 526 unsigned long it_sp_count; 527 unsigned long it_off_base; 528 unsigned long it_off_stride; 529 unsigned long it_off_count; 530 unsigned long it_loop; 531 /* data-TLB */ 532 unsigned long dt_size; /* number of entries in D-TLB */ 533 struct pdc_tlb_cf dt_conf; /* D-TLB-configuration */ 534 unsigned long dt_sp_base; 535 unsigned long dt_sp_stride; 536 unsigned long dt_sp_count; 537 unsigned long dt_off_base; 538 unsigned long dt_off_stride; 539 unsigned long dt_off_count; 540 unsigned long dt_loop; 541 }; 542 543 /* Might need adjustment to work with 64-bit firmware */ 544 struct pdc_iodc { /* PDC_IODC */ 545 unsigned char hversion_model; 546 unsigned char hversion; 547 unsigned char spa; 548 unsigned char type; 549 unsigned int sversion_rev:4; 550 unsigned int sversion_model:19; 551 unsigned int sversion_opt:8; 552 unsigned char rev; 553 unsigned char dep; 554 unsigned char features; 555 unsigned char pad1; 556 unsigned int checksum:16; 557 unsigned int length:16; 558 unsigned int pad[15]; 559 } __attribute__((aligned(8))) ; 560 561 /* no BLTBs in pa2.0 processors */ 562 struct pdc_btlb_info_range { 563 unsigned char res00; 564 unsigned char num_i; 565 unsigned char num_d; 566 unsigned char num_comb; 567 }; 568 569 struct pdc_btlb_info { /* PDC_BLOCK_TLB, return of PDC_BTLB_INFO */ 570 unsigned int min_size; /* minimum size of BTLB in pages */ 571 unsigned int max_size; /* maximum size of BTLB in pages */ 572 struct pdc_btlb_info_range fixed_range_info; 573 struct pdc_btlb_info_range variable_range_info; 574 }; 575 576 struct pdc_mem_retinfo { /* PDC_MEM/PDC_MEM_MEMINFO (return info) */ 577 unsigned long pdt_size; 578 unsigned long pdt_entries; 579 unsigned long pdt_status; 580 unsigned long first_dbe_loc; 581 unsigned long good_mem; 582 }; 583 584 struct pdc_mem_read_pdt { /* PDC_MEM/PDC_MEM_READ_PDT (return info) */ 585 unsigned long pdt_entries; 586 }; 587 588 #ifdef __LP64__ 589 struct pdc_memory_table_raddr { /* PDC_MEM/PDC_MEM_TABLE (return info) */ 590 unsigned long entries_returned; 591 unsigned long entries_total; 592 }; 593 594 struct pdc_memory_table { /* PDC_MEM/PDC_MEM_TABLE (arguments) */ 595 unsigned long paddr; 596 unsigned int pages; 597 unsigned int reserved; 598 }; 599 #endif /* __LP64__ */ 600 601 struct pdc_system_map_mod_info { /* PDC_SYSTEM_MAP/FIND_MODULE */ 602 unsigned long mod_addr; 603 unsigned long mod_pgs; 604 unsigned long add_addrs; 605 }; 606 607 struct pdc_system_map_addr_info { /* PDC_SYSTEM_MAP/FIND_ADDRESS */ 608 unsigned long mod_addr; 609 unsigned long mod_pgs; 610 }; 611 612 struct pdc_initiator { /* PDC_INITIATOR */ 613 int host_id; 614 int factor; 615 int width; 616 int mode; 617 }; 618 619 /* Only used on some pre-PA2.0 boxes */ 620 struct pdc_memory_map { /* PDC_MEMORY_MAP */ 621 unsigned long hpa; /* mod's register set address */ 622 unsigned long more_pgs; /* number of additional I/O pgs */ 623 }; 624 625 struct pdc_tod { 626 unsigned long tod_sec; 627 unsigned long tod_usec; 628 }; 629 630 /* architected results from PDC_PIM/transfer hpmc on a PA1.1 machine */ 631 632 struct pdc_hpmc_pim_11 { /* PDC_PIM */ 633 unsigned int gr[32]; 634 unsigned int cr[32]; 635 unsigned int sr[8]; 636 unsigned int iasq_back; 637 unsigned int iaoq_back; 638 unsigned int check_type; 639 unsigned int cpu_state; 640 unsigned int rsvd1; 641 unsigned int cache_check; 642 unsigned int tlb_check; 643 unsigned int bus_check; 644 unsigned int assists_check; 645 unsigned int rsvd2; 646 unsigned int assist_state; 647 unsigned int responder_addr; 648 unsigned int requestor_addr; 649 unsigned int path_info; 650 unsigned long long fr[32]; 651 }; 652 653 /* 654 * architected results from PDC_PIM/transfer hpmc on a PA2.0 machine 655 * 656 * Note that PDC_PIM doesn't care whether or not wide mode was enabled 657 * so the results are different on PA1.1 vs. PA2.0 when in narrow mode. 658 * 659 * Note also that there are unarchitected results available, which 660 * are hversion dependent. Do a "ser pim 0 hpmc" after rebooting, since 661 * the firmware is probably the best way of printing hversion dependent 662 * data. 663 */ 664 665 struct pdc_hpmc_pim_20 { /* PDC_PIM */ 666 unsigned long long gr[32]; 667 unsigned long long cr[32]; 668 unsigned long long sr[8]; 669 unsigned long long iasq_back; 670 unsigned long long iaoq_back; 671 unsigned int check_type; 672 unsigned int cpu_state; 673 unsigned int cache_check; 674 unsigned int tlb_check; 675 unsigned int bus_check; 676 unsigned int assists_check; 677 unsigned int assist_state; 678 unsigned int path_info; 679 unsigned long long responder_addr; 680 unsigned long long requestor_addr; 681 unsigned long long fr[32]; 682 }; 683 684 struct pim_cpu_state_cf { 685 union { 686 unsigned int 687 iqv : 1, /* IIA queue Valid */ 688 iqf : 1, /* IIA queue Failure */ 689 ipv : 1, /* IPRs Valid */ 690 grv : 1, /* GRs Valid */ 691 crv : 1, /* CRs Valid */ 692 srv : 1, /* SRs Valid */ 693 trv : 1, /* CR24 through CR31 valid */ 694 pad : 24, /* reserved */ 695 td : 1; /* TOC did not cause any damage to the system state */ 696 unsigned int val; 697 }; 698 }; 699 700 struct pdc_toc_pim_11 { 701 unsigned int gr[32]; 702 unsigned int cr[32]; 703 unsigned int sr[8]; 704 unsigned int iasq_back; 705 unsigned int iaoq_back; 706 unsigned int check_type; 707 struct pim_cpu_state_cf cpu_state; 708 }; 709 710 struct pdc_toc_pim_20 { 711 unsigned long long gr[32]; 712 unsigned long long cr[32]; 713 unsigned long long sr[8]; 714 unsigned long long iasq_back; 715 unsigned long long iaoq_back; 716 unsigned int check_type; 717 struct pim_cpu_state_cf cpu_state; 718 }; 719 720 #endif /* !defined(__ASSEMBLY__) */ 721 722 #endif /* _UAPI_PARISC_PDC_H */ 723