1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2deae26bfSKyle McMartin #ifndef _ASM_PARISC_ROPES_H_ 3deae26bfSKyle McMartin #define _ASM_PARISC_ROPES_H_ 4deae26bfSKyle McMartin 5deae26bfSKyle McMartin #include <asm/parisc-device.h> 6deae26bfSKyle McMartin 7deae26bfSKyle McMartin #ifdef CONFIG_64BIT 8deae26bfSKyle McMartin /* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */ 9deae26bfSKyle McMartin #define ZX1_SUPPORT 10deae26bfSKyle McMartin #endif 11deae26bfSKyle McMartin 12deae26bfSKyle McMartin #ifdef CONFIG_PROC_FS 13deae26bfSKyle McMartin /* depends on proc fs support. But costs CPU performance */ 14deae26bfSKyle McMartin #undef SBA_COLLECT_STATS 15deae26bfSKyle McMartin #endif 16deae26bfSKyle McMartin 17deae26bfSKyle McMartin /* 18deae26bfSKyle McMartin ** The number of pdir entries to "free" before issuing 19deae26bfSKyle McMartin ** a read to PCOM register to flush out PCOM writes. 20deae26bfSKyle McMartin ** Interacts with allocation granularity (ie 4 or 8 entries 21deae26bfSKyle McMartin ** allocated and free'd/purged at a time might make this 22deae26bfSKyle McMartin ** less interesting). 23deae26bfSKyle McMartin */ 24deae26bfSKyle McMartin #define DELAYED_RESOURCE_CNT 16 25deae26bfSKyle McMartin 26deae26bfSKyle McMartin #define MAX_IOC 2 /* per Ike. Pluto/Astro only have 1. */ 27deae26bfSKyle McMartin #define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */ 28deae26bfSKyle McMartin 29deae26bfSKyle McMartin struct ioc { 30deae26bfSKyle McMartin void __iomem *ioc_hpa; /* I/O MMU base address */ 31deae26bfSKyle McMartin char *res_map; /* resource map, bit == pdir entry */ 32deae26bfSKyle McMartin u64 *pdir_base; /* physical base address */ 33deae26bfSKyle McMartin unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */ 34deae26bfSKyle McMartin unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */ 35deae26bfSKyle McMartin #ifdef ZX1_SUPPORT 36deae26bfSKyle McMartin unsigned long iovp_mask; /* help convert IOVA to IOVP */ 37deae26bfSKyle McMartin #endif 38deae26bfSKyle McMartin unsigned long *res_hint; /* next avail IOVP - circular search */ 39deae26bfSKyle McMartin spinlock_t res_lock; 40deae26bfSKyle McMartin unsigned int res_bitshift; /* from the LEFT! */ 41deae26bfSKyle McMartin unsigned int res_size; /* size of resource map in bytes */ 42deae26bfSKyle McMartin #ifdef SBA_HINT_SUPPORT 43deae26bfSKyle McMartin /* FIXME : DMA HINTs not used */ 44deae26bfSKyle McMartin unsigned long hint_mask_pdir; /* bits used for DMA hints */ 45deae26bfSKyle McMartin unsigned int hint_shift_pdir; 46deae26bfSKyle McMartin #endif 47deae26bfSKyle McMartin #if DELAYED_RESOURCE_CNT > 0 48deae26bfSKyle McMartin int saved_cnt; 49deae26bfSKyle McMartin struct sba_dma_pair { 50deae26bfSKyle McMartin dma_addr_t iova; 51deae26bfSKyle McMartin size_t size; 52deae26bfSKyle McMartin } saved[DELAYED_RESOURCE_CNT]; 53deae26bfSKyle McMartin #endif 54deae26bfSKyle McMartin 55deae26bfSKyle McMartin #ifdef SBA_COLLECT_STATS 56deae26bfSKyle McMartin #define SBA_SEARCH_SAMPLE 0x100 57deae26bfSKyle McMartin unsigned long avg_search[SBA_SEARCH_SAMPLE]; 58deae26bfSKyle McMartin unsigned long avg_idx; /* current index into avg_search */ 59deae26bfSKyle McMartin unsigned long used_pages; 60deae26bfSKyle McMartin unsigned long msingle_calls; 61deae26bfSKyle McMartin unsigned long msingle_pages; 62deae26bfSKyle McMartin unsigned long msg_calls; 63deae26bfSKyle McMartin unsigned long msg_pages; 64deae26bfSKyle McMartin unsigned long usingle_calls; 65deae26bfSKyle McMartin unsigned long usingle_pages; 66deae26bfSKyle McMartin unsigned long usg_calls; 67deae26bfSKyle McMartin unsigned long usg_pages; 68deae26bfSKyle McMartin #endif 69deae26bfSKyle McMartin /* STUFF We don't need in performance path */ 70deae26bfSKyle McMartin unsigned int pdir_size; /* in bytes, determined by IOV Space size */ 71deae26bfSKyle McMartin }; 72deae26bfSKyle McMartin 73deae26bfSKyle McMartin struct sba_device { 74deae26bfSKyle McMartin struct sba_device *next; /* list of SBA's in system */ 75deae26bfSKyle McMartin struct parisc_device *dev; /* dev found in bus walk */ 76deae26bfSKyle McMartin const char *name; 77deae26bfSKyle McMartin void __iomem *sba_hpa; /* base address */ 78deae26bfSKyle McMartin spinlock_t sba_lock; 79deae26bfSKyle McMartin unsigned int flags; /* state/functionality enabled */ 80deae26bfSKyle McMartin unsigned int hw_rev; /* HW revision of chip */ 81deae26bfSKyle McMartin 82deae26bfSKyle McMartin struct resource chip_resv; /* MMIO reserved for chip */ 83deae26bfSKyle McMartin struct resource iommu_resv; /* MMIO reserved for iommu */ 84deae26bfSKyle McMartin 85deae26bfSKyle McMartin unsigned int num_ioc; /* number of on-board IOC's */ 86deae26bfSKyle McMartin struct ioc ioc[MAX_IOC]; 87deae26bfSKyle McMartin }; 88deae26bfSKyle McMartin 89*eb3255eeSHelge Deller /* list of SBA's in system, see drivers/parisc/sba_iommu.c */ 90*eb3255eeSHelge Deller extern struct sba_device *sba_list; 91*eb3255eeSHelge Deller 92deae26bfSKyle McMartin #define ASTRO_RUNWAY_PORT 0x582 93deae26bfSKyle McMartin #define IKE_MERCED_PORT 0x803 94deae26bfSKyle McMartin #define REO_MERCED_PORT 0x804 95deae26bfSKyle McMartin #define REOG_MERCED_PORT 0x805 96deae26bfSKyle McMartin #define PLUTO_MCKINLEY_PORT 0x880 97deae26bfSKyle McMartin 98deae26bfSKyle McMartin static inline int IS_ASTRO(struct parisc_device *d) { 99deae26bfSKyle McMartin return d->id.hversion == ASTRO_RUNWAY_PORT; 100deae26bfSKyle McMartin } 101deae26bfSKyle McMartin 102deae26bfSKyle McMartin static inline int IS_IKE(struct parisc_device *d) { 103deae26bfSKyle McMartin return d->id.hversion == IKE_MERCED_PORT; 104deae26bfSKyle McMartin } 105deae26bfSKyle McMartin 106deae26bfSKyle McMartin static inline int IS_PLUTO(struct parisc_device *d) { 107deae26bfSKyle McMartin return d->id.hversion == PLUTO_MCKINLEY_PORT; 108deae26bfSKyle McMartin } 109deae26bfSKyle McMartin 110deae26bfSKyle McMartin #define PLUTO_IOVA_BASE (1UL*1024*1024*1024) /* 1GB */ 111deae26bfSKyle McMartin #define PLUTO_IOVA_SIZE (1UL*1024*1024*1024) /* 1GB */ 112deae26bfSKyle McMartin #define PLUTO_GART_SIZE (PLUTO_IOVA_SIZE / 2) 113deae26bfSKyle McMartin 114deae26bfSKyle McMartin #define SBA_PDIR_VALID_BIT 0x8000000000000000ULL 115deae26bfSKyle McMartin 116deae26bfSKyle McMartin #define SBA_AGPGART_COOKIE 0x0000badbadc0ffeeULL 117deae26bfSKyle McMartin 118deae26bfSKyle McMartin #define SBA_FUNC_ID 0x0000 /* function id */ 119deae26bfSKyle McMartin #define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */ 120deae26bfSKyle McMartin 121deae26bfSKyle McMartin #define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */ 122deae26bfSKyle McMartin 123deae26bfSKyle McMartin #define ASTRO_IOC_OFFSET (32 * SBA_FUNC_SIZE) 124deae26bfSKyle McMartin #define PLUTO_IOC_OFFSET (1 * SBA_FUNC_SIZE) 125deae26bfSKyle McMartin /* Ike's IOC's occupy functions 2 and 3 */ 126deae26bfSKyle McMartin #define IKE_IOC_OFFSET(p) ((p+2) * SBA_FUNC_SIZE) 127deae26bfSKyle McMartin 128deae26bfSKyle McMartin #define IOC_CTRL 0x8 /* IOC_CTRL offset */ 129deae26bfSKyle McMartin #define IOC_CTRL_TC (1 << 0) /* TOC Enable */ 130deae26bfSKyle McMartin #define IOC_CTRL_CE (1 << 1) /* Coalesce Enable */ 131deae26bfSKyle McMartin #define IOC_CTRL_DE (1 << 2) /* Dillon Enable */ 132deae26bfSKyle McMartin #define IOC_CTRL_RM (1 << 8) /* Real Mode */ 133deae26bfSKyle McMartin #define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */ 134deae26bfSKyle McMartin #define IOC_CTRL_D4 (1 << 11) /* Disable 4-byte coalescing */ 135deae26bfSKyle McMartin #define IOC_CTRL_DD (1 << 13) /* Disable distr. LMMIO range coalescing */ 136deae26bfSKyle McMartin 137deae26bfSKyle McMartin /* 138deae26bfSKyle McMartin ** Offsets into MBIB (Function 0 on Ike and hopefully Astro) 139deae26bfSKyle McMartin ** Firmware programs this stuff. Don't touch it. 140deae26bfSKyle McMartin */ 141deae26bfSKyle McMartin #define LMMIO_DIRECT0_BASE 0x300 142deae26bfSKyle McMartin #define LMMIO_DIRECT0_MASK 0x308 143deae26bfSKyle McMartin #define LMMIO_DIRECT0_ROUTE 0x310 144deae26bfSKyle McMartin 145deae26bfSKyle McMartin #define LMMIO_DIST_BASE 0x360 146deae26bfSKyle McMartin #define LMMIO_DIST_MASK 0x368 147deae26bfSKyle McMartin #define LMMIO_DIST_ROUTE 0x370 148deae26bfSKyle McMartin 149deae26bfSKyle McMartin #define IOS_DIST_BASE 0x390 150deae26bfSKyle McMartin #define IOS_DIST_MASK 0x398 151deae26bfSKyle McMartin #define IOS_DIST_ROUTE 0x3A0 152deae26bfSKyle McMartin 153deae26bfSKyle McMartin #define IOS_DIRECT_BASE 0x3C0 154deae26bfSKyle McMartin #define IOS_DIRECT_MASK 0x3C8 155deae26bfSKyle McMartin #define IOS_DIRECT_ROUTE 0x3D0 156deae26bfSKyle McMartin 157deae26bfSKyle McMartin /* 158deae26bfSKyle McMartin ** Offsets into I/O TLB (Function 2 and 3 on Ike) 159deae26bfSKyle McMartin */ 160deae26bfSKyle McMartin #define ROPE0_CTL 0x200 /* "regbus pci0" */ 161deae26bfSKyle McMartin #define ROPE1_CTL 0x208 162deae26bfSKyle McMartin #define ROPE2_CTL 0x210 163deae26bfSKyle McMartin #define ROPE3_CTL 0x218 164deae26bfSKyle McMartin #define ROPE4_CTL 0x220 165deae26bfSKyle McMartin #define ROPE5_CTL 0x228 166deae26bfSKyle McMartin #define ROPE6_CTL 0x230 167deae26bfSKyle McMartin #define ROPE7_CTL 0x238 168deae26bfSKyle McMartin 169deae26bfSKyle McMartin #define IOC_ROPE0_CFG 0x500 /* pluto only */ 170deae26bfSKyle McMartin #define IOC_ROPE_AO 0x10 /* Allow "Relaxed Ordering" */ 171deae26bfSKyle McMartin 172deae26bfSKyle McMartin #define HF_ENABLE 0x40 173deae26bfSKyle McMartin 174deae26bfSKyle McMartin #define IOC_IBASE 0x300 /* IO TLB */ 175deae26bfSKyle McMartin #define IOC_IMASK 0x308 176deae26bfSKyle McMartin #define IOC_PCOM 0x310 177deae26bfSKyle McMartin #define IOC_TCNFG 0x318 178deae26bfSKyle McMartin #define IOC_PDIR_BASE 0x320 179deae26bfSKyle McMartin 180deae26bfSKyle McMartin /* 181deae26bfSKyle McMartin ** IOC supports 4/8/16/64KB page sizes (see TCNFG register) 182deae26bfSKyle McMartin ** It's safer (avoid memory corruption) to keep DMA page mappings 183deae26bfSKyle McMartin ** equivalently sized to VM PAGE_SIZE. 184deae26bfSKyle McMartin ** 185deae26bfSKyle McMartin ** We really can't avoid generating a new mapping for each 186deae26bfSKyle McMartin ** page since the Virtual Coherence Index has to be generated 187deae26bfSKyle McMartin ** and updated for each page. 188deae26bfSKyle McMartin ** 189deae26bfSKyle McMartin ** PAGE_SIZE could be greater than IOVP_SIZE. But not the inverse. 190deae26bfSKyle McMartin */ 191deae26bfSKyle McMartin #define IOVP_SIZE PAGE_SIZE 192deae26bfSKyle McMartin #define IOVP_SHIFT PAGE_SHIFT 193deae26bfSKyle McMartin #define IOVP_MASK PAGE_MASK 194deae26bfSKyle McMartin 195deae26bfSKyle McMartin #define SBA_PERF_CFG 0x708 /* Performance Counter stuff */ 196deae26bfSKyle McMartin #define SBA_PERF_MASK1 0x718 197deae26bfSKyle McMartin #define SBA_PERF_MASK2 0x730 198deae26bfSKyle McMartin 199deae26bfSKyle McMartin /* 200deae26bfSKyle McMartin ** Offsets into PCI Performance Counters (functions 12 and 13) 201deae26bfSKyle McMartin ** Controlled by PERF registers in function 2 & 3 respectively. 202deae26bfSKyle McMartin */ 203deae26bfSKyle McMartin #define SBA_PERF_CNT1 0x200 204deae26bfSKyle McMartin #define SBA_PERF_CNT2 0x208 205deae26bfSKyle McMartin #define SBA_PERF_CNT3 0x210 206deae26bfSKyle McMartin 207deae26bfSKyle McMartin /* 208deae26bfSKyle McMartin ** lba_device: Per instance Elroy data structure 209deae26bfSKyle McMartin */ 210deae26bfSKyle McMartin struct lba_device { 211deae26bfSKyle McMartin struct pci_hba_data hba; 212deae26bfSKyle McMartin 213deae26bfSKyle McMartin spinlock_t lba_lock; 214deae26bfSKyle McMartin void *iosapic_obj; 215deae26bfSKyle McMartin 216deae26bfSKyle McMartin #ifdef CONFIG_64BIT 217deae26bfSKyle McMartin void __iomem *iop_base; /* PA_VIEW - for IO port accessor funcs */ 218deae26bfSKyle McMartin #endif 219deae26bfSKyle McMartin 220deae26bfSKyle McMartin int flags; /* state/functionality enabled */ 221deae26bfSKyle McMartin int hw_rev; /* HW revision of chip */ 222deae26bfSKyle McMartin }; 223deae26bfSKyle McMartin 224deae26bfSKyle McMartin #define ELROY_HVERS 0x782 225deae26bfSKyle McMartin #define MERCURY_HVERS 0x783 226deae26bfSKyle McMartin #define QUICKSILVER_HVERS 0x784 227deae26bfSKyle McMartin 228deae26bfSKyle McMartin static inline int IS_ELROY(struct parisc_device *d) { 229deae26bfSKyle McMartin return (d->id.hversion == ELROY_HVERS); 230deae26bfSKyle McMartin } 231deae26bfSKyle McMartin 232deae26bfSKyle McMartin static inline int IS_MERCURY(struct parisc_device *d) { 233deae26bfSKyle McMartin return (d->id.hversion == MERCURY_HVERS); 234deae26bfSKyle McMartin } 235deae26bfSKyle McMartin 236deae26bfSKyle McMartin static inline int IS_QUICKSILVER(struct parisc_device *d) { 237deae26bfSKyle McMartin return (d->id.hversion == QUICKSILVER_HVERS); 238deae26bfSKyle McMartin } 239deae26bfSKyle McMartin 240deae26bfSKyle McMartin static inline int agp_mode_mercury(void __iomem *hpa) { 241deae26bfSKyle McMartin u64 bus_mode; 242deae26bfSKyle McMartin 243deae26bfSKyle McMartin bus_mode = readl(hpa + 0x0620); 244deae26bfSKyle McMartin if (bus_mode & 1) 245deae26bfSKyle McMartin return 1; 246deae26bfSKyle McMartin 247deae26bfSKyle McMartin return 0; 248deae26bfSKyle McMartin } 249deae26bfSKyle McMartin 250deae26bfSKyle McMartin /* 251deae26bfSKyle McMartin ** I/O SAPIC init function 252deae26bfSKyle McMartin ** Caller knows where an I/O SAPIC is. LBA has an integrated I/O SAPIC. 253deae26bfSKyle McMartin ** Call setup as part of per instance initialization. 254deae26bfSKyle McMartin ** (ie *not* init_module() function unless only one is present.) 255deae26bfSKyle McMartin ** fixup_irq is to initialize PCI IRQ line support and 256deae26bfSKyle McMartin ** virtualize pcidev->irq value. To be called by pci_fixup_bus(). 257deae26bfSKyle McMartin */ 2588f01caf0SHelge Deller extern void *iosapic_register(unsigned long hpa, void __iomem *vaddr); 259deae26bfSKyle McMartin extern int iosapic_fixup_irq(void *obj, struct pci_dev *pcidev); 260deae26bfSKyle McMartin 261deae26bfSKyle McMartin #define LBA_FUNC_ID 0x0000 /* function id */ 262deae26bfSKyle McMartin #define LBA_FCLASS 0x0008 /* function class, bist, header, rev... */ 263deae26bfSKyle McMartin #define LBA_CAPABLE 0x0030 /* capabilities register */ 264deae26bfSKyle McMartin 265deae26bfSKyle McMartin #define LBA_PCI_CFG_ADDR 0x0040 /* poke CFG address here */ 266deae26bfSKyle McMartin #define LBA_PCI_CFG_DATA 0x0048 /* read or write data here */ 267deae26bfSKyle McMartin 268deae26bfSKyle McMartin #define LBA_PMC_MTLT 0x0050 /* Firmware sets this - read only. */ 269deae26bfSKyle McMartin #define LBA_FW_SCRATCH 0x0058 /* Firmware writes the PCI bus number here. */ 270deae26bfSKyle McMartin #define LBA_ERROR_ADDR 0x0070 /* On error, address gets logged here */ 271deae26bfSKyle McMartin 272deae26bfSKyle McMartin #define LBA_ARB_MASK 0x0080 /* bit 0 enable arbitration. PAT/PDC enables */ 273deae26bfSKyle McMartin #define LBA_ARB_PRI 0x0088 /* firmware sets this. */ 274deae26bfSKyle McMartin #define LBA_ARB_MODE 0x0090 /* firmware sets this. */ 275deae26bfSKyle McMartin #define LBA_ARB_MTLT 0x0098 /* firmware sets this. */ 276deae26bfSKyle McMartin 277deae26bfSKyle McMartin #define LBA_MOD_ID 0x0100 /* Module ID. PDC_PAT_CELL reports 4 */ 278deae26bfSKyle McMartin 279deae26bfSKyle McMartin #define LBA_STAT_CTL 0x0108 /* Status & Control */ 280deae26bfSKyle McMartin #define LBA_BUS_RESET 0x01 /* Deassert PCI Bus Reset Signal */ 281deae26bfSKyle McMartin #define CLEAR_ERRLOG 0x10 /* "Clear Error Log" cmd */ 282deae26bfSKyle McMartin #define CLEAR_ERRLOG_ENABLE 0x20 /* "Clear Error Log" Enable */ 283deae26bfSKyle McMartin #define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */ 284deae26bfSKyle McMartin 285deae26bfSKyle McMartin #define LBA_LMMIO_BASE 0x0200 /* < 4GB I/O address range */ 286deae26bfSKyle McMartin #define LBA_LMMIO_MASK 0x0208 287deae26bfSKyle McMartin 288deae26bfSKyle McMartin #define LBA_GMMIO_BASE 0x0210 /* > 4GB I/O address range */ 289deae26bfSKyle McMartin #define LBA_GMMIO_MASK 0x0218 290deae26bfSKyle McMartin 291deae26bfSKyle McMartin #define LBA_WLMMIO_BASE 0x0220 /* All < 4GB ranges under the same *SBA* */ 292deae26bfSKyle McMartin #define LBA_WLMMIO_MASK 0x0228 293deae26bfSKyle McMartin 294deae26bfSKyle McMartin #define LBA_WGMMIO_BASE 0x0230 /* All > 4GB ranges under the same *SBA* */ 295deae26bfSKyle McMartin #define LBA_WGMMIO_MASK 0x0238 296deae26bfSKyle McMartin 297deae26bfSKyle McMartin #define LBA_IOS_BASE 0x0240 /* I/O port space for this LBA */ 298deae26bfSKyle McMartin #define LBA_IOS_MASK 0x0248 299deae26bfSKyle McMartin 300deae26bfSKyle McMartin #define LBA_ELMMIO_BASE 0x0250 /* Extra LMMIO range */ 301deae26bfSKyle McMartin #define LBA_ELMMIO_MASK 0x0258 302deae26bfSKyle McMartin 303deae26bfSKyle McMartin #define LBA_EIOS_BASE 0x0260 /* Extra I/O port space */ 304deae26bfSKyle McMartin #define LBA_EIOS_MASK 0x0268 305deae26bfSKyle McMartin 306deae26bfSKyle McMartin #define LBA_GLOBAL_MASK 0x0270 /* Mercury only: Global Address Mask */ 307deae26bfSKyle McMartin #define LBA_DMA_CTL 0x0278 /* firmware sets this */ 308deae26bfSKyle McMartin 309deae26bfSKyle McMartin #define LBA_IBASE 0x0300 /* SBA DMA support */ 310deae26bfSKyle McMartin #define LBA_IMASK 0x0308 311deae26bfSKyle McMartin 312deae26bfSKyle McMartin /* FIXME: ignore DMA Hint stuff until we can measure performance */ 313deae26bfSKyle McMartin #define LBA_HINT_CFG 0x0310 314deae26bfSKyle McMartin #define LBA_HINT_BASE 0x0380 /* 14 registers at every 8 bytes. */ 315deae26bfSKyle McMartin 316deae26bfSKyle McMartin #define LBA_BUS_MODE 0x0620 317deae26bfSKyle McMartin 318deae26bfSKyle McMartin /* ERROR regs are needed for config cycle kluges */ 319deae26bfSKyle McMartin #define LBA_ERROR_CONFIG 0x0680 320deae26bfSKyle McMartin #define LBA_SMART_MODE 0x20 321deae26bfSKyle McMartin #define LBA_ERROR_STATUS 0x0688 322deae26bfSKyle McMartin #define LBA_ROPE_CTL 0x06A0 323deae26bfSKyle McMartin 324deae26bfSKyle McMartin #define LBA_IOSAPIC_BASE 0x800 /* Offset of IRQ logic */ 325deae26bfSKyle McMartin 326deae26bfSKyle McMartin #endif /*_ASM_PARISC_ROPES_H_*/ 327