1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _PARISC_PGTABLE_H 3 #define _PARISC_PGTABLE_H 4 5 #include <asm/page.h> 6 7 #if CONFIG_PGTABLE_LEVELS == 3 8 #include <asm-generic/pgtable-nopud.h> 9 #elif CONFIG_PGTABLE_LEVELS == 2 10 #include <asm-generic/pgtable-nopmd.h> 11 #endif 12 13 #include <asm/fixmap.h> 14 15 #ifndef __ASSEMBLY__ 16 /* 17 * we simulate an x86-style page table for the linux mm code 18 */ 19 20 #include <linux/bitops.h> 21 #include <linux/spinlock.h> 22 #include <linux/mm_types.h> 23 #include <asm/processor.h> 24 #include <asm/cache.h> 25 26 static inline spinlock_t *pgd_spinlock(pgd_t *); 27 28 /* 29 * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel 30 * memory. For the return value to be meaningful, ADDR must be >= 31 * PAGE_OFFSET. This operation can be relatively expensive (e.g., 32 * require a hash-, or multi-level tree-lookup or something of that 33 * sort) but it guarantees to return TRUE only if accessing the page 34 * at that address does not cause an error. Note that there may be 35 * addresses for which kern_addr_valid() returns FALSE even though an 36 * access would not cause an error (e.g., this is typically true for 37 * memory mapped I/O regions. 38 * 39 * XXX Need to implement this for parisc. 40 */ 41 #define kern_addr_valid(addr) (1) 42 43 /* This is for the serialization of PxTLB broadcasts. At least on the N class 44 * systems, only one PxTLB inter processor broadcast can be active at any one 45 * time on the Merced bus. 46 47 * PTE updates are protected by locks in the PMD. 48 */ 49 extern spinlock_t pa_tlb_flush_lock; 50 extern spinlock_t pa_swapper_pg_lock; 51 #if defined(CONFIG_64BIT) && defined(CONFIG_SMP) 52 extern int pa_serialize_tlb_flushes; 53 #else 54 #define pa_serialize_tlb_flushes (0) 55 #endif 56 57 #define purge_tlb_start(flags) do { \ 58 if (pa_serialize_tlb_flushes) \ 59 spin_lock_irqsave(&pa_tlb_flush_lock, flags); \ 60 else \ 61 local_irq_save(flags); \ 62 } while (0) 63 #define purge_tlb_end(flags) do { \ 64 if (pa_serialize_tlb_flushes) \ 65 spin_unlock_irqrestore(&pa_tlb_flush_lock, flags); \ 66 else \ 67 local_irq_restore(flags); \ 68 } while (0) 69 70 /* Purge data and instruction TLB entries. The TLB purge instructions 71 * are slow on SMP machines since the purge must be broadcast to all CPUs. 72 */ 73 74 static inline void purge_tlb_entries(struct mm_struct *mm, unsigned long addr) 75 { 76 unsigned long flags; 77 78 purge_tlb_start(flags); 79 mtsp(mm->context, 1); 80 pdtlb(addr); 81 pitlb(addr); 82 purge_tlb_end(flags); 83 } 84 85 /* Certain architectures need to do special things when PTEs 86 * within a page table are directly modified. Thus, the following 87 * hook is made available. 88 */ 89 #define set_pte(pteptr, pteval) \ 90 do{ \ 91 *(pteptr) = (pteval); \ 92 } while(0) 93 94 #define set_pte_at(mm, addr, ptep, pteval) \ 95 do { \ 96 pte_t old_pte; \ 97 unsigned long flags; \ 98 spin_lock_irqsave(pgd_spinlock((mm)->pgd), flags);\ 99 old_pte = *ptep; \ 100 set_pte(ptep, pteval); \ 101 purge_tlb_entries(mm, addr); \ 102 spin_unlock_irqrestore(pgd_spinlock((mm)->pgd), flags);\ 103 } while (0) 104 105 #endif /* !__ASSEMBLY__ */ 106 107 #define pte_ERROR(e) \ 108 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 109 #if CONFIG_PGTABLE_LEVELS == 3 110 #define pmd_ERROR(e) \ 111 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, (unsigned long)pmd_val(e)) 112 #endif 113 #define pgd_ERROR(e) \ 114 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, (unsigned long)pgd_val(e)) 115 116 /* This is the size of the initially mapped kernel memory */ 117 #if defined(CONFIG_64BIT) 118 #define KERNEL_INITIAL_ORDER 26 /* 1<<26 = 64MB */ 119 #else 120 #define KERNEL_INITIAL_ORDER 25 /* 1<<25 = 32MB */ 121 #endif 122 #define KERNEL_INITIAL_SIZE (1 << KERNEL_INITIAL_ORDER) 123 124 #if CONFIG_PGTABLE_LEVELS == 3 125 #define PGD_ORDER 1 /* Number of pages per pgd */ 126 #define PMD_ORDER 1 /* Number of pages per pmd */ 127 #define PGD_ALLOC_ORDER (2 + 1) /* first pgd contains pmd */ 128 #else 129 #define PGD_ORDER 1 /* Number of pages per pgd */ 130 #define PGD_ALLOC_ORDER (PGD_ORDER + 1) 131 #endif 132 133 /* Definitions for 3rd level (we use PLD here for Page Lower directory 134 * because PTE_SHIFT is used lower down to mean shift that has to be 135 * done to get usable bits out of the PTE) */ 136 #define PLD_SHIFT PAGE_SHIFT 137 #define PLD_SIZE PAGE_SIZE 138 #define BITS_PER_PTE (PAGE_SHIFT - BITS_PER_PTE_ENTRY) 139 #define PTRS_PER_PTE (1UL << BITS_PER_PTE) 140 141 /* Definitions for 2nd level */ 142 #if CONFIG_PGTABLE_LEVELS == 3 143 #define PMD_SHIFT (PLD_SHIFT + BITS_PER_PTE) 144 #define PMD_SIZE (1UL << PMD_SHIFT) 145 #define PMD_MASK (~(PMD_SIZE-1)) 146 #define BITS_PER_PMD (PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY) 147 #define PTRS_PER_PMD (1UL << BITS_PER_PMD) 148 #else 149 #define BITS_PER_PMD 0 150 #endif 151 152 /* Definitions for 1st level */ 153 #define PGDIR_SHIFT (PLD_SHIFT + BITS_PER_PTE + BITS_PER_PMD) 154 #if (PGDIR_SHIFT + PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY) > BITS_PER_LONG 155 #define BITS_PER_PGD (BITS_PER_LONG - PGDIR_SHIFT) 156 #else 157 #define BITS_PER_PGD (PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY) 158 #endif 159 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 160 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 161 #define PTRS_PER_PGD (1UL << BITS_PER_PGD) 162 #define USER_PTRS_PER_PGD PTRS_PER_PGD 163 164 #ifdef CONFIG_64BIT 165 #define MAX_ADDRBITS (PGDIR_SHIFT + BITS_PER_PGD) 166 #define MAX_ADDRESS (1UL << MAX_ADDRBITS) 167 #define SPACEID_SHIFT (MAX_ADDRBITS - 32) 168 #else 169 #define MAX_ADDRBITS (BITS_PER_LONG) 170 #define MAX_ADDRESS (1UL << MAX_ADDRBITS) 171 #define SPACEID_SHIFT 0 172 #endif 173 174 /* This calculates the number of initial pages we need for the initial 175 * page tables */ 176 #if (KERNEL_INITIAL_ORDER) >= (PMD_SHIFT) 177 # define PT_INITIAL (1 << (KERNEL_INITIAL_ORDER - PMD_SHIFT)) 178 #else 179 # define PT_INITIAL (1) /* all initial PTEs fit into one page */ 180 #endif 181 182 /* 183 * pgd entries used up by user/kernel: 184 */ 185 186 #define FIRST_USER_ADDRESS 0UL 187 188 /* NB: The tlb miss handlers make certain assumptions about the order */ 189 /* of the following bits, so be careful (One example, bits 25-31 */ 190 /* are moved together in one instruction). */ 191 192 #define _PAGE_READ_BIT 31 /* (0x001) read access allowed */ 193 #define _PAGE_WRITE_BIT 30 /* (0x002) write access allowed */ 194 #define _PAGE_EXEC_BIT 29 /* (0x004) execute access allowed */ 195 #define _PAGE_GATEWAY_BIT 28 /* (0x008) privilege promotion allowed */ 196 #define _PAGE_DMB_BIT 27 /* (0x010) Data Memory Break enable (B bit) */ 197 #define _PAGE_DIRTY_BIT 26 /* (0x020) Page Dirty (D bit) */ 198 #define _PAGE_REFTRAP_BIT 25 /* (0x040) Page Ref. Trap enable (T bit) */ 199 #define _PAGE_NO_CACHE_BIT 24 /* (0x080) Uncached Page (U bit) */ 200 #define _PAGE_ACCESSED_BIT 23 /* (0x100) Software: Page Accessed */ 201 #define _PAGE_PRESENT_BIT 22 /* (0x200) Software: translation valid */ 202 #define _PAGE_HPAGE_BIT 21 /* (0x400) Software: Huge Page */ 203 #define _PAGE_USER_BIT 20 /* (0x800) Software: User accessible page */ 204 205 /* N.B. The bits are defined in terms of a 32 bit word above, so the */ 206 /* following macro is ok for both 32 and 64 bit. */ 207 208 #define xlate_pabit(x) (31 - x) 209 210 /* this defines the shift to the usable bits in the PTE it is set so 211 * that the valid bits _PAGE_PRESENT_BIT and _PAGE_USER_BIT are set 212 * to zero */ 213 #define PTE_SHIFT xlate_pabit(_PAGE_USER_BIT) 214 215 /* PFN_PTE_SHIFT defines the shift of a PTE value to access the PFN field */ 216 #define PFN_PTE_SHIFT 12 217 218 #define _PAGE_READ (1 << xlate_pabit(_PAGE_READ_BIT)) 219 #define _PAGE_WRITE (1 << xlate_pabit(_PAGE_WRITE_BIT)) 220 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 221 #define _PAGE_EXEC (1 << xlate_pabit(_PAGE_EXEC_BIT)) 222 #define _PAGE_GATEWAY (1 << xlate_pabit(_PAGE_GATEWAY_BIT)) 223 #define _PAGE_DMB (1 << xlate_pabit(_PAGE_DMB_BIT)) 224 #define _PAGE_DIRTY (1 << xlate_pabit(_PAGE_DIRTY_BIT)) 225 #define _PAGE_REFTRAP (1 << xlate_pabit(_PAGE_REFTRAP_BIT)) 226 #define _PAGE_NO_CACHE (1 << xlate_pabit(_PAGE_NO_CACHE_BIT)) 227 #define _PAGE_ACCESSED (1 << xlate_pabit(_PAGE_ACCESSED_BIT)) 228 #define _PAGE_PRESENT (1 << xlate_pabit(_PAGE_PRESENT_BIT)) 229 #define _PAGE_HUGE (1 << xlate_pabit(_PAGE_HPAGE_BIT)) 230 #define _PAGE_USER (1 << xlate_pabit(_PAGE_USER_BIT)) 231 232 #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED) 233 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) 234 #define _PAGE_KERNEL_RO (_PAGE_PRESENT | _PAGE_READ | _PAGE_DIRTY | _PAGE_ACCESSED) 235 #define _PAGE_KERNEL_EXEC (_PAGE_KERNEL_RO | _PAGE_EXEC) 236 #define _PAGE_KERNEL_RWX (_PAGE_KERNEL_EXEC | _PAGE_WRITE) 237 #define _PAGE_KERNEL (_PAGE_KERNEL_RO | _PAGE_WRITE) 238 239 /* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds 240 * are page-aligned, we don't care about the PAGE_OFFSET bits, except 241 * for a few meta-information bits, so we shift the address to be 242 * able to effectively address 40/42/44-bits of physical address space 243 * depending on 4k/16k/64k PAGE_SIZE */ 244 #define _PxD_PRESENT_BIT 31 245 #define _PxD_ATTACHED_BIT 30 246 #define _PxD_VALID_BIT 29 247 248 #define PxD_FLAG_PRESENT (1 << xlate_pabit(_PxD_PRESENT_BIT)) 249 #define PxD_FLAG_ATTACHED (1 << xlate_pabit(_PxD_ATTACHED_BIT)) 250 #define PxD_FLAG_VALID (1 << xlate_pabit(_PxD_VALID_BIT)) 251 #define PxD_FLAG_MASK (0xf) 252 #define PxD_FLAG_SHIFT (4) 253 #define PxD_VALUE_SHIFT (PFN_PTE_SHIFT-PxD_FLAG_SHIFT) 254 255 #ifndef __ASSEMBLY__ 256 257 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_USER) 258 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE) 259 /* Others seem to make this executable, I don't know if that's correct 260 or not. The stack is mapped this way though so this is necessary 261 in the short term - dhd@linuxcare.com, 2000-08-08 */ 262 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ) 263 #define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITE) 264 #define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_EXEC) 265 #define PAGE_COPY PAGE_EXECREAD 266 #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) 267 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 268 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL_EXEC) 269 #define PAGE_KERNEL_RWX __pgprot(_PAGE_KERNEL_RWX) 270 #define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL_RO) 271 #define PAGE_KERNEL_UNC __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE) 272 #define PAGE_GATEWAY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_GATEWAY| _PAGE_READ) 273 274 275 /* 276 * We could have an execute only page using "gateway - promote to priv 277 * level 3", but that is kind of silly. So, the way things are defined 278 * now, we must always have read permission for pages with execute 279 * permission. For the fun of it we'll go ahead and support write only 280 * pages. 281 */ 282 283 /*xwr*/ 284 #define __P000 PAGE_NONE 285 #define __P001 PAGE_READONLY 286 #define __P010 __P000 /* copy on write */ 287 #define __P011 __P001 /* copy on write */ 288 #define __P100 PAGE_EXECREAD 289 #define __P101 PAGE_EXECREAD 290 #define __P110 __P100 /* copy on write */ 291 #define __P111 __P101 /* copy on write */ 292 293 #define __S000 PAGE_NONE 294 #define __S001 PAGE_READONLY 295 #define __S010 PAGE_WRITEONLY 296 #define __S011 PAGE_SHARED 297 #define __S100 PAGE_EXECREAD 298 #define __S101 PAGE_EXECREAD 299 #define __S110 PAGE_RWX 300 #define __S111 PAGE_RWX 301 302 303 extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */ 304 305 /* initial page tables for 0-8MB for kernel */ 306 307 extern pte_t pg0[]; 308 309 /* zero page used for uninitialized stuff */ 310 311 extern unsigned long *empty_zero_page; 312 313 /* 314 * ZERO_PAGE is a global shared page that is always zero: used 315 * for zero-mapped memory areas etc.. 316 */ 317 318 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 319 320 #define pte_none(x) (pte_val(x) == 0) 321 #define pte_present(x) (pte_val(x) & _PAGE_PRESENT) 322 #define pte_clear(mm, addr, xp) set_pte_at(mm, addr, xp, __pte(0)) 323 324 #define pmd_flag(x) (pmd_val(x) & PxD_FLAG_MASK) 325 #define pmd_address(x) ((unsigned long)(pmd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT) 326 #define pud_flag(x) (pud_val(x) & PxD_FLAG_MASK) 327 #define pud_address(x) ((unsigned long)(pud_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT) 328 #define pgd_flag(x) (pgd_val(x) & PxD_FLAG_MASK) 329 #define pgd_address(x) ((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT) 330 331 #if CONFIG_PGTABLE_LEVELS == 3 332 /* The first entry of the permanent pmd is not there if it contains 333 * the gateway marker */ 334 #define pmd_none(x) (!pmd_val(x) || pmd_flag(x) == PxD_FLAG_ATTACHED) 335 #else 336 #define pmd_none(x) (!pmd_val(x)) 337 #endif 338 #define pmd_bad(x) (!(pmd_flag(x) & PxD_FLAG_VALID)) 339 #define pmd_present(x) (pmd_flag(x) & PxD_FLAG_PRESENT) 340 static inline void pmd_clear(pmd_t *pmd) { 341 #if CONFIG_PGTABLE_LEVELS == 3 342 if (pmd_flag(*pmd) & PxD_FLAG_ATTACHED) 343 /* This is the entry pointing to the permanent pmd 344 * attached to the pgd; cannot clear it */ 345 set_pmd(pmd, __pmd(PxD_FLAG_ATTACHED)); 346 else 347 #endif 348 set_pmd(pmd, __pmd(0)); 349 } 350 351 352 353 #if CONFIG_PGTABLE_LEVELS == 3 354 #define pud_page_vaddr(pud) ((unsigned long) __va(pud_address(pud))) 355 #define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud)) 356 357 /* For 64 bit we have three level tables */ 358 359 #define pud_none(x) (!pud_val(x)) 360 #define pud_bad(x) (!(pud_flag(x) & PxD_FLAG_VALID)) 361 #define pud_present(x) (pud_flag(x) & PxD_FLAG_PRESENT) 362 static inline void pud_clear(pud_t *pud) { 363 #if CONFIG_PGTABLE_LEVELS == 3 364 if(pud_flag(*pud) & PxD_FLAG_ATTACHED) 365 /* This is the permanent pmd attached to the pud; cannot 366 * free it */ 367 return; 368 #endif 369 set_pud(pud, __pud(0)); 370 } 371 #endif 372 373 /* 374 * The following only work if pte_present() is true. 375 * Undefined behaviour if not.. 376 */ 377 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } 378 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } 379 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } 380 static inline int pte_special(pte_t pte) { return 0; } 381 382 static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; } 383 static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } 384 static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_WRITE; return pte; } 385 static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; } 386 static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; } 387 static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return pte; } 388 static inline pte_t pte_mkspecial(pte_t pte) { return pte; } 389 390 /* 391 * Huge pte definitions. 392 */ 393 #ifdef CONFIG_HUGETLB_PAGE 394 #define pte_huge(pte) (pte_val(pte) & _PAGE_HUGE) 395 #define pte_mkhuge(pte) (__pte(pte_val(pte) | \ 396 (parisc_requires_coherency() ? 0 : _PAGE_HUGE))) 397 #else 398 #define pte_huge(pte) (0) 399 #define pte_mkhuge(pte) (pte) 400 #endif 401 402 403 /* 404 * Conversion functions: convert a page and protection to a page entry, 405 * and a page entry and page directory to the page they refer to. 406 */ 407 #define __mk_pte(addr,pgprot) \ 408 ({ \ 409 pte_t __pte; \ 410 \ 411 pte_val(__pte) = ((((addr)>>PAGE_SHIFT)<<PFN_PTE_SHIFT) + pgprot_val(pgprot)); \ 412 \ 413 __pte; \ 414 }) 415 416 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 417 418 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 419 { 420 pte_t pte; 421 pte_val(pte) = (pfn << PFN_PTE_SHIFT) | pgprot_val(pgprot); 422 return pte; 423 } 424 425 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 426 { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; } 427 428 /* Permanent address of a page. On parisc we don't have highmem. */ 429 430 #define pte_pfn(x) (pte_val(x) >> PFN_PTE_SHIFT) 431 432 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 433 434 #define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_address(pmd))) 435 436 #define __pmd_page(pmd) ((unsigned long) __va(pmd_address(pmd))) 437 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd)) 438 439 #define pgd_index(address) ((address) >> PGDIR_SHIFT) 440 441 /* to find an entry in a page-table-directory */ 442 #define pgd_offset(mm, address) \ 443 ((mm)->pgd + ((address) >> PGDIR_SHIFT)) 444 445 /* to find an entry in a kernel page-table-directory */ 446 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 447 448 /* Find an entry in the second-level page table.. */ 449 450 #if CONFIG_PGTABLE_LEVELS == 3 451 #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) 452 #define pmd_offset(dir,address) \ 453 ((pmd_t *) pud_page_vaddr(*(dir)) + pmd_index(address)) 454 #else 455 #define pmd_offset(dir,addr) ((pmd_t *) dir) 456 #endif 457 458 /* Find an entry in the third-level page table.. */ 459 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) 460 #define pte_offset_kernel(pmd, address) \ 461 ((pte_t *) pmd_page_vaddr(*(pmd)) + pte_index(address)) 462 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) 463 #define pte_unmap(pte) do { } while (0) 464 465 #define pte_unmap(pte) do { } while (0) 466 #define pte_unmap_nested(pte) do { } while (0) 467 468 extern void paging_init (void); 469 470 /* Used for deferring calls to flush_dcache_page() */ 471 472 #define PG_dcache_dirty PG_arch_1 473 474 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *); 475 476 /* Encode and de-code a swap entry */ 477 478 #define __swp_type(x) ((x).val & 0x1f) 479 #define __swp_offset(x) ( (((x).val >> 6) & 0x7) | \ 480 (((x).val >> 8) & ~0x7) ) 481 #define __swp_entry(type, offset) ((swp_entry_t) { (type) | \ 482 ((offset & 0x7) << 6) | \ 483 ((offset & ~0x7) << 8) }) 484 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 485 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 486 487 488 static inline spinlock_t *pgd_spinlock(pgd_t *pgd) 489 { 490 if (unlikely(pgd == swapper_pg_dir)) 491 return &pa_swapper_pg_lock; 492 return (spinlock_t *)((char *)pgd + (PAGE_SIZE << (PGD_ALLOC_ORDER - 1))); 493 } 494 495 496 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep) 497 { 498 pte_t pte; 499 unsigned long flags; 500 501 if (!pte_young(*ptep)) 502 return 0; 503 504 spin_lock_irqsave(pgd_spinlock(vma->vm_mm->pgd), flags); 505 pte = *ptep; 506 if (!pte_young(pte)) { 507 spin_unlock_irqrestore(pgd_spinlock(vma->vm_mm->pgd), flags); 508 return 0; 509 } 510 set_pte(ptep, pte_mkold(pte)); 511 purge_tlb_entries(vma->vm_mm, addr); 512 spin_unlock_irqrestore(pgd_spinlock(vma->vm_mm->pgd), flags); 513 return 1; 514 } 515 516 struct mm_struct; 517 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 518 { 519 pte_t old_pte; 520 unsigned long flags; 521 522 spin_lock_irqsave(pgd_spinlock(mm->pgd), flags); 523 old_pte = *ptep; 524 set_pte(ptep, __pte(0)); 525 purge_tlb_entries(mm, addr); 526 spin_unlock_irqrestore(pgd_spinlock(mm->pgd), flags); 527 528 return old_pte; 529 } 530 531 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 532 { 533 unsigned long flags; 534 spin_lock_irqsave(pgd_spinlock(mm->pgd), flags); 535 set_pte(ptep, pte_wrprotect(*ptep)); 536 purge_tlb_entries(mm, addr); 537 spin_unlock_irqrestore(pgd_spinlock(mm->pgd), flags); 538 } 539 540 #define pte_same(A,B) (pte_val(A) == pte_val(B)) 541 542 struct seq_file; 543 extern void arch_report_meminfo(struct seq_file *m); 544 545 #endif /* !__ASSEMBLY__ */ 546 547 548 /* TLB page size encoding - see table 3-1 in parisc20.pdf */ 549 #define _PAGE_SIZE_ENCODING_4K 0 550 #define _PAGE_SIZE_ENCODING_16K 1 551 #define _PAGE_SIZE_ENCODING_64K 2 552 #define _PAGE_SIZE_ENCODING_256K 3 553 #define _PAGE_SIZE_ENCODING_1M 4 554 #define _PAGE_SIZE_ENCODING_4M 5 555 #define _PAGE_SIZE_ENCODING_16M 6 556 #define _PAGE_SIZE_ENCODING_64M 7 557 558 #if defined(CONFIG_PARISC_PAGE_SIZE_4KB) 559 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_4K 560 #elif defined(CONFIG_PARISC_PAGE_SIZE_16KB) 561 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_16K 562 #elif defined(CONFIG_PARISC_PAGE_SIZE_64KB) 563 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_64K 564 #endif 565 566 567 #define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE) 568 569 /* We provide our own get_unmapped_area to provide cache coherency */ 570 571 #define HAVE_ARCH_UNMAPPED_AREA 572 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 573 574 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 575 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 576 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 577 #define __HAVE_ARCH_PTE_SAME 578 #include <asm-generic/pgtable.h> 579 580 #endif /* _PARISC_PGTABLE_H */ 581