1 #ifndef _PARISC_PGTABLE_H 2 #define _PARISC_PGTABLE_H 3 4 #include <asm-generic/4level-fixup.h> 5 6 #include <asm/fixmap.h> 7 8 #ifndef __ASSEMBLY__ 9 /* 10 * we simulate an x86-style page table for the linux mm code 11 */ 12 13 #include <linux/bitops.h> 14 #include <linux/spinlock.h> 15 #include <linux/mm_types.h> 16 #include <asm/processor.h> 17 #include <asm/cache.h> 18 19 extern spinlock_t pa_tlb_lock; 20 21 /* 22 * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel 23 * memory. For the return value to be meaningful, ADDR must be >= 24 * PAGE_OFFSET. This operation can be relatively expensive (e.g., 25 * require a hash-, or multi-level tree-lookup or something of that 26 * sort) but it guarantees to return TRUE only if accessing the page 27 * at that address does not cause an error. Note that there may be 28 * addresses for which kern_addr_valid() returns FALSE even though an 29 * access would not cause an error (e.g., this is typically true for 30 * memory mapped I/O regions. 31 * 32 * XXX Need to implement this for parisc. 33 */ 34 #define kern_addr_valid(addr) (1) 35 36 /* Purge data and instruction TLB entries. Must be called holding 37 * the pa_tlb_lock. The TLB purge instructions are slow on SMP 38 * machines since the purge must be broadcast to all CPUs. 39 */ 40 41 static inline void purge_tlb_entries(struct mm_struct *mm, unsigned long addr) 42 { 43 mtsp(mm->context, 1); 44 pdtlb(addr); 45 if (unlikely(split_tlb)) 46 pitlb(addr); 47 } 48 49 /* Certain architectures need to do special things when PTEs 50 * within a page table are directly modified. Thus, the following 51 * hook is made available. 52 */ 53 #define set_pte(pteptr, pteval) \ 54 do{ \ 55 *(pteptr) = (pteval); \ 56 } while(0) 57 58 #define pte_inserted(x) \ 59 ((pte_val(x) & (_PAGE_PRESENT|_PAGE_ACCESSED)) \ 60 == (_PAGE_PRESENT|_PAGE_ACCESSED)) 61 62 #define set_pte_at(mm, addr, ptep, pteval) \ 63 do { \ 64 pte_t old_pte; \ 65 unsigned long flags; \ 66 spin_lock_irqsave(&pa_tlb_lock, flags); \ 67 old_pte = *ptep; \ 68 if (pte_inserted(old_pte)) \ 69 purge_tlb_entries(mm, addr); \ 70 set_pte(ptep, pteval); \ 71 spin_unlock_irqrestore(&pa_tlb_lock, flags); \ 72 } while (0) 73 74 #endif /* !__ASSEMBLY__ */ 75 76 #include <asm/page.h> 77 78 #define pte_ERROR(e) \ 79 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 80 #define pmd_ERROR(e) \ 81 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, (unsigned long)pmd_val(e)) 82 #define pgd_ERROR(e) \ 83 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, (unsigned long)pgd_val(e)) 84 85 /* This is the size of the initially mapped kernel memory */ 86 #if defined(CONFIG_64BIT) 87 #define KERNEL_INITIAL_ORDER 26 /* 1<<26 = 64MB */ 88 #else 89 #define KERNEL_INITIAL_ORDER 25 /* 1<<25 = 32MB */ 90 #endif 91 #define KERNEL_INITIAL_SIZE (1 << KERNEL_INITIAL_ORDER) 92 93 #if CONFIG_PGTABLE_LEVELS == 3 94 #define PGD_ORDER 1 /* Number of pages per pgd */ 95 #define PMD_ORDER 1 /* Number of pages per pmd */ 96 #define PGD_ALLOC_ORDER 2 /* first pgd contains pmd */ 97 #else 98 #define PGD_ORDER 1 /* Number of pages per pgd */ 99 #define PGD_ALLOC_ORDER PGD_ORDER 100 #endif 101 102 /* Definitions for 3rd level (we use PLD here for Page Lower directory 103 * because PTE_SHIFT is used lower down to mean shift that has to be 104 * done to get usable bits out of the PTE) */ 105 #define PLD_SHIFT PAGE_SHIFT 106 #define PLD_SIZE PAGE_SIZE 107 #define BITS_PER_PTE (PAGE_SHIFT - BITS_PER_PTE_ENTRY) 108 #define PTRS_PER_PTE (1UL << BITS_PER_PTE) 109 110 /* Definitions for 2nd level */ 111 #define pgtable_cache_init() do { } while (0) 112 113 #define PMD_SHIFT (PLD_SHIFT + BITS_PER_PTE) 114 #define PMD_SIZE (1UL << PMD_SHIFT) 115 #define PMD_MASK (~(PMD_SIZE-1)) 116 #if CONFIG_PGTABLE_LEVELS == 3 117 #define BITS_PER_PMD (PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY) 118 #else 119 #define __PAGETABLE_PMD_FOLDED 120 #define BITS_PER_PMD 0 121 #endif 122 #define PTRS_PER_PMD (1UL << BITS_PER_PMD) 123 124 /* Definitions for 1st level */ 125 #define PGDIR_SHIFT (PMD_SHIFT + BITS_PER_PMD) 126 #if (PGDIR_SHIFT + PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY) > BITS_PER_LONG 127 #define BITS_PER_PGD (BITS_PER_LONG - PGDIR_SHIFT) 128 #else 129 #define BITS_PER_PGD (PAGE_SHIFT + PGD_ORDER - BITS_PER_PGD_ENTRY) 130 #endif 131 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 132 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 133 #define PTRS_PER_PGD (1UL << BITS_PER_PGD) 134 #define USER_PTRS_PER_PGD PTRS_PER_PGD 135 136 #ifdef CONFIG_64BIT 137 #define MAX_ADDRBITS (PGDIR_SHIFT + BITS_PER_PGD) 138 #define MAX_ADDRESS (1UL << MAX_ADDRBITS) 139 #define SPACEID_SHIFT (MAX_ADDRBITS - 32) 140 #else 141 #define MAX_ADDRBITS (BITS_PER_LONG) 142 #define MAX_ADDRESS (1UL << MAX_ADDRBITS) 143 #define SPACEID_SHIFT 0 144 #endif 145 146 /* This calculates the number of initial pages we need for the initial 147 * page tables */ 148 #if (KERNEL_INITIAL_ORDER) >= (PMD_SHIFT) 149 # define PT_INITIAL (1 << (KERNEL_INITIAL_ORDER - PMD_SHIFT)) 150 #else 151 # define PT_INITIAL (1) /* all initial PTEs fit into one page */ 152 #endif 153 154 /* 155 * pgd entries used up by user/kernel: 156 */ 157 158 #define FIRST_USER_ADDRESS 0UL 159 160 /* NB: The tlb miss handlers make certain assumptions about the order */ 161 /* of the following bits, so be careful (One example, bits 25-31 */ 162 /* are moved together in one instruction). */ 163 164 #define _PAGE_READ_BIT 31 /* (0x001) read access allowed */ 165 #define _PAGE_WRITE_BIT 30 /* (0x002) write access allowed */ 166 #define _PAGE_EXEC_BIT 29 /* (0x004) execute access allowed */ 167 #define _PAGE_GATEWAY_BIT 28 /* (0x008) privilege promotion allowed */ 168 #define _PAGE_DMB_BIT 27 /* (0x010) Data Memory Break enable (B bit) */ 169 #define _PAGE_DIRTY_BIT 26 /* (0x020) Page Dirty (D bit) */ 170 #define _PAGE_REFTRAP_BIT 25 /* (0x040) Page Ref. Trap enable (T bit) */ 171 #define _PAGE_NO_CACHE_BIT 24 /* (0x080) Uncached Page (U bit) */ 172 #define _PAGE_ACCESSED_BIT 23 /* (0x100) Software: Page Accessed */ 173 #define _PAGE_PRESENT_BIT 22 /* (0x200) Software: translation valid */ 174 #define _PAGE_HPAGE_BIT 21 /* (0x400) Software: Huge Page */ 175 #define _PAGE_USER_BIT 20 /* (0x800) Software: User accessible page */ 176 177 /* N.B. The bits are defined in terms of a 32 bit word above, so the */ 178 /* following macro is ok for both 32 and 64 bit. */ 179 180 #define xlate_pabit(x) (31 - x) 181 182 /* this defines the shift to the usable bits in the PTE it is set so 183 * that the valid bits _PAGE_PRESENT_BIT and _PAGE_USER_BIT are set 184 * to zero */ 185 #define PTE_SHIFT xlate_pabit(_PAGE_USER_BIT) 186 187 /* PFN_PTE_SHIFT defines the shift of a PTE value to access the PFN field */ 188 #define PFN_PTE_SHIFT 12 189 190 #define _PAGE_READ (1 << xlate_pabit(_PAGE_READ_BIT)) 191 #define _PAGE_WRITE (1 << xlate_pabit(_PAGE_WRITE_BIT)) 192 #define _PAGE_RW (_PAGE_READ | _PAGE_WRITE) 193 #define _PAGE_EXEC (1 << xlate_pabit(_PAGE_EXEC_BIT)) 194 #define _PAGE_GATEWAY (1 << xlate_pabit(_PAGE_GATEWAY_BIT)) 195 #define _PAGE_DMB (1 << xlate_pabit(_PAGE_DMB_BIT)) 196 #define _PAGE_DIRTY (1 << xlate_pabit(_PAGE_DIRTY_BIT)) 197 #define _PAGE_REFTRAP (1 << xlate_pabit(_PAGE_REFTRAP_BIT)) 198 #define _PAGE_NO_CACHE (1 << xlate_pabit(_PAGE_NO_CACHE_BIT)) 199 #define _PAGE_ACCESSED (1 << xlate_pabit(_PAGE_ACCESSED_BIT)) 200 #define _PAGE_PRESENT (1 << xlate_pabit(_PAGE_PRESENT_BIT)) 201 #define _PAGE_HUGE (1 << xlate_pabit(_PAGE_HPAGE_BIT)) 202 #define _PAGE_USER (1 << xlate_pabit(_PAGE_USER_BIT)) 203 204 #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED) 205 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) 206 #define _PAGE_KERNEL_RO (_PAGE_PRESENT | _PAGE_READ | _PAGE_DIRTY | _PAGE_ACCESSED) 207 #define _PAGE_KERNEL_EXEC (_PAGE_KERNEL_RO | _PAGE_EXEC) 208 #define _PAGE_KERNEL_RWX (_PAGE_KERNEL_EXEC | _PAGE_WRITE) 209 #define _PAGE_KERNEL (_PAGE_KERNEL_RO | _PAGE_WRITE) 210 211 /* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds 212 * are page-aligned, we don't care about the PAGE_OFFSET bits, except 213 * for a few meta-information bits, so we shift the address to be 214 * able to effectively address 40/42/44-bits of physical address space 215 * depending on 4k/16k/64k PAGE_SIZE */ 216 #define _PxD_PRESENT_BIT 31 217 #define _PxD_ATTACHED_BIT 30 218 #define _PxD_VALID_BIT 29 219 220 #define PxD_FLAG_PRESENT (1 << xlate_pabit(_PxD_PRESENT_BIT)) 221 #define PxD_FLAG_ATTACHED (1 << xlate_pabit(_PxD_ATTACHED_BIT)) 222 #define PxD_FLAG_VALID (1 << xlate_pabit(_PxD_VALID_BIT)) 223 #define PxD_FLAG_MASK (0xf) 224 #define PxD_FLAG_SHIFT (4) 225 #define PxD_VALUE_SHIFT (PFN_PTE_SHIFT-PxD_FLAG_SHIFT) 226 227 #ifndef __ASSEMBLY__ 228 229 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED) 230 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_ACCESSED) 231 /* Others seem to make this executable, I don't know if that's correct 232 or not. The stack is mapped this way though so this is necessary 233 in the short term - dhd@linuxcare.com, 2000-08-08 */ 234 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_ACCESSED) 235 #define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITE | _PAGE_ACCESSED) 236 #define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_EXEC |_PAGE_ACCESSED) 237 #define PAGE_COPY PAGE_EXECREAD 238 #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC |_PAGE_ACCESSED) 239 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL) 240 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL_EXEC) 241 #define PAGE_KERNEL_RWX __pgprot(_PAGE_KERNEL_RWX) 242 #define PAGE_KERNEL_RO __pgprot(_PAGE_KERNEL_RO) 243 #define PAGE_KERNEL_UNC __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE) 244 #define PAGE_GATEWAY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_GATEWAY| _PAGE_READ) 245 246 247 /* 248 * We could have an execute only page using "gateway - promote to priv 249 * level 3", but that is kind of silly. So, the way things are defined 250 * now, we must always have read permission for pages with execute 251 * permission. For the fun of it we'll go ahead and support write only 252 * pages. 253 */ 254 255 /*xwr*/ 256 #define __P000 PAGE_NONE 257 #define __P001 PAGE_READONLY 258 #define __P010 __P000 /* copy on write */ 259 #define __P011 __P001 /* copy on write */ 260 #define __P100 PAGE_EXECREAD 261 #define __P101 PAGE_EXECREAD 262 #define __P110 __P100 /* copy on write */ 263 #define __P111 __P101 /* copy on write */ 264 265 #define __S000 PAGE_NONE 266 #define __S001 PAGE_READONLY 267 #define __S010 PAGE_WRITEONLY 268 #define __S011 PAGE_SHARED 269 #define __S100 PAGE_EXECREAD 270 #define __S101 PAGE_EXECREAD 271 #define __S110 PAGE_RWX 272 #define __S111 PAGE_RWX 273 274 275 extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */ 276 277 /* initial page tables for 0-8MB for kernel */ 278 279 extern pte_t pg0[]; 280 281 /* zero page used for uninitialized stuff */ 282 283 extern unsigned long *empty_zero_page; 284 285 /* 286 * ZERO_PAGE is a global shared page that is always zero: used 287 * for zero-mapped memory areas etc.. 288 */ 289 290 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 291 292 #define pte_none(x) (pte_val(x) == 0) 293 #define pte_present(x) (pte_val(x) & _PAGE_PRESENT) 294 #define pte_clear(mm, addr, xp) set_pte_at(mm, addr, xp, __pte(0)) 295 296 #define pmd_flag(x) (pmd_val(x) & PxD_FLAG_MASK) 297 #define pmd_address(x) ((unsigned long)(pmd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT) 298 #define pgd_flag(x) (pgd_val(x) & PxD_FLAG_MASK) 299 #define pgd_address(x) ((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT) 300 301 #if CONFIG_PGTABLE_LEVELS == 3 302 /* The first entry of the permanent pmd is not there if it contains 303 * the gateway marker */ 304 #define pmd_none(x) (!pmd_val(x) || pmd_flag(x) == PxD_FLAG_ATTACHED) 305 #else 306 #define pmd_none(x) (!pmd_val(x)) 307 #endif 308 #define pmd_bad(x) (!(pmd_flag(x) & PxD_FLAG_VALID)) 309 #define pmd_present(x) (pmd_flag(x) & PxD_FLAG_PRESENT) 310 static inline void pmd_clear(pmd_t *pmd) { 311 #if CONFIG_PGTABLE_LEVELS == 3 312 if (pmd_flag(*pmd) & PxD_FLAG_ATTACHED) 313 /* This is the entry pointing to the permanent pmd 314 * attached to the pgd; cannot clear it */ 315 __pmd_val_set(*pmd, PxD_FLAG_ATTACHED); 316 else 317 #endif 318 __pmd_val_set(*pmd, 0); 319 } 320 321 322 323 #if CONFIG_PGTABLE_LEVELS == 3 324 #define pgd_page_vaddr(pgd) ((unsigned long) __va(pgd_address(pgd))) 325 #define pgd_page(pgd) virt_to_page((void *)pgd_page_vaddr(pgd)) 326 327 /* For 64 bit we have three level tables */ 328 329 #define pgd_none(x) (!pgd_val(x)) 330 #define pgd_bad(x) (!(pgd_flag(x) & PxD_FLAG_VALID)) 331 #define pgd_present(x) (pgd_flag(x) & PxD_FLAG_PRESENT) 332 static inline void pgd_clear(pgd_t *pgd) { 333 #if CONFIG_PGTABLE_LEVELS == 3 334 if(pgd_flag(*pgd) & PxD_FLAG_ATTACHED) 335 /* This is the permanent pmd attached to the pgd; cannot 336 * free it */ 337 return; 338 #endif 339 __pgd_val_set(*pgd, 0); 340 } 341 #else 342 /* 343 * The "pgd_xxx()" functions here are trivial for a folded two-level 344 * setup: the pgd is never bad, and a pmd always exists (as it's folded 345 * into the pgd entry) 346 */ 347 static inline int pgd_none(pgd_t pgd) { return 0; } 348 static inline int pgd_bad(pgd_t pgd) { return 0; } 349 static inline int pgd_present(pgd_t pgd) { return 1; } 350 static inline void pgd_clear(pgd_t * pgdp) { } 351 #endif 352 353 /* 354 * The following only work if pte_present() is true. 355 * Undefined behaviour if not.. 356 */ 357 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } 358 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } 359 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } 360 static inline int pte_special(pte_t pte) { return 0; } 361 362 static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; } 363 static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } 364 static inline pte_t pte_wrprotect(pte_t pte) { pte_val(pte) &= ~_PAGE_WRITE; return pte; } 365 static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; } 366 static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; } 367 static inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return pte; } 368 static inline pte_t pte_mkspecial(pte_t pte) { return pte; } 369 370 /* 371 * Huge pte definitions. 372 */ 373 #ifdef CONFIG_HUGETLB_PAGE 374 #define pte_huge(pte) (pte_val(pte) & _PAGE_HUGE) 375 #define pte_mkhuge(pte) (__pte(pte_val(pte) | \ 376 (parisc_requires_coherency() ? 0 : _PAGE_HUGE))) 377 #else 378 #define pte_huge(pte) (0) 379 #define pte_mkhuge(pte) (pte) 380 #endif 381 382 383 /* 384 * Conversion functions: convert a page and protection to a page entry, 385 * and a page entry and page directory to the page they refer to. 386 */ 387 #define __mk_pte(addr,pgprot) \ 388 ({ \ 389 pte_t __pte; \ 390 \ 391 pte_val(__pte) = ((((addr)>>PAGE_SHIFT)<<PFN_PTE_SHIFT) + pgprot_val(pgprot)); \ 392 \ 393 __pte; \ 394 }) 395 396 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 397 398 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) 399 { 400 pte_t pte; 401 pte_val(pte) = (pfn << PFN_PTE_SHIFT) | pgprot_val(pgprot); 402 return pte; 403 } 404 405 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 406 { pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; } 407 408 /* Permanent address of a page. On parisc we don't have highmem. */ 409 410 #define pte_pfn(x) (pte_val(x) >> PFN_PTE_SHIFT) 411 412 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 413 414 #define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_address(pmd))) 415 416 #define __pmd_page(pmd) ((unsigned long) __va(pmd_address(pmd))) 417 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd)) 418 419 #define pgd_index(address) ((address) >> PGDIR_SHIFT) 420 421 /* to find an entry in a page-table-directory */ 422 #define pgd_offset(mm, address) \ 423 ((mm)->pgd + ((address) >> PGDIR_SHIFT)) 424 425 /* to find an entry in a kernel page-table-directory */ 426 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 427 428 /* Find an entry in the second-level page table.. */ 429 430 #if CONFIG_PGTABLE_LEVELS == 3 431 #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) 432 #define pmd_offset(dir,address) \ 433 ((pmd_t *) pgd_page_vaddr(*(dir)) + pmd_index(address)) 434 #else 435 #define pmd_offset(dir,addr) ((pmd_t *) dir) 436 #endif 437 438 /* Find an entry in the third-level page table.. */ 439 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1)) 440 #define pte_offset_kernel(pmd, address) \ 441 ((pte_t *) pmd_page_vaddr(*(pmd)) + pte_index(address)) 442 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address) 443 #define pte_unmap(pte) do { } while (0) 444 445 #define pte_unmap(pte) do { } while (0) 446 #define pte_unmap_nested(pte) do { } while (0) 447 448 extern void paging_init (void); 449 450 /* Used for deferring calls to flush_dcache_page() */ 451 452 #define PG_dcache_dirty PG_arch_1 453 454 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *); 455 456 /* Encode and de-code a swap entry */ 457 458 #define __swp_type(x) ((x).val & 0x1f) 459 #define __swp_offset(x) ( (((x).val >> 6) & 0x7) | \ 460 (((x).val >> 8) & ~0x7) ) 461 #define __swp_entry(type, offset) ((swp_entry_t) { (type) | \ 462 ((offset & 0x7) << 6) | \ 463 ((offset & ~0x7) << 8) }) 464 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 465 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 466 467 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep) 468 { 469 pte_t pte; 470 unsigned long flags; 471 472 if (!pte_young(*ptep)) 473 return 0; 474 475 spin_lock_irqsave(&pa_tlb_lock, flags); 476 pte = *ptep; 477 if (!pte_young(pte)) { 478 spin_unlock_irqrestore(&pa_tlb_lock, flags); 479 return 0; 480 } 481 purge_tlb_entries(vma->vm_mm, addr); 482 set_pte(ptep, pte_mkold(pte)); 483 spin_unlock_irqrestore(&pa_tlb_lock, flags); 484 return 1; 485 } 486 487 struct mm_struct; 488 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 489 { 490 pte_t old_pte; 491 unsigned long flags; 492 493 spin_lock_irqsave(&pa_tlb_lock, flags); 494 old_pte = *ptep; 495 if (pte_inserted(old_pte)) 496 purge_tlb_entries(mm, addr); 497 set_pte(ptep, __pte(0)); 498 spin_unlock_irqrestore(&pa_tlb_lock, flags); 499 500 return old_pte; 501 } 502 503 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 504 { 505 unsigned long flags; 506 spin_lock_irqsave(&pa_tlb_lock, flags); 507 purge_tlb_entries(mm, addr); 508 set_pte(ptep, pte_wrprotect(*ptep)); 509 spin_unlock_irqrestore(&pa_tlb_lock, flags); 510 } 511 512 #define pte_same(A,B) (pte_val(A) == pte_val(B)) 513 514 struct seq_file; 515 extern void arch_report_meminfo(struct seq_file *m); 516 517 #endif /* !__ASSEMBLY__ */ 518 519 520 /* TLB page size encoding - see table 3-1 in parisc20.pdf */ 521 #define _PAGE_SIZE_ENCODING_4K 0 522 #define _PAGE_SIZE_ENCODING_16K 1 523 #define _PAGE_SIZE_ENCODING_64K 2 524 #define _PAGE_SIZE_ENCODING_256K 3 525 #define _PAGE_SIZE_ENCODING_1M 4 526 #define _PAGE_SIZE_ENCODING_4M 5 527 #define _PAGE_SIZE_ENCODING_16M 6 528 #define _PAGE_SIZE_ENCODING_64M 7 529 530 #if defined(CONFIG_PARISC_PAGE_SIZE_4KB) 531 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_4K 532 #elif defined(CONFIG_PARISC_PAGE_SIZE_16KB) 533 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_16K 534 #elif defined(CONFIG_PARISC_PAGE_SIZE_64KB) 535 # define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_64K 536 #endif 537 538 539 #define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE) 540 541 /* We provide our own get_unmapped_area to provide cache coherency */ 542 543 #define HAVE_ARCH_UNMAPPED_AREA 544 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN 545 546 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 547 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 548 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 549 #define __HAVE_ARCH_PTE_SAME 550 #include <asm-generic/pgtable.h> 551 552 #endif /* _PARISC_PGTABLE_H */ 553