1 #ifndef _PARISC_PDC_H 2 #define _PARISC_PDC_H 3 4 /* 5 * PDC return values ... 6 * All PDC calls return a subset of these errors. 7 */ 8 9 #define PDC_WARN 3 /* Call completed with a warning */ 10 #define PDC_REQ_ERR_1 2 /* See above */ 11 #define PDC_REQ_ERR_0 1 /* Call would generate a requestor error */ 12 #define PDC_OK 0 /* Call completed successfully */ 13 #define PDC_BAD_PROC -1 /* Called non-existent procedure*/ 14 #define PDC_BAD_OPTION -2 /* Called with non-existent option */ 15 #define PDC_ERROR -3 /* Call could not complete without an error */ 16 #define PDC_NE_MOD -5 /* Module not found */ 17 #define PDC_NE_CELL_MOD -7 /* Cell module not found */ 18 #define PDC_INVALID_ARG -10 /* Called with an invalid argument */ 19 #define PDC_BUS_POW_WARN -12 /* Call could not complete in allowed power budget */ 20 #define PDC_NOT_NARROW -17 /* Narrow mode not supported */ 21 22 /* 23 * PDC entry points... 24 */ 25 26 #define PDC_POW_FAIL 1 /* perform a power-fail */ 27 #define PDC_POW_FAIL_PREPARE 0 /* prepare for powerfail */ 28 29 #define PDC_CHASSIS 2 /* PDC-chassis functions */ 30 #define PDC_CHASSIS_DISP 0 /* update chassis display */ 31 #define PDC_CHASSIS_WARN 1 /* return chassis warnings */ 32 #define PDC_CHASSIS_DISPWARN 2 /* update&return chassis status */ 33 #define PDC_RETURN_CHASSIS_INFO 128 /* HVERSION dependent: return chassis LED/LCD info */ 34 35 #define PDC_PIM 3 /* Get PIM data */ 36 #define PDC_PIM_HPMC 0 /* Transfer HPMC data */ 37 #define PDC_PIM_RETURN_SIZE 1 /* Get Max buffer needed for PIM*/ 38 #define PDC_PIM_LPMC 2 /* Transfer HPMC data */ 39 #define PDC_PIM_SOFT_BOOT 3 /* Transfer Soft Boot data */ 40 #define PDC_PIM_TOC 4 /* Transfer TOC data */ 41 42 #define PDC_MODEL 4 /* PDC model information call */ 43 #define PDC_MODEL_INFO 0 /* returns information */ 44 #define PDC_MODEL_BOOTID 1 /* set the BOOT_ID */ 45 #define PDC_MODEL_VERSIONS 2 /* returns cpu-internal versions*/ 46 #define PDC_MODEL_SYSMODEL 3 /* return system model info */ 47 #define PDC_MODEL_ENSPEC 4 /* enable specific option */ 48 #define PDC_MODEL_DISPEC 5 /* disable specific option */ 49 #define PDC_MODEL_CPU_ID 6 /* returns cpu-id (only newer machines!) */ 50 #define PDC_MODEL_CAPABILITIES 7 /* returns OS32/OS64-flags */ 51 /* Values for PDC_MODEL_CAPABILITIES non-equivalent virtual aliasing support */ 52 #define PDC_MODEL_IOPDIR_FDC (1 << 2) 53 #define PDC_MODEL_NVA_MASK (3 << 4) 54 #define PDC_MODEL_NVA_SUPPORTED (0 << 4) 55 #define PDC_MODEL_NVA_SLOW (1 << 4) 56 #define PDC_MODEL_NVA_UNSUPPORTED (3 << 4) 57 #define PDC_MODEL_GET_BOOT__OP 8 /* returns boot test options */ 58 #define PDC_MODEL_SET_BOOT__OP 9 /* set boot test options */ 59 60 #define PA89_INSTRUCTION_SET 0x4 /* capatibilies returned */ 61 #define PA90_INSTRUCTION_SET 0x8 62 63 #define PDC_CACHE 5 /* return/set cache (& TLB) info*/ 64 #define PDC_CACHE_INFO 0 /* returns information */ 65 #define PDC_CACHE_SET_COH 1 /* set coherence state */ 66 #define PDC_CACHE_RET_SPID 2 /* returns space-ID bits */ 67 68 #define PDC_HPA 6 /* return HPA of processor */ 69 #define PDC_HPA_PROCESSOR 0 70 #define PDC_HPA_MODULES 1 71 72 #define PDC_COPROC 7 /* Co-Processor (usually FP unit(s)) */ 73 #define PDC_COPROC_CFG 0 /* Co-Processor Cfg (FP unit(s) enabled?) */ 74 75 #define PDC_IODC 8 /* talk to IODC */ 76 #define PDC_IODC_READ 0 /* read IODC entry point */ 77 /* PDC_IODC_RI_ * INDEX parameter of PDC_IODC_READ */ 78 #define PDC_IODC_RI_DATA_BYTES 0 /* IODC Data Bytes */ 79 /* 1, 2 obsolete - HVERSION dependent*/ 80 #define PDC_IODC_RI_INIT 3 /* Initialize module */ 81 #define PDC_IODC_RI_IO 4 /* Module input/output */ 82 #define PDC_IODC_RI_SPA 5 /* Module input/output */ 83 #define PDC_IODC_RI_CONFIG 6 /* Module input/output */ 84 /* 7 obsolete - HVERSION dependent */ 85 #define PDC_IODC_RI_TEST 8 /* Module input/output */ 86 #define PDC_IODC_RI_TLB 9 /* Module input/output */ 87 #define PDC_IODC_NINIT 2 /* non-destructive init */ 88 #define PDC_IODC_DINIT 3 /* destructive init */ 89 #define PDC_IODC_MEMERR 4 /* check for memory errors */ 90 #define PDC_IODC_INDEX_DATA 0 /* get first 16 bytes from mod IODC */ 91 #define PDC_IODC_BUS_ERROR -4 /* bus error return value */ 92 #define PDC_IODC_INVALID_INDEX -5 /* invalid index return value */ 93 #define PDC_IODC_COUNT -6 /* count is too small */ 94 95 #define PDC_TOD 9 /* time-of-day clock (TOD) */ 96 #define PDC_TOD_READ 0 /* read TOD */ 97 #define PDC_TOD_WRITE 1 /* write TOD */ 98 99 100 #define PDC_STABLE 10 /* stable storage (sprockets) */ 101 #define PDC_STABLE_READ 0 102 #define PDC_STABLE_WRITE 1 103 #define PDC_STABLE_RETURN_SIZE 2 104 #define PDC_STABLE_VERIFY_CONTENTS 3 105 #define PDC_STABLE_INITIALIZE 4 106 107 #define PDC_NVOLATILE 11 /* often not implemented */ 108 109 #define PDC_ADD_VALID 12 /* Memory validation PDC call */ 110 #define PDC_ADD_VALID_VERIFY 0 /* Make PDC_ADD_VALID verify region */ 111 112 #define PDC_INSTR 15 /* get instr to invoke PDCE_CHECK() */ 113 114 #define PDC_PROC 16 /* (sprockets) */ 115 116 #define PDC_CONFIG 16 /* (sprockets) */ 117 #define PDC_CONFIG_DECONFIG 0 118 #define PDC_CONFIG_DRECONFIG 1 119 #define PDC_CONFIG_DRETURN_CONFIG 2 120 121 #define PDC_BLOCK_TLB 18 /* manage hardware block-TLB */ 122 #define PDC_BTLB_INFO 0 /* returns parameter */ 123 #define PDC_BTLB_INSERT 1 /* insert BTLB entry */ 124 #define PDC_BTLB_PURGE 2 /* purge BTLB entries */ 125 #define PDC_BTLB_PURGE_ALL 3 /* purge all BTLB entries */ 126 127 #define PDC_TLB 19 /* manage hardware TLB miss handling */ 128 #define PDC_TLB_INFO 0 /* returns parameter */ 129 #define PDC_TLB_SETUP 1 /* set up miss handling */ 130 131 #define PDC_MEM 20 /* Manage memory */ 132 #define PDC_MEM_MEMINFO 0 133 #define PDC_MEM_ADD_PAGE 1 134 #define PDC_MEM_CLEAR_PDT 2 135 #define PDC_MEM_READ_PDT 3 136 #define PDC_MEM_RESET_CLEAR 4 137 #define PDC_MEM_GOODMEM 5 138 #define PDC_MEM_TABLE 128 /* Non contig mem map (sprockets) */ 139 #define PDC_MEM_RETURN_ADDRESS_TABLE PDC_MEM_TABLE 140 #define PDC_MEM_GET_MEMORY_SYSTEM_TABLES_SIZE 131 141 #define PDC_MEM_GET_MEMORY_SYSTEM_TABLES 132 142 #define PDC_MEM_GET_PHYSICAL_LOCATION_FROM_MEMORY_ADDRESS 133 143 144 #define PDC_MEM_RET_SBE_REPLACED 5 /* PDC_MEM return values */ 145 #define PDC_MEM_RET_DUPLICATE_ENTRY 4 146 #define PDC_MEM_RET_BUF_SIZE_SMALL 1 147 #define PDC_MEM_RET_PDT_FULL -11 148 #define PDC_MEM_RET_INVALID_PHYSICAL_LOCATION ~0ULL 149 150 #define PDC_PSW 21 /* Get/Set default System Mask */ 151 #define PDC_PSW_MASK 0 /* Return mask */ 152 #define PDC_PSW_GET_DEFAULTS 1 /* Return defaults */ 153 #define PDC_PSW_SET_DEFAULTS 2 /* Set default */ 154 #define PDC_PSW_ENDIAN_BIT 1 /* set for big endian */ 155 #define PDC_PSW_WIDE_BIT 2 /* set for wide mode */ 156 157 #define PDC_SYSTEM_MAP 22 /* find system modules */ 158 #define PDC_FIND_MODULE 0 159 #define PDC_FIND_ADDRESS 1 160 #define PDC_TRANSLATE_PATH 2 161 162 #define PDC_SOFT_POWER 23 /* soft power switch */ 163 #define PDC_SOFT_POWER_INFO 0 /* return info about the soft power switch */ 164 #define PDC_SOFT_POWER_ENABLE 1 /* enable/disable soft power switch */ 165 166 167 /* HVERSION dependent */ 168 169 /* The PDC_MEM_MAP calls */ 170 #define PDC_MEM_MAP 128 /* on s700: return page info */ 171 #define PDC_MEM_MAP_HPA 0 /* returns hpa of a module */ 172 173 #define PDC_EEPROM 129 /* EEPROM access */ 174 #define PDC_EEPROM_READ_WORD 0 175 #define PDC_EEPROM_WRITE_WORD 1 176 #define PDC_EEPROM_READ_BYTE 2 177 #define PDC_EEPROM_WRITE_BYTE 3 178 #define PDC_EEPROM_EEPROM_PASSWORD -1000 179 180 #define PDC_NVM 130 /* NVM (non-volatile memory) access */ 181 #define PDC_NVM_READ_WORD 0 182 #define PDC_NVM_WRITE_WORD 1 183 #define PDC_NVM_READ_BYTE 2 184 #define PDC_NVM_WRITE_BYTE 3 185 186 #define PDC_SEED_ERROR 132 /* (sprockets) */ 187 188 #define PDC_IO 135 /* log error info, reset IO system */ 189 #define PDC_IO_READ_AND_CLEAR_ERRORS 0 190 #define PDC_IO_RESET 1 191 #define PDC_IO_RESET_DEVICES 2 192 /* sets bits 6&7 (little endian) of the HcControl Register */ 193 #define PDC_IO_USB_SUSPEND 0xC000000000000000 194 #define PDC_IO_EEPROM_IO_ERR_TABLE_FULL -5 /* return value */ 195 #define PDC_IO_NO_SUSPEND -6 /* return value */ 196 197 #define PDC_BROADCAST_RESET 136 /* reset all processors */ 198 #define PDC_DO_RESET 0 /* option: perform a broadcast reset */ 199 #define PDC_DO_FIRM_TEST_RESET 1 /* Do broadcast reset with bitmap */ 200 #define PDC_BR_RECONFIGURATION 2 /* reset w/reconfiguration */ 201 #define PDC_FIRM_TEST_MAGIC 0xab9ec36fUL /* for this reboot only */ 202 203 #define PDC_LAN_STATION_ID 138 /* Hversion dependent mechanism for */ 204 #define PDC_LAN_STATION_ID_READ 0 /* getting the lan station address */ 205 206 #define PDC_LAN_STATION_ID_SIZE 6 207 208 #define PDC_CHECK_RANGES 139 /* (sprockets) */ 209 210 #define PDC_NV_SECTIONS 141 /* (sprockets) */ 211 212 #define PDC_PERFORMANCE 142 /* performance monitoring */ 213 214 #define PDC_SYSTEM_INFO 143 /* system information */ 215 #define PDC_SYSINFO_RETURN_INFO_SIZE 0 216 #define PDC_SYSINFO_RRETURN_SYS_INFO 1 217 #define PDC_SYSINFO_RRETURN_ERRORS 2 218 #define PDC_SYSINFO_RRETURN_WARNINGS 3 219 #define PDC_SYSINFO_RETURN_REVISIONS 4 220 #define PDC_SYSINFO_RRETURN_DIAGNOSE 5 221 #define PDC_SYSINFO_RRETURN_HV_DIAGNOSE 1005 222 223 #define PDC_RDR 144 /* (sprockets) */ 224 #define PDC_RDR_READ_BUFFER 0 225 #define PDC_RDR_READ_SINGLE 1 226 #define PDC_RDR_WRITE_SINGLE 2 227 228 #define PDC_INTRIGUE 145 /* (sprockets) */ 229 #define PDC_INTRIGUE_WRITE_BUFFER 0 230 #define PDC_INTRIGUE_GET_SCRATCH_BUFSIZE 1 231 #define PDC_INTRIGUE_START_CPU_COUNTERS 2 232 #define PDC_INTRIGUE_STOP_CPU_COUNTERS 3 233 234 #define PDC_STI 146 /* STI access */ 235 /* same as PDC_PCI_XXX values (see below) */ 236 237 /* Legacy PDC definitions for same stuff */ 238 #define PDC_PCI_INDEX 147 239 #define PDC_PCI_INTERFACE_INFO 0 240 #define PDC_PCI_SLOT_INFO 1 241 #define PDC_PCI_INFLIGHT_BYTES 2 242 #define PDC_PCI_READ_CONFIG 3 243 #define PDC_PCI_WRITE_CONFIG 4 244 #define PDC_PCI_READ_PCI_IO 5 245 #define PDC_PCI_WRITE_PCI_IO 6 246 #define PDC_PCI_READ_CONFIG_DELAY 7 247 #define PDC_PCI_UPDATE_CONFIG_DELAY 8 248 #define PDC_PCI_PCI_PATH_TO_PCI_HPA 9 249 #define PDC_PCI_PCI_HPA_TO_PCI_PATH 10 250 #define PDC_PCI_PCI_PATH_TO_PCI_BUS 11 251 #define PDC_PCI_PCI_RESERVED 12 252 #define PDC_PCI_PCI_INT_ROUTE_SIZE 13 253 #define PDC_PCI_GET_INT_TBL_SIZE PDC_PCI_PCI_INT_ROUTE_SIZE 254 #define PDC_PCI_PCI_INT_ROUTE 14 255 #define PDC_PCI_GET_INT_TBL PDC_PCI_PCI_INT_ROUTE 256 #define PDC_PCI_READ_MON_TYPE 15 257 #define PDC_PCI_WRITE_MON_TYPE 16 258 259 260 /* Get SCSI Interface Card info: SDTR, SCSI ID, mode (SE vs LVD) */ 261 #define PDC_INITIATOR 163 262 #define PDC_GET_INITIATOR 0 263 #define PDC_SET_INITIATOR 1 264 #define PDC_DELETE_INITIATOR 2 265 #define PDC_RETURN_TABLE_SIZE 3 266 #define PDC_RETURN_TABLE 4 267 268 #define PDC_LINK 165 /* (sprockets) */ 269 #define PDC_LINK_PCI_ENTRY_POINTS 0 /* list (Arg1) = 0 */ 270 #define PDC_LINK_USB_ENTRY_POINTS 1 /* list (Arg1) = 1 */ 271 272 /* cl_class 273 * page 3-33 of IO-Firmware ARS 274 * IODC ENTRY_INIT(Search first) RET[1] 275 */ 276 #define CL_NULL 0 /* invalid */ 277 #define CL_RANDOM 1 /* random access (as disk) */ 278 #define CL_SEQU 2 /* sequential access (as tape) */ 279 #define CL_DUPLEX 7 /* full-duplex point-to-point (RS-232, Net) */ 280 #define CL_KEYBD 8 /* half-duplex console (HIL Keyboard) */ 281 #define CL_DISPL 9 /* half-duplex console (display) */ 282 #define CL_FC 10 /* FiberChannel access media */ 283 284 /* IODC ENTRY_INIT() */ 285 #define ENTRY_INIT_SRCH_FRST 2 286 #define ENTRY_INIT_SRCH_NEXT 3 287 #define ENTRY_INIT_MOD_DEV 4 288 #define ENTRY_INIT_DEV 5 289 #define ENTRY_INIT_MOD 6 290 #define ENTRY_INIT_MSG 9 291 292 /* IODC ENTRY_IO() */ 293 #define ENTRY_IO_BOOTIN 0 294 #define ENTRY_IO_BOOTOUT 1 295 #define ENTRY_IO_CIN 2 296 #define ENTRY_IO_COUT 3 297 #define ENTRY_IO_CLOSE 4 298 #define ENTRY_IO_GETMSG 9 299 #define ENTRY_IO_BBLOCK_IN 16 300 #define ENTRY_IO_BBLOCK_OUT 17 301 302 /* IODC ENTRY_SPA() */ 303 304 /* IODC ENTRY_CONFIG() */ 305 306 /* IODC ENTRY_TEST() */ 307 308 /* IODC ENTRY_TLB() */ 309 310 /* constants for OS (NVM...) */ 311 #define OS_ID_NONE 0 /* Undefined OS ID */ 312 #define OS_ID_HPUX 1 /* HP-UX OS */ 313 #define OS_ID_MPEXL 2 /* MPE XL OS */ 314 #define OS_ID_OSF 3 /* OSF OS */ 315 #define OS_ID_HPRT 4 /* HP-RT OS */ 316 #define OS_ID_NOVEL 5 /* NOVELL OS */ 317 #define OS_ID_LINUX 6 /* Linux */ 318 319 320 /* constants for PDC_CHASSIS */ 321 #define OSTAT_OFF 0 322 #define OSTAT_FLT 1 323 #define OSTAT_TEST 2 324 #define OSTAT_INIT 3 325 #define OSTAT_SHUT 4 326 #define OSTAT_WARN 5 327 #define OSTAT_RUN 6 328 #define OSTAT_ON 7 329 330 /* Page Zero constant offsets used by the HPMC handler */ 331 #define BOOT_CONSOLE_HPA_OFFSET 0x3c0 332 #define BOOT_CONSOLE_SPA_OFFSET 0x3c4 333 #define BOOT_CONSOLE_PATH_OFFSET 0x3a8 334 335 /* size of the pdc_result buffer for firmware.c */ 336 #define NUM_PDC_RESULT 32 337 338 #if !defined(__ASSEMBLY__) 339 #ifdef __KERNEL__ 340 341 #include <linux/types.h> 342 343 extern int pdc_type; 344 345 /* Values for pdc_type */ 346 #define PDC_TYPE_ILLEGAL -1 347 #define PDC_TYPE_PAT 0 /* 64-bit PAT-PDC */ 348 #define PDC_TYPE_SYSTEM_MAP 1 /* 32-bit, but supports PDC_SYSTEM_MAP */ 349 #define PDC_TYPE_SNAKE 2 /* Doesn't support SYSTEM_MAP */ 350 351 struct pdc_chassis_info { /* for PDC_CHASSIS_INFO */ 352 unsigned long actcnt; /* actual number of bytes returned */ 353 unsigned long maxcnt; /* maximum number of bytes that could be returned */ 354 }; 355 356 struct pdc_coproc_cfg { /* for PDC_COPROC_CFG */ 357 unsigned long ccr_functional; 358 unsigned long ccr_present; 359 unsigned long revision; 360 unsigned long model; 361 }; 362 363 struct pdc_model { /* for PDC_MODEL */ 364 unsigned long hversion; 365 unsigned long sversion; 366 unsigned long hw_id; 367 unsigned long boot_id; 368 unsigned long sw_id; 369 unsigned long sw_cap; 370 unsigned long arch_rev; 371 unsigned long pot_key; 372 unsigned long curr_key; 373 }; 374 375 struct pdc_cache_cf { /* for PDC_CACHE (I/D-caches) */ 376 unsigned long 377 #ifdef CONFIG_64BIT 378 cc_padW:32, 379 #endif 380 cc_alias: 4, /* alias boundaries for virtual addresses */ 381 cc_block: 4, /* to determine most efficient stride */ 382 cc_line : 3, /* maximum amount written back as a result of store (multiple of 16 bytes) */ 383 cc_shift: 2, /* how much to shift cc_block left */ 384 cc_wt : 1, /* 0 = WT-Dcache, 1 = WB-Dcache */ 385 cc_sh : 2, /* 0 = separate I/D-cache, else shared I/D-cache */ 386 cc_cst : 3, /* 0 = incoherent D-cache, 1=coherent D-cache */ 387 cc_pad1 : 10, /* reserved */ 388 cc_hv : 3; /* hversion dependent */ 389 }; 390 391 struct pdc_tlb_cf { /* for PDC_CACHE (I/D-TLB's) */ 392 unsigned long tc_pad0:12, /* reserved */ 393 #ifdef CONFIG_64BIT 394 tc_padW:32, 395 #endif 396 tc_sh : 2, /* 0 = separate I/D-TLB, else shared I/D-TLB */ 397 tc_hv : 1, /* HV */ 398 tc_page : 1, /* 0 = 2K page-size-machine, 1 = 4k page size */ 399 tc_cst : 3, /* 0 = incoherent operations, else coherent operations */ 400 tc_aid : 5, /* ITLB: width of access ids of processor (encoded!) */ 401 tc_pad1 : 8; /* ITLB: width of space-registers (encoded) */ 402 }; 403 404 struct pdc_cache_info { /* main-PDC_CACHE-structure (caches & TLB's) */ 405 /* I-cache */ 406 unsigned long ic_size; /* size in bytes */ 407 struct pdc_cache_cf ic_conf; /* configuration */ 408 unsigned long ic_base; /* base-addr */ 409 unsigned long ic_stride; 410 unsigned long ic_count; 411 unsigned long ic_loop; 412 /* D-cache */ 413 unsigned long dc_size; /* size in bytes */ 414 struct pdc_cache_cf dc_conf; /* configuration */ 415 unsigned long dc_base; /* base-addr */ 416 unsigned long dc_stride; 417 unsigned long dc_count; 418 unsigned long dc_loop; 419 /* Instruction-TLB */ 420 unsigned long it_size; /* number of entries in I-TLB */ 421 struct pdc_tlb_cf it_conf; /* I-TLB-configuration */ 422 unsigned long it_sp_base; 423 unsigned long it_sp_stride; 424 unsigned long it_sp_count; 425 unsigned long it_off_base; 426 unsigned long it_off_stride; 427 unsigned long it_off_count; 428 unsigned long it_loop; 429 /* data-TLB */ 430 unsigned long dt_size; /* number of entries in D-TLB */ 431 struct pdc_tlb_cf dt_conf; /* D-TLB-configuration */ 432 unsigned long dt_sp_base; 433 unsigned long dt_sp_stride; 434 unsigned long dt_sp_count; 435 unsigned long dt_off_base; 436 unsigned long dt_off_stride; 437 unsigned long dt_off_count; 438 unsigned long dt_loop; 439 }; 440 441 #if 0 442 /* If you start using the next struct, you'll have to adjust it to 443 * work with 64-bit firmware I think -PB 444 */ 445 struct pdc_iodc { /* PDC_IODC */ 446 unsigned char hversion_model; 447 unsigned char hversion; 448 unsigned char spa; 449 unsigned char type; 450 unsigned int sversion_rev:4; 451 unsigned int sversion_model:19; 452 unsigned int sversion_opt:8; 453 unsigned char rev; 454 unsigned char dep; 455 unsigned char features; 456 unsigned char pad1; 457 unsigned int checksum:16; 458 unsigned int length:16; 459 unsigned int pad[15]; 460 } __attribute__((aligned(8))) ; 461 #endif 462 463 #ifndef CONFIG_PA20 464 /* no BLTBs in pa2.0 processors */ 465 struct pdc_btlb_info_range { 466 __u8 res00; 467 __u8 num_i; 468 __u8 num_d; 469 __u8 num_comb; 470 }; 471 472 struct pdc_btlb_info { /* PDC_BLOCK_TLB, return of PDC_BTLB_INFO */ 473 unsigned int min_size; /* minimum size of BTLB in pages */ 474 unsigned int max_size; /* maximum size of BTLB in pages */ 475 struct pdc_btlb_info_range fixed_range_info; 476 struct pdc_btlb_info_range variable_range_info; 477 }; 478 479 #endif /* !CONFIG_PA20 */ 480 481 #ifdef CONFIG_64BIT 482 struct pdc_memory_table_raddr { /* PDC_MEM/PDC_MEM_TABLE (return info) */ 483 unsigned long entries_returned; 484 unsigned long entries_total; 485 }; 486 487 struct pdc_memory_table { /* PDC_MEM/PDC_MEM_TABLE (arguments) */ 488 unsigned long paddr; 489 unsigned int pages; 490 unsigned int reserved; 491 }; 492 #endif /* CONFIG_64BIT */ 493 494 struct pdc_system_map_mod_info { /* PDC_SYSTEM_MAP/FIND_MODULE */ 495 unsigned long mod_addr; 496 unsigned long mod_pgs; 497 unsigned long add_addrs; 498 }; 499 500 struct pdc_system_map_addr_info { /* PDC_SYSTEM_MAP/FIND_ADDRESS */ 501 unsigned long mod_addr; 502 unsigned long mod_pgs; 503 }; 504 505 struct pdc_initiator { /* PDC_INITIATOR */ 506 int host_id; 507 int factor; 508 int width; 509 int mode; 510 }; 511 512 struct hardware_path { 513 char flags; /* see bit definitions below */ 514 char bc[6]; /* Bus Converter routing info to a specific */ 515 /* I/O adaptor (< 0 means none, > 63 resvd) */ 516 char mod; /* fixed field of specified module */ 517 }; 518 519 /* 520 * Device path specifications used by PDC. 521 */ 522 struct pdc_module_path { 523 struct hardware_path path; 524 unsigned int layers[6]; /* device-specific info (ctlr #, unit # ...) */ 525 }; 526 527 #ifndef CONFIG_PA20 528 /* Only used on some pre-PA2.0 boxes */ 529 struct pdc_memory_map { /* PDC_MEMORY_MAP */ 530 unsigned long hpa; /* mod's register set address */ 531 unsigned long more_pgs; /* number of additional I/O pgs */ 532 }; 533 #endif 534 535 struct pdc_tod { 536 unsigned long tod_sec; 537 unsigned long tod_usec; 538 }; 539 540 /* architected results from PDC_PIM/transfer hpmc on a PA1.1 machine */ 541 542 struct pdc_hpmc_pim_11 { /* PDC_PIM */ 543 __u32 gr[32]; 544 __u32 cr[32]; 545 __u32 sr[8]; 546 __u32 iasq_back; 547 __u32 iaoq_back; 548 __u32 check_type; 549 __u32 cpu_state; 550 __u32 rsvd1; 551 __u32 cache_check; 552 __u32 tlb_check; 553 __u32 bus_check; 554 __u32 assists_check; 555 __u32 rsvd2; 556 __u32 assist_state; 557 __u32 responder_addr; 558 __u32 requestor_addr; 559 __u32 path_info; 560 __u64 fr[32]; 561 }; 562 563 /* 564 * architected results from PDC_PIM/transfer hpmc on a PA2.0 machine 565 * 566 * Note that PDC_PIM doesn't care whether or not wide mode was enabled 567 * so the results are different on PA1.1 vs. PA2.0 when in narrow mode. 568 * 569 * Note also that there are unarchitected results available, which 570 * are hversion dependent. Do a "ser pim 0 hpmc" after rebooting, since 571 * the firmware is probably the best way of printing hversion dependent 572 * data. 573 */ 574 575 struct pdc_hpmc_pim_20 { /* PDC_PIM */ 576 __u64 gr[32]; 577 __u64 cr[32]; 578 __u64 sr[8]; 579 __u64 iasq_back; 580 __u64 iaoq_back; 581 __u32 check_type; 582 __u32 cpu_state; 583 __u32 cache_check; 584 __u32 tlb_check; 585 __u32 bus_check; 586 __u32 assists_check; 587 __u32 assist_state; 588 __u32 path_info; 589 __u64 responder_addr; 590 __u64 requestor_addr; 591 __u64 fr[32]; 592 }; 593 594 void pdc_console_init(void); /* in pdc_console.c */ 595 void pdc_console_restart(void); 596 597 void setup_pdc(void); /* in inventory.c */ 598 599 /* wrapper-functions from pdc.c */ 600 601 int pdc_add_valid(unsigned long address); 602 int pdc_chassis_info(struct pdc_chassis_info *chassis_info, void *led_info, unsigned long len); 603 int pdc_chassis_disp(unsigned long disp); 604 int pdc_chassis_warn(unsigned long *warn); 605 int pdc_coproc_cfg(struct pdc_coproc_cfg *pdc_coproc_info); 606 int pdc_coproc_cfg_unlocked(struct pdc_coproc_cfg *pdc_coproc_info); 607 int pdc_iodc_read(unsigned long *actcnt, unsigned long hpa, unsigned int index, 608 void *iodc_data, unsigned int iodc_data_size); 609 int pdc_system_map_find_mods(struct pdc_system_map_mod_info *pdc_mod_info, 610 struct pdc_module_path *mod_path, long mod_index); 611 int pdc_system_map_find_addrs(struct pdc_system_map_addr_info *pdc_addr_info, 612 long mod_index, long addr_index); 613 int pdc_model_info(struct pdc_model *model); 614 int pdc_model_sysmodel(char *name); 615 int pdc_model_cpuid(unsigned long *cpu_id); 616 int pdc_model_versions(unsigned long *versions, int id); 617 int pdc_model_capabilities(unsigned long *capabilities); 618 int pdc_cache_info(struct pdc_cache_info *cache); 619 int pdc_spaceid_bits(unsigned long *space_bits); 620 #ifndef CONFIG_PA20 621 int pdc_btlb_info(struct pdc_btlb_info *btlb); 622 int pdc_mem_map_hpa(struct pdc_memory_map *r_addr, struct pdc_module_path *mod_path); 623 #endif /* !CONFIG_PA20 */ 624 int pdc_lan_station_id(char *lan_addr, unsigned long net_hpa); 625 626 int pdc_stable_read(unsigned long staddr, void *memaddr, unsigned long count); 627 int pdc_stable_write(unsigned long staddr, void *memaddr, unsigned long count); 628 int pdc_stable_get_size(unsigned long *size); 629 int pdc_stable_verify_contents(void); 630 int pdc_stable_initialize(void); 631 632 int pdc_pci_irt_size(unsigned long *num_entries, unsigned long hpa); 633 int pdc_pci_irt(unsigned long num_entries, unsigned long hpa, void *tbl); 634 635 int pdc_get_initiator(struct hardware_path *, struct pdc_initiator *); 636 int pdc_tod_read(struct pdc_tod *tod); 637 int pdc_tod_set(unsigned long sec, unsigned long usec); 638 639 #ifdef CONFIG_64BIT 640 int pdc_mem_mem_table(struct pdc_memory_table_raddr *r_addr, 641 struct pdc_memory_table *tbl, unsigned long entries); 642 #endif 643 644 void set_firmware_width(void); 645 void set_firmware_width_unlocked(void); 646 int pdc_do_firm_test_reset(unsigned long ftc_bitmap); 647 int pdc_do_reset(void); 648 int pdc_soft_power_info(unsigned long *power_reg); 649 int pdc_soft_power_button(int sw_control); 650 void pdc_io_reset(void); 651 void pdc_io_reset_devices(void); 652 int pdc_iodc_getc(void); 653 int pdc_iodc_print(const unsigned char *str, unsigned count); 654 655 void pdc_emergency_unlock(void); 656 int pdc_sti_call(unsigned long func, unsigned long flags, 657 unsigned long inptr, unsigned long outputr, 658 unsigned long glob_cfg); 659 660 static inline char * os_id_to_string(u16 os_id) { 661 switch(os_id) { 662 case OS_ID_NONE: return "No OS"; 663 case OS_ID_HPUX: return "HP-UX"; 664 case OS_ID_MPEXL: return "MPE-iX"; 665 case OS_ID_OSF: return "OSF"; 666 case OS_ID_HPRT: return "HP-RT"; 667 case OS_ID_NOVEL: return "Novell Netware"; 668 case OS_ID_LINUX: return "Linux"; 669 default: return "Unknown"; 670 } 671 } 672 673 #endif /* __KERNEL__ */ 674 675 #define PAGE0 ((struct zeropage *)__PAGE_OFFSET) 676 677 /* DEFINITION OF THE ZERO-PAGE (PAG0) */ 678 /* based on work by Jason Eckhardt (jason@equator.com) */ 679 680 /* flags of the device_path */ 681 #define PF_AUTOBOOT 0x80 682 #define PF_AUTOSEARCH 0x40 683 #define PF_TIMER 0x0F 684 685 struct device_path { /* page 1-69 */ 686 unsigned char flags; /* flags see above! */ 687 unsigned char bc[6]; /* bus converter routing info */ 688 unsigned char mod; 689 unsigned int layers[6];/* device-specific layer-info */ 690 } __attribute__((aligned(8))) ; 691 692 struct pz_device { 693 struct device_path dp; /* see above */ 694 /* struct iomod *hpa; */ 695 unsigned int hpa; /* HPA base address */ 696 /* char *spa; */ 697 unsigned int spa; /* SPA base address */ 698 /* int (*iodc_io)(struct iomod*, ...); */ 699 unsigned int iodc_io; /* device entry point */ 700 short pad; /* reserved */ 701 unsigned short cl_class;/* see below */ 702 } __attribute__((aligned(8))) ; 703 704 struct zeropage { 705 /* [0x000] initialize vectors (VEC) */ 706 unsigned int vec_special; /* must be zero */ 707 /* int (*vec_pow_fail)(void);*/ 708 unsigned int vec_pow_fail; /* power failure handler */ 709 /* int (*vec_toc)(void); */ 710 unsigned int vec_toc; 711 unsigned int vec_toclen; 712 /* int (*vec_rendz)(void); */ 713 unsigned int vec_rendz; 714 int vec_pow_fail_flen; 715 int vec_pad[10]; 716 717 /* [0x040] reserved processor dependent */ 718 int pad0[112]; 719 720 /* [0x200] reserved */ 721 int pad1[84]; 722 723 /* [0x350] memory configuration (MC) */ 724 int memc_cont; /* contiguous mem size (bytes) */ 725 int memc_phsize; /* physical memory size */ 726 int memc_adsize; /* additional mem size, bytes of SPA space used by PDC */ 727 unsigned int mem_pdc_hi; /* used for 64-bit */ 728 729 /* [0x360] various parameters for the boot-CPU */ 730 /* unsigned int *mem_booterr[8]; */ 731 unsigned int mem_booterr[8]; /* ptr to boot errors */ 732 unsigned int mem_free; /* first location, where OS can be loaded */ 733 /* struct iomod *mem_hpa; */ 734 unsigned int mem_hpa; /* HPA of the boot-CPU */ 735 /* int (*mem_pdc)(int, ...); */ 736 unsigned int mem_pdc; /* PDC entry point */ 737 unsigned int mem_10msec; /* number of clock ticks in 10msec */ 738 739 /* [0x390] initial memory module (IMM) */ 740 /* struct iomod *imm_hpa; */ 741 unsigned int imm_hpa; /* HPA of the IMM */ 742 int imm_soft_boot; /* 0 = was hard boot, 1 = was soft boot */ 743 unsigned int imm_spa_size; /* SPA size of the IMM in bytes */ 744 unsigned int imm_max_mem; /* bytes of mem in IMM */ 745 746 /* [0x3A0] boot console, display device and keyboard */ 747 struct pz_device mem_cons; /* description of console device */ 748 struct pz_device mem_boot; /* description of boot device */ 749 struct pz_device mem_kbd; /* description of keyboard device */ 750 751 /* [0x430] reserved */ 752 int pad430[116]; 753 754 /* [0x600] processor dependent */ 755 __u32 pad600[1]; 756 __u32 proc_sti; /* pointer to STI ROM */ 757 __u32 pad608[126]; 758 }; 759 760 #endif /* !defined(__ASSEMBLY__) */ 761 762 #endif /* _PARISC_PDC_H */ 763