1 #ifndef __ASM_PARISC_PCI_H 2 #define __ASM_PARISC_PCI_H 3 4 #include <asm/scatterlist.h> 5 6 7 8 /* 9 ** HP PCI platforms generally support multiple bus adapters. 10 ** (workstations 1-~4, servers 2-~32) 11 ** 12 ** Newer platforms number the busses across PCI bus adapters *sparsely*. 13 ** E.g. 0, 8, 16, ... 14 ** 15 ** Under a PCI bus, most HP platforms support PPBs up to two or three 16 ** levels deep. See "Bit3" product line. 17 */ 18 #define PCI_MAX_BUSSES 256 19 20 21 /* To be used as: mdelay(pci_post_reset_delay); 22 * 23 * post_reset is the time the kernel should stall to prevent anyone from 24 * accessing the PCI bus once #RESET is de-asserted. 25 * PCI spec somewhere says 1 second but with multi-PCI bus systems, 26 * this makes the boot time much longer than necessary. 27 * 20ms seems to work for all the HP PCI implementations to date. 28 */ 29 #define pci_post_reset_delay 50 30 31 32 /* 33 ** pci_hba_data (aka H2P_OBJECT in HP/UX) 34 ** 35 ** This is the "common" or "base" data structure which HBA drivers 36 ** (eg Dino or LBA) are required to place at the top of their own 37 ** platform_data structure. I've heard this called "C inheritance" too. 38 ** 39 ** Data needed by pcibios layer belongs here. 40 */ 41 struct pci_hba_data { 42 void __iomem *base_addr; /* aka Host Physical Address */ 43 const struct parisc_device *dev; /* device from PA bus walk */ 44 struct pci_bus *hba_bus; /* primary PCI bus below HBA */ 45 int hba_num; /* I/O port space access "key" */ 46 struct resource bus_num; /* PCI bus numbers */ 47 struct resource io_space; /* PIOP */ 48 struct resource lmmio_space; /* bus addresses < 4Gb */ 49 struct resource elmmio_space; /* additional bus addresses < 4Gb */ 50 struct resource gmmio_space; /* bus addresses > 4Gb */ 51 52 /* NOTE: Dino code assumes it can use *all* of the lmmio_space, 53 * elmmio_space and gmmio_space as a contiguous array of 54 * resources. This #define represents the array size */ 55 #define DINO_MAX_LMMIO_RESOURCES 3 56 57 unsigned long lmmio_space_offset; /* CPU view - PCI view */ 58 void * iommu; /* IOMMU this device is under */ 59 /* REVISIT - spinlock to protect resources? */ 60 61 #define HBA_NAME_SIZE 16 62 char io_name[HBA_NAME_SIZE]; 63 char lmmio_name[HBA_NAME_SIZE]; 64 char elmmio_name[HBA_NAME_SIZE]; 65 char gmmio_name[HBA_NAME_SIZE]; 66 }; 67 68 #define HBA_DATA(d) ((struct pci_hba_data *) (d)) 69 70 /* 71 ** We support 2^16 I/O ports per HBA. These are set up in the form 72 ** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port 73 ** space address. 74 */ 75 #define HBA_PORT_SPACE_BITS 16 76 77 #define HBA_PORT_BASE(h) ((h) << HBA_PORT_SPACE_BITS) 78 #define HBA_PORT_SPACE_SIZE (1UL << HBA_PORT_SPACE_BITS) 79 80 #define PCI_PORT_HBA(a) ((a) >> HBA_PORT_SPACE_BITS) 81 #define PCI_PORT_ADDR(a) ((a) & (HBA_PORT_SPACE_SIZE - 1)) 82 83 #ifdef CONFIG_64BIT 84 #define PCI_F_EXTEND 0xffffffff00000000UL 85 #define PCI_IS_LMMIO(hba,a) pci_is_lmmio(hba,a) 86 87 /* We need to know if an address is LMMMIO or GMMIO. 88 * LMMIO requires mangling and GMMIO we must use as-is. 89 */ 90 static __inline__ int pci_is_lmmio(struct pci_hba_data *hba, unsigned long a) 91 { 92 return(((a) & PCI_F_EXTEND) == PCI_F_EXTEND); 93 } 94 95 /* 96 ** Convert between PCI (IO_VIEW) addresses and processor (PA_VIEW) addresses. 97 ** See pci.c for more conversions used by Generic PCI code. 98 ** 99 ** Platform characteristics/firmware guarantee that 100 ** (1) PA_VIEW - IO_VIEW = lmmio_offset for both LMMIO and ELMMIO 101 ** (2) PA_VIEW == IO_VIEW for GMMIO 102 */ 103 #define PCI_BUS_ADDR(hba,a) (PCI_IS_LMMIO(hba,a) \ 104 ? ((a) - hba->lmmio_space_offset) /* mangle LMMIO */ \ 105 : (a)) /* GMMIO */ 106 #define PCI_HOST_ADDR(hba,a) (((a) & PCI_F_EXTEND) == 0 \ 107 ? (a) + hba->lmmio_space_offset \ 108 : (a)) 109 110 #else /* !CONFIG_64BIT */ 111 112 #define PCI_BUS_ADDR(hba,a) (a) 113 #define PCI_HOST_ADDR(hba,a) (a) 114 #define PCI_F_EXTEND 0UL 115 #define PCI_IS_LMMIO(hba,a) (1) /* 32-bit doesn't support GMMIO */ 116 117 #endif /* !CONFIG_64BIT */ 118 119 /* 120 ** KLUGE: linux/pci.h include asm/pci.h BEFORE declaring struct pci_bus 121 ** (This eliminates some of the warnings). 122 */ 123 struct pci_bus; 124 struct pci_dev; 125 126 /* 127 * If the PCI device's view of memory is the same as the CPU's view of memory, 128 * PCI_DMA_BUS_IS_PHYS is true. The networking and block device layers use 129 * this boolean for bounce buffer decisions. 130 */ 131 #ifdef CONFIG_PA20 132 /* All PA-2.0 machines have an IOMMU. */ 133 #define PCI_DMA_BUS_IS_PHYS 0 134 #define parisc_has_iommu() do { } while (0) 135 #else 136 137 #if defined(CONFIG_IOMMU_CCIO) || defined(CONFIG_IOMMU_SBA) 138 extern int parisc_bus_is_phys; /* in arch/parisc/kernel/setup.c */ 139 #define PCI_DMA_BUS_IS_PHYS parisc_bus_is_phys 140 #define parisc_has_iommu() do { parisc_bus_is_phys = 0; } while (0) 141 #else 142 #define PCI_DMA_BUS_IS_PHYS 1 143 #define parisc_has_iommu() do { } while (0) 144 #endif 145 146 #endif /* !CONFIG_PA20 */ 147 148 149 /* 150 ** Most PCI devices (eg Tulip, NCR720) also export the same registers 151 ** to both MMIO and I/O port space. Due to poor performance of I/O Port 152 ** access under HP PCI bus adapters, strongly recommend the use of MMIO 153 ** address space. 154 ** 155 ** While I'm at it more PA programming notes: 156 ** 157 ** 1) MMIO stores (writes) are posted operations. This means the processor 158 ** gets an "ACK" before the write actually gets to the device. A read 159 ** to the same device (or typically the bus adapter above it) will 160 ** force in-flight write transaction(s) out to the targeted device 161 ** before the read can complete. 162 ** 163 ** 2) The Programmed I/O (PIO) data may not always be strongly ordered with 164 ** respect to DMA on all platforms. Ie PIO data can reach the processor 165 ** before in-flight DMA reaches memory. Since most SMP PA platforms 166 ** are I/O coherent, it generally doesn't matter...but sometimes 167 ** it does. 168 ** 169 ** I've helped device driver writers debug both types of problems. 170 */ 171 struct pci_port_ops { 172 u8 (*inb) (struct pci_hba_data *hba, u16 port); 173 u16 (*inw) (struct pci_hba_data *hba, u16 port); 174 u32 (*inl) (struct pci_hba_data *hba, u16 port); 175 void (*outb) (struct pci_hba_data *hba, u16 port, u8 data); 176 void (*outw) (struct pci_hba_data *hba, u16 port, u16 data); 177 void (*outl) (struct pci_hba_data *hba, u16 port, u32 data); 178 }; 179 180 181 struct pci_bios_ops { 182 void (*init)(void); 183 void (*fixup_bus)(struct pci_bus *bus); 184 }; 185 186 /* pci_unmap_{single,page} is not a nop, thus... */ 187 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ 188 dma_addr_t ADDR_NAME; 189 #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ 190 __u32 LEN_NAME; 191 #define pci_unmap_addr(PTR, ADDR_NAME) \ 192 ((PTR)->ADDR_NAME) 193 #define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \ 194 (((PTR)->ADDR_NAME) = (VAL)) 195 #define pci_unmap_len(PTR, LEN_NAME) \ 196 ((PTR)->LEN_NAME) 197 #define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ 198 (((PTR)->LEN_NAME) = (VAL)) 199 200 /* 201 ** Stuff declared in arch/parisc/kernel/pci.c 202 */ 203 extern struct pci_port_ops *pci_port; 204 extern struct pci_bios_ops *pci_bios; 205 206 #ifdef CONFIG_PCI 207 extern void pcibios_register_hba(struct pci_hba_data *); 208 extern void pcibios_set_master(struct pci_dev *); 209 #else 210 static inline void pcibios_register_hba(struct pci_hba_data *x) 211 { 212 } 213 #endif 214 215 /* 216 * pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus() 217 * 0 == check if bridge is numbered before re-numbering. 218 * 1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges. 219 * 220 * We *should* set this to zero for "legacy" platforms and one 221 * for PAT platforms. 222 * 223 * But legacy platforms also need to renumber the busses below a Host 224 * Bus controller. Adding a 4-port Tulip card on the first PCI root 225 * bus of a C200 resulted in the secondary bus being numbered as 1. 226 * The second PCI host bus controller's root bus had already been 227 * assigned bus number 1 by firmware and sysfs complained. 228 * 229 * Firmware isn't doing anything wrong here since each controller 230 * is its own PCI domain. It's simpler and easier for us to renumber 231 * the busses rather than treat each Dino as a separate PCI domain. 232 * Eventually, we may want to introduce PCI domains for Superdome or 233 * rp7420/8420 boxes and then revisit this issue. 234 */ 235 #define pcibios_assign_all_busses() (1) 236 237 #define PCIBIOS_MIN_IO 0x10 238 #define PCIBIOS_MIN_MEM 0x1000 /* NBPG - but pci/setup-res.c dies */ 239 240 /* export the pci_ DMA API in terms of the dma_ one */ 241 #include <asm-generic/pci-dma-compat.h> 242 243 #ifdef CONFIG_PCI 244 static inline void pci_dma_burst_advice(struct pci_dev *pdev, 245 enum pci_dma_burst_strategy *strat, 246 unsigned long *strategy_parameter) 247 { 248 unsigned long cacheline_size; 249 u8 byte; 250 251 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte); 252 if (byte == 0) 253 cacheline_size = 1024; 254 else 255 cacheline_size = (int) byte * 4; 256 257 *strat = PCI_DMA_BURST_MULTIPLE; 258 *strategy_parameter = cacheline_size; 259 } 260 #endif 261 262 extern void 263 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 264 struct resource *res); 265 266 extern void 267 pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, 268 struct pci_bus_region *region); 269 270 static inline void pcibios_penalize_isa_irq(int irq, int active) 271 { 272 /* We don't need to penalize isa irq's */ 273 } 274 275 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) 276 { 277 return channel ? 15 : 14; 278 } 279 280 #endif /* __ASM_PARISC_PCI_H */ 281