1 #ifndef __ASM_PARISC_PCI_H 2 #define __ASM_PARISC_PCI_H 3 4 #include <linux/scatterlist.h> 5 6 7 8 /* 9 ** HP PCI platforms generally support multiple bus adapters. 10 ** (workstations 1-~4, servers 2-~32) 11 ** 12 ** Newer platforms number the busses across PCI bus adapters *sparsely*. 13 ** E.g. 0, 8, 16, ... 14 ** 15 ** Under a PCI bus, most HP platforms support PPBs up to two or three 16 ** levels deep. See "Bit3" product line. 17 */ 18 #define PCI_MAX_BUSSES 256 19 20 21 /* To be used as: mdelay(pci_post_reset_delay); 22 * 23 * post_reset is the time the kernel should stall to prevent anyone from 24 * accessing the PCI bus once #RESET is de-asserted. 25 * PCI spec somewhere says 1 second but with multi-PCI bus systems, 26 * this makes the boot time much longer than necessary. 27 * 20ms seems to work for all the HP PCI implementations to date. 28 */ 29 #define pci_post_reset_delay 50 30 31 32 /* 33 ** pci_hba_data (aka H2P_OBJECT in HP/UX) 34 ** 35 ** This is the "common" or "base" data structure which HBA drivers 36 ** (eg Dino or LBA) are required to place at the top of their own 37 ** platform_data structure. I've heard this called "C inheritance" too. 38 ** 39 ** Data needed by pcibios layer belongs here. 40 */ 41 struct pci_hba_data { 42 void __iomem *base_addr; /* aka Host Physical Address */ 43 const struct parisc_device *dev; /* device from PA bus walk */ 44 struct pci_bus *hba_bus; /* primary PCI bus below HBA */ 45 int hba_num; /* I/O port space access "key" */ 46 struct resource bus_num; /* PCI bus numbers */ 47 struct resource io_space; /* PIOP */ 48 struct resource lmmio_space; /* bus addresses < 4Gb */ 49 struct resource elmmio_space; /* additional bus addresses < 4Gb */ 50 struct resource gmmio_space; /* bus addresses > 4Gb */ 51 52 /* NOTE: Dino code assumes it can use *all* of the lmmio_space, 53 * elmmio_space and gmmio_space as a contiguous array of 54 * resources. This #define represents the array size */ 55 #define DINO_MAX_LMMIO_RESOURCES 3 56 57 unsigned long lmmio_space_offset; /* CPU view - PCI view */ 58 void * iommu; /* IOMMU this device is under */ 59 /* REVISIT - spinlock to protect resources? */ 60 61 #define HBA_NAME_SIZE 16 62 char io_name[HBA_NAME_SIZE]; 63 char lmmio_name[HBA_NAME_SIZE]; 64 char elmmio_name[HBA_NAME_SIZE]; 65 char gmmio_name[HBA_NAME_SIZE]; 66 }; 67 68 #define HBA_DATA(d) ((struct pci_hba_data *) (d)) 69 70 /* 71 ** We support 2^16 I/O ports per HBA. These are set up in the form 72 ** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port 73 ** space address. 74 */ 75 #define HBA_PORT_SPACE_BITS 16 76 77 #define HBA_PORT_BASE(h) ((h) << HBA_PORT_SPACE_BITS) 78 #define HBA_PORT_SPACE_SIZE (1UL << HBA_PORT_SPACE_BITS) 79 80 #define PCI_PORT_HBA(a) ((a) >> HBA_PORT_SPACE_BITS) 81 #define PCI_PORT_ADDR(a) ((a) & (HBA_PORT_SPACE_SIZE - 1)) 82 83 #ifdef CONFIG_64BIT 84 #define PCI_F_EXTEND 0xffffffff00000000UL 85 #else /* !CONFIG_64BIT */ 86 #define PCI_F_EXTEND 0UL 87 #endif /* !CONFIG_64BIT */ 88 89 /* 90 ** KLUGE: linux/pci.h include asm/pci.h BEFORE declaring struct pci_bus 91 ** (This eliminates some of the warnings). 92 */ 93 struct pci_bus; 94 struct pci_dev; 95 96 /* 97 * If the PCI device's view of memory is the same as the CPU's view of memory, 98 * PCI_DMA_BUS_IS_PHYS is true. The networking and block device layers use 99 * this boolean for bounce buffer decisions. 100 */ 101 #ifdef CONFIG_PA20 102 /* All PA-2.0 machines have an IOMMU. */ 103 #define PCI_DMA_BUS_IS_PHYS 0 104 #define parisc_has_iommu() do { } while (0) 105 #else 106 107 #if defined(CONFIG_IOMMU_CCIO) || defined(CONFIG_IOMMU_SBA) 108 extern int parisc_bus_is_phys; /* in arch/parisc/kernel/setup.c */ 109 #define PCI_DMA_BUS_IS_PHYS parisc_bus_is_phys 110 #define parisc_has_iommu() do { parisc_bus_is_phys = 0; } while (0) 111 #else 112 #define PCI_DMA_BUS_IS_PHYS 1 113 #define parisc_has_iommu() do { } while (0) 114 #endif 115 116 #endif /* !CONFIG_PA20 */ 117 118 119 /* 120 ** Most PCI devices (eg Tulip, NCR720) also export the same registers 121 ** to both MMIO and I/O port space. Due to poor performance of I/O Port 122 ** access under HP PCI bus adapters, strongly recommend the use of MMIO 123 ** address space. 124 ** 125 ** While I'm at it more PA programming notes: 126 ** 127 ** 1) MMIO stores (writes) are posted operations. This means the processor 128 ** gets an "ACK" before the write actually gets to the device. A read 129 ** to the same device (or typically the bus adapter above it) will 130 ** force in-flight write transaction(s) out to the targeted device 131 ** before the read can complete. 132 ** 133 ** 2) The Programmed I/O (PIO) data may not always be strongly ordered with 134 ** respect to DMA on all platforms. Ie PIO data can reach the processor 135 ** before in-flight DMA reaches memory. Since most SMP PA platforms 136 ** are I/O coherent, it generally doesn't matter...but sometimes 137 ** it does. 138 ** 139 ** I've helped device driver writers debug both types of problems. 140 */ 141 struct pci_port_ops { 142 u8 (*inb) (struct pci_hba_data *hba, u16 port); 143 u16 (*inw) (struct pci_hba_data *hba, u16 port); 144 u32 (*inl) (struct pci_hba_data *hba, u16 port); 145 void (*outb) (struct pci_hba_data *hba, u16 port, u8 data); 146 void (*outw) (struct pci_hba_data *hba, u16 port, u16 data); 147 void (*outl) (struct pci_hba_data *hba, u16 port, u32 data); 148 }; 149 150 151 struct pci_bios_ops { 152 void (*init)(void); 153 void (*fixup_bus)(struct pci_bus *bus); 154 }; 155 156 /* 157 ** Stuff declared in arch/parisc/kernel/pci.c 158 */ 159 extern struct pci_port_ops *pci_port; 160 extern struct pci_bios_ops *pci_bios; 161 162 #ifdef CONFIG_PCI 163 extern void pcibios_register_hba(struct pci_hba_data *); 164 extern void pcibios_set_master(struct pci_dev *); 165 #else 166 static inline void pcibios_register_hba(struct pci_hba_data *x) 167 { 168 } 169 #endif 170 extern void pcibios_init_bridge(struct pci_dev *); 171 172 /* 173 * pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus() 174 * 0 == check if bridge is numbered before re-numbering. 175 * 1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges. 176 * 177 * We *should* set this to zero for "legacy" platforms and one 178 * for PAT platforms. 179 * 180 * But legacy platforms also need to renumber the busses below a Host 181 * Bus controller. Adding a 4-port Tulip card on the first PCI root 182 * bus of a C200 resulted in the secondary bus being numbered as 1. 183 * The second PCI host bus controller's root bus had already been 184 * assigned bus number 1 by firmware and sysfs complained. 185 * 186 * Firmware isn't doing anything wrong here since each controller 187 * is its own PCI domain. It's simpler and easier for us to renumber 188 * the busses rather than treat each Dino as a separate PCI domain. 189 * Eventually, we may want to introduce PCI domains for Superdome or 190 * rp7420/8420 boxes and then revisit this issue. 191 */ 192 #define pcibios_assign_all_busses() (1) 193 194 #define PCIBIOS_MIN_IO 0x10 195 #define PCIBIOS_MIN_MEM 0x1000 /* NBPG - but pci/setup-res.c dies */ 196 197 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) 198 { 199 return channel ? 15 : 14; 200 } 201 202 #define HAVE_PCI_MMAP 203 #define ARCH_GENERIC_PCI_MMAP_RESOURCE 204 205 #endif /* __ASM_PARISC_PCI_H */ 206