1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ASM_PARISC_PCI_H 3 #define __ASM_PARISC_PCI_H 4 5 #include <linux/scatterlist.h> 6 7 8 9 /* 10 ** HP PCI platforms generally support multiple bus adapters. 11 ** (workstations 1-~4, servers 2-~32) 12 ** 13 ** Newer platforms number the busses across PCI bus adapters *sparsely*. 14 ** E.g. 0, 8, 16, ... 15 ** 16 ** Under a PCI bus, most HP platforms support PPBs up to two or three 17 ** levels deep. See "Bit3" product line. 18 */ 19 #define PCI_MAX_BUSSES 256 20 21 22 /* To be used as: mdelay(pci_post_reset_delay); 23 * 24 * post_reset is the time the kernel should stall to prevent anyone from 25 * accessing the PCI bus once #RESET is de-asserted. 26 * PCI spec somewhere says 1 second but with multi-PCI bus systems, 27 * this makes the boot time much longer than necessary. 28 * 20ms seems to work for all the HP PCI implementations to date. 29 */ 30 #define pci_post_reset_delay 50 31 32 33 /* 34 ** pci_hba_data (aka H2P_OBJECT in HP/UX) 35 ** 36 ** This is the "common" or "base" data structure which HBA drivers 37 ** (eg Dino or LBA) are required to place at the top of their own 38 ** platform_data structure. I've heard this called "C inheritance" too. 39 ** 40 ** Data needed by pcibios layer belongs here. 41 */ 42 struct pci_hba_data { 43 void __iomem *base_addr; /* aka Host Physical Address */ 44 const struct parisc_device *dev; /* device from PA bus walk */ 45 struct pci_bus *hba_bus; /* primary PCI bus below HBA */ 46 int hba_num; /* I/O port space access "key" */ 47 struct resource bus_num; /* PCI bus numbers */ 48 struct resource io_space; /* PIOP */ 49 struct resource lmmio_space; /* bus addresses < 4Gb */ 50 struct resource elmmio_space; /* additional bus addresses < 4Gb */ 51 struct resource gmmio_space; /* bus addresses > 4Gb */ 52 53 /* NOTE: Dino code assumes it can use *all* of the lmmio_space, 54 * elmmio_space and gmmio_space as a contiguous array of 55 * resources. This #define represents the array size */ 56 #define DINO_MAX_LMMIO_RESOURCES 3 57 58 unsigned long lmmio_space_offset; /* CPU view - PCI view */ 59 void * iommu; /* IOMMU this device is under */ 60 /* REVISIT - spinlock to protect resources? */ 61 62 #define HBA_NAME_SIZE 16 63 char io_name[HBA_NAME_SIZE]; 64 char lmmio_name[HBA_NAME_SIZE]; 65 char elmmio_name[HBA_NAME_SIZE]; 66 char gmmio_name[HBA_NAME_SIZE]; 67 }; 68 69 #define HBA_DATA(d) ((struct pci_hba_data *) (d)) 70 71 /* 72 ** We support 2^16 I/O ports per HBA. These are set up in the form 73 ** 0xbbxxxx, where bb is the bus number and xxxx is the I/O port 74 ** space address. 75 */ 76 #define HBA_PORT_SPACE_BITS 16 77 78 #define HBA_PORT_BASE(h) ((h) << HBA_PORT_SPACE_BITS) 79 #define HBA_PORT_SPACE_SIZE (1UL << HBA_PORT_SPACE_BITS) 80 81 #define PCI_PORT_HBA(a) ((a) >> HBA_PORT_SPACE_BITS) 82 #define PCI_PORT_ADDR(a) ((a) & (HBA_PORT_SPACE_SIZE - 1)) 83 84 #ifdef CONFIG_64BIT 85 #define PCI_F_EXTEND 0xffffffff00000000UL 86 #else /* !CONFIG_64BIT */ 87 #define PCI_F_EXTEND 0UL 88 #endif /* !CONFIG_64BIT */ 89 90 /* 91 * If the PCI device's view of memory is the same as the CPU's view of memory, 92 * PCI_DMA_BUS_IS_PHYS is true. The networking and block device layers use 93 * this boolean for bounce buffer decisions. 94 */ 95 #ifdef CONFIG_PA20 96 /* All PA-2.0 machines have an IOMMU. */ 97 #define PCI_DMA_BUS_IS_PHYS 0 98 #define parisc_has_iommu() do { } while (0) 99 #else 100 101 #if defined(CONFIG_IOMMU_CCIO) || defined(CONFIG_IOMMU_SBA) 102 extern int parisc_bus_is_phys; /* in arch/parisc/kernel/setup.c */ 103 #define PCI_DMA_BUS_IS_PHYS parisc_bus_is_phys 104 #define parisc_has_iommu() do { parisc_bus_is_phys = 0; } while (0) 105 #else 106 #define PCI_DMA_BUS_IS_PHYS 1 107 #define parisc_has_iommu() do { } while (0) 108 #endif 109 110 #endif /* !CONFIG_PA20 */ 111 112 113 /* 114 ** Most PCI devices (eg Tulip, NCR720) also export the same registers 115 ** to both MMIO and I/O port space. Due to poor performance of I/O Port 116 ** access under HP PCI bus adapters, strongly recommend the use of MMIO 117 ** address space. 118 ** 119 ** While I'm at it more PA programming notes: 120 ** 121 ** 1) MMIO stores (writes) are posted operations. This means the processor 122 ** gets an "ACK" before the write actually gets to the device. A read 123 ** to the same device (or typically the bus adapter above it) will 124 ** force in-flight write transaction(s) out to the targeted device 125 ** before the read can complete. 126 ** 127 ** 2) The Programmed I/O (PIO) data may not always be strongly ordered with 128 ** respect to DMA on all platforms. Ie PIO data can reach the processor 129 ** before in-flight DMA reaches memory. Since most SMP PA platforms 130 ** are I/O coherent, it generally doesn't matter...but sometimes 131 ** it does. 132 ** 133 ** I've helped device driver writers debug both types of problems. 134 */ 135 struct pci_port_ops { 136 u8 (*inb) (struct pci_hba_data *hba, u16 port); 137 u16 (*inw) (struct pci_hba_data *hba, u16 port); 138 u32 (*inl) (struct pci_hba_data *hba, u16 port); 139 void (*outb) (struct pci_hba_data *hba, u16 port, u8 data); 140 void (*outw) (struct pci_hba_data *hba, u16 port, u16 data); 141 void (*outl) (struct pci_hba_data *hba, u16 port, u32 data); 142 }; 143 144 145 struct pci_bios_ops { 146 void (*init)(void); 147 void (*fixup_bus)(struct pci_bus *bus); 148 }; 149 150 /* 151 ** Stuff declared in arch/parisc/kernel/pci.c 152 */ 153 extern struct pci_port_ops *pci_port; 154 extern struct pci_bios_ops *pci_bios; 155 156 #ifdef CONFIG_PCI 157 extern void pcibios_register_hba(struct pci_hba_data *); 158 #else 159 static inline void pcibios_register_hba(struct pci_hba_data *x) 160 { 161 } 162 #endif 163 extern void pcibios_init_bridge(struct pci_dev *); 164 165 /* 166 * pcibios_assign_all_busses() is used in drivers/pci/pci.c:pci_do_scan_bus() 167 * 0 == check if bridge is numbered before re-numbering. 168 * 1 == pci_do_scan_bus() should automatically number all PCI-PCI bridges. 169 * 170 * We *should* set this to zero for "legacy" platforms and one 171 * for PAT platforms. 172 * 173 * But legacy platforms also need to renumber the busses below a Host 174 * Bus controller. Adding a 4-port Tulip card on the first PCI root 175 * bus of a C200 resulted in the secondary bus being numbered as 1. 176 * The second PCI host bus controller's root bus had already been 177 * assigned bus number 1 by firmware and sysfs complained. 178 * 179 * Firmware isn't doing anything wrong here since each controller 180 * is its own PCI domain. It's simpler and easier for us to renumber 181 * the busses rather than treat each Dino as a separate PCI domain. 182 * Eventually, we may want to introduce PCI domains for Superdome or 183 * rp7420/8420 boxes and then revisit this issue. 184 */ 185 #define pcibios_assign_all_busses() (1) 186 187 #define PCIBIOS_MIN_IO 0x10 188 #define PCIBIOS_MIN_MEM 0x1000 /* NBPG - but pci/setup-res.c dies */ 189 190 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) 191 { 192 return channel ? 15 : 14; 193 } 194 195 #define HAVE_PCI_MMAP 196 #define ARCH_GENERIC_PCI_MMAP_RESOURCE 197 198 #endif /* __ASM_PARISC_PCI_H */ 199