1 #ifndef _PARISC_DMA_MAPPING_H 2 #define _PARISC_DMA_MAPPING_H 3 4 #include <asm/cacheflush.h> 5 6 /* 7 ** We need to support 4 different coherent dma models with one binary: 8 ** 9 ** I/O MMU consistent method dma_sync behavior 10 ** ============= ====================== ======================= 11 ** a) PA-7x00LC uncachable host memory flush/purge 12 ** b) U2/Uturn cachable host memory NOP 13 ** c) Ike/Astro cachable host memory NOP 14 ** d) EPIC/SAGA memory on EPIC/SAGA flush/reset DMA channel 15 ** 16 ** PA-7[13]00LC processors have a GSC bus interface and no I/O MMU. 17 ** 18 ** Systems (eg PCX-T workstations) that don't fall into the above 19 ** categories will need to modify the needed drivers to perform 20 ** flush/purge and allocate "regular" cacheable pages for everything. 21 */ 22 23 #ifdef CONFIG_PA11 24 extern struct dma_map_ops pcxl_dma_ops; 25 extern struct dma_map_ops pcx_dma_ops; 26 #endif 27 28 extern struct dma_map_ops *hppa_dma_ops; 29 30 static inline struct dma_map_ops *get_dma_ops(struct device *dev) 31 { 32 return hppa_dma_ops; 33 } 34 35 static inline void 36 dma_cache_sync(struct device *dev, void *vaddr, size_t size, 37 enum dma_data_direction direction) 38 { 39 if (hppa_dma_ops->sync_single_for_cpu) 40 flush_kernel_dcache_range((unsigned long)vaddr, size); 41 } 42 43 static inline void * 44 parisc_walk_tree(struct device *dev) 45 { 46 struct device *otherdev; 47 if(likely(dev->platform_data != NULL)) 48 return dev->platform_data; 49 /* OK, just traverse the bus to find it */ 50 for(otherdev = dev->parent; otherdev; 51 otherdev = otherdev->parent) { 52 if(otherdev->platform_data) { 53 dev->platform_data = otherdev->platform_data; 54 break; 55 } 56 } 57 BUG_ON(!dev->platform_data); 58 return dev->platform_data; 59 } 60 61 #define GET_IOC(dev) (HBA_DATA(parisc_walk_tree(dev))->iommu) 62 63 64 #ifdef CONFIG_IOMMU_CCIO 65 struct parisc_device; 66 struct ioc; 67 void * ccio_get_iommu(const struct parisc_device *dev); 68 int ccio_request_resource(const struct parisc_device *dev, 69 struct resource *res); 70 int ccio_allocate_resource(const struct parisc_device *dev, 71 struct resource *res, unsigned long size, 72 unsigned long min, unsigned long max, unsigned long align); 73 #else /* !CONFIG_IOMMU_CCIO */ 74 #define ccio_get_iommu(dev) NULL 75 #define ccio_request_resource(dev, res) insert_resource(&iomem_resource, res) 76 #define ccio_allocate_resource(dev, res, size, min, max, align) \ 77 allocate_resource(&iomem_resource, res, size, min, max, \ 78 align, NULL, NULL) 79 #endif /* !CONFIG_IOMMU_CCIO */ 80 81 #ifdef CONFIG_IOMMU_SBA 82 struct parisc_device; 83 void * sba_get_iommu(struct parisc_device *dev); 84 #endif 85 86 #endif 87