1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * include/asm-parisc/cache.h 4 */ 5 6 #ifndef __ARCH_PARISC_CACHE_H 7 #define __ARCH_PARISC_CACHE_H 8 9 10 /* 11 * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors 12 * have 32-byte cachelines. The L1 length appears to be 16 bytes but this 13 * is not clearly documented. 14 */ 15 #define L1_CACHE_BYTES 16 16 #define L1_CACHE_SHIFT 4 17 18 #ifndef __ASSEMBLY__ 19 20 #define SMP_CACHE_BYTES L1_CACHE_BYTES 21 22 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES 23 24 #define __read_mostly __attribute__((__section__(".data..read_mostly"))) 25 26 /* Read-only memory is marked before mark_rodata_ro() is called. */ 27 #define __ro_after_init __read_mostly 28 29 void parisc_cache_init(void); /* initializes cache-flushing */ 30 void disable_sr_hashing_asm(int); /* low level support for above */ 31 void disable_sr_hashing(void); /* turns off space register hashing */ 32 void free_sid(unsigned long); 33 unsigned long alloc_sid(void); 34 35 struct seq_file; 36 extern void show_cache_info(struct seq_file *m); 37 38 extern int split_tlb; 39 extern int dcache_stride; 40 extern int icache_stride; 41 extern struct pdc_cache_info cache_info; 42 void parisc_setup_cache_timing(void); 43 44 #define pdtlb(addr) asm volatile("pdtlb 0(%%sr1,%0)" : : "r" (addr)); 45 #define pitlb(addr) asm volatile("pitlb 0(%%sr1,%0)" : : "r" (addr)); 46 #define pdtlb_kernel(addr) asm volatile("pdtlb 0(%0)" : : "r" (addr)); 47 48 #endif /* ! __ASSEMBLY__ */ 49 50 /* Classes of processor wrt: disabling space register hashing */ 51 52 #define SRHASH_PCXST 0 /* pcxs, pcxt, pcxt_ */ 53 #define SRHASH_PCXL 1 /* pcxl */ 54 #define SRHASH_PA20 2 /* pcxu, pcxu_, pcxw, pcxw_ */ 55 56 #endif 57