1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand) 4 * Copyright (C) 1999 Philipp Rumpf <prumpf@tux.org> 5 * Copyright (C) 1999 SuSE GmbH 6 */ 7 8 #ifndef _PARISC_ASSEMBLY_H 9 #define _PARISC_ASSEMBLY_H 10 11 #define CALLEE_FLOAT_FRAME_SIZE 80 12 13 #ifdef CONFIG_64BIT 14 #define LDREG ldd 15 #define STREG std 16 #define LDREGX ldd,s 17 #define LDREGM ldd,mb 18 #define STREGM std,ma 19 #define SHRREG shrd 20 #define SHLREG shld 21 #define ANDCM andcm,* 22 #define COND(x) * ## x 23 #define RP_OFFSET 16 24 #define FRAME_SIZE 128 25 #define CALLEE_REG_FRAME_SIZE 144 26 #define REG_SZ 8 27 #define ASM_ULONG_INSN .dword 28 #else /* CONFIG_64BIT */ 29 #define LDREG ldw 30 #define STREG stw 31 #define LDREGX ldwx,s 32 #define LDREGM ldwm 33 #define STREGM stwm 34 #define SHRREG shr 35 #define SHLREG shlw 36 #define ANDCM andcm 37 #define COND(x) x 38 #define RP_OFFSET 20 39 #define FRAME_SIZE 64 40 #define CALLEE_REG_FRAME_SIZE 128 41 #define REG_SZ 4 42 #define ASM_ULONG_INSN .word 43 #endif 44 45 #define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE) 46 47 #ifdef CONFIG_PA20 48 #define LDCW ldcw,co 49 #define BL b,l 50 # ifdef CONFIG_64BIT 51 # define PA_ASM_LEVEL 2.0w 52 # else 53 # define PA_ASM_LEVEL 2.0 54 # endif 55 #else 56 #define LDCW ldcw 57 #define BL bl 58 #define PA_ASM_LEVEL 1.1 59 #endif 60 61 #ifdef __ASSEMBLY__ 62 63 #ifdef CONFIG_64BIT 64 /* the 64-bit pa gnu assembler unfortunately defaults to .level 1.1 or 2.0 so 65 * work around that for now... */ 66 .level 2.0w 67 #endif 68 69 #include <asm/asm-offsets.h> 70 #include <asm/page.h> 71 #include <asm/types.h> 72 73 #include <asm/asmregs.h> 74 75 sp = 30 76 gp = 27 77 ipsw = 22 78 79 /* 80 * We provide two versions of each macro to convert from physical 81 * to virtual and vice versa. The "_r1" versions take one argument 82 * register, but trashes r1 to do the conversion. The other 83 * version takes two arguments: a src and destination register. 84 * However, the source and destination registers can not be 85 * the same register. 86 */ 87 88 .macro tophys grvirt, grphys 89 ldil L%(__PAGE_OFFSET), \grphys 90 sub \grvirt, \grphys, \grphys 91 .endm 92 93 .macro tovirt grphys, grvirt 94 ldil L%(__PAGE_OFFSET), \grvirt 95 add \grphys, \grvirt, \grvirt 96 .endm 97 98 .macro tophys_r1 gr 99 ldil L%(__PAGE_OFFSET), %r1 100 sub \gr, %r1, \gr 101 .endm 102 103 .macro tovirt_r1 gr 104 ldil L%(__PAGE_OFFSET), %r1 105 add \gr, %r1, \gr 106 .endm 107 108 .macro delay value 109 ldil L%\value, 1 110 ldo R%\value(1), 1 111 addib,UV,n -1,1,. 112 addib,NUV,n -1,1,.+8 113 nop 114 .endm 115 116 .macro debug value 117 .endm 118 119 .macro shlw r, sa, t 120 zdep \r, 31-(\sa), 32-(\sa), \t 121 .endm 122 123 /* And the PA 2.0W shift left */ 124 .macro shld r, sa, t 125 depd,z \r, 63-(\sa), 64-(\sa), \t 126 .endm 127 128 /* Shift Right - note the r and t can NOT be the same! */ 129 .macro shr r, sa, t 130 extru \r, 31-(\sa), 32-(\sa), \t 131 .endm 132 133 /* pa20w version of shift right */ 134 .macro shrd r, sa, t 135 extrd,u \r, 63-(\sa), 64-(\sa), \t 136 .endm 137 138 /* load 32-bit 'value' into 'reg' compensating for the ldil 139 * sign-extension when running in wide mode. 140 * WARNING!! neither 'value' nor 'reg' can be expressions 141 * containing '.'!!!! */ 142 .macro load32 value, reg 143 ldil L%\value, \reg 144 ldo R%\value(\reg), \reg 145 .endm 146 147 .macro loadgp 148 #ifdef CONFIG_64BIT 149 ldil L%__gp, %r27 150 ldo R%__gp(%r27), %r27 151 #else 152 ldil L%$global$, %r27 153 ldo R%$global$(%r27), %r27 154 #endif 155 .endm 156 157 #define SAVE_SP(r, where) mfsp r, %r1 ! STREG %r1, where 158 #define REST_SP(r, where) LDREG where, %r1 ! mtsp %r1, r 159 #define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where 160 #define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r 161 162 .macro save_general regs 163 STREG %r1, PT_GR1 (\regs) 164 STREG %r2, PT_GR2 (\regs) 165 STREG %r3, PT_GR3 (\regs) 166 STREG %r4, PT_GR4 (\regs) 167 STREG %r5, PT_GR5 (\regs) 168 STREG %r6, PT_GR6 (\regs) 169 STREG %r7, PT_GR7 (\regs) 170 STREG %r8, PT_GR8 (\regs) 171 STREG %r9, PT_GR9 (\regs) 172 STREG %r10, PT_GR10(\regs) 173 STREG %r11, PT_GR11(\regs) 174 STREG %r12, PT_GR12(\regs) 175 STREG %r13, PT_GR13(\regs) 176 STREG %r14, PT_GR14(\regs) 177 STREG %r15, PT_GR15(\regs) 178 STREG %r16, PT_GR16(\regs) 179 STREG %r17, PT_GR17(\regs) 180 STREG %r18, PT_GR18(\regs) 181 STREG %r19, PT_GR19(\regs) 182 STREG %r20, PT_GR20(\regs) 183 STREG %r21, PT_GR21(\regs) 184 STREG %r22, PT_GR22(\regs) 185 STREG %r23, PT_GR23(\regs) 186 STREG %r24, PT_GR24(\regs) 187 STREG %r25, PT_GR25(\regs) 188 /* r26 is saved in get_stack and used to preserve a value across virt_map */ 189 STREG %r27, PT_GR27(\regs) 190 STREG %r28, PT_GR28(\regs) 191 /* r29 is saved in get_stack and used to point to saved registers */ 192 /* r30 stack pointer saved in get_stack */ 193 STREG %r31, PT_GR31(\regs) 194 .endm 195 196 .macro rest_general regs 197 /* r1 used as a temp in rest_stack and is restored there */ 198 LDREG PT_GR2 (\regs), %r2 199 LDREG PT_GR3 (\regs), %r3 200 LDREG PT_GR4 (\regs), %r4 201 LDREG PT_GR5 (\regs), %r5 202 LDREG PT_GR6 (\regs), %r6 203 LDREG PT_GR7 (\regs), %r7 204 LDREG PT_GR8 (\regs), %r8 205 LDREG PT_GR9 (\regs), %r9 206 LDREG PT_GR10(\regs), %r10 207 LDREG PT_GR11(\regs), %r11 208 LDREG PT_GR12(\regs), %r12 209 LDREG PT_GR13(\regs), %r13 210 LDREG PT_GR14(\regs), %r14 211 LDREG PT_GR15(\regs), %r15 212 LDREG PT_GR16(\regs), %r16 213 LDREG PT_GR17(\regs), %r17 214 LDREG PT_GR18(\regs), %r18 215 LDREG PT_GR19(\regs), %r19 216 LDREG PT_GR20(\regs), %r20 217 LDREG PT_GR21(\regs), %r21 218 LDREG PT_GR22(\regs), %r22 219 LDREG PT_GR23(\regs), %r23 220 LDREG PT_GR24(\regs), %r24 221 LDREG PT_GR25(\regs), %r25 222 LDREG PT_GR26(\regs), %r26 223 LDREG PT_GR27(\regs), %r27 224 LDREG PT_GR28(\regs), %r28 225 /* r29 points to register save area, and is restored in rest_stack */ 226 /* r30 stack pointer restored in rest_stack */ 227 LDREG PT_GR31(\regs), %r31 228 .endm 229 230 .macro save_fp regs 231 fstd,ma %fr0, 8(\regs) 232 fstd,ma %fr1, 8(\regs) 233 fstd,ma %fr2, 8(\regs) 234 fstd,ma %fr3, 8(\regs) 235 fstd,ma %fr4, 8(\regs) 236 fstd,ma %fr5, 8(\regs) 237 fstd,ma %fr6, 8(\regs) 238 fstd,ma %fr7, 8(\regs) 239 fstd,ma %fr8, 8(\regs) 240 fstd,ma %fr9, 8(\regs) 241 fstd,ma %fr10, 8(\regs) 242 fstd,ma %fr11, 8(\regs) 243 fstd,ma %fr12, 8(\regs) 244 fstd,ma %fr13, 8(\regs) 245 fstd,ma %fr14, 8(\regs) 246 fstd,ma %fr15, 8(\regs) 247 fstd,ma %fr16, 8(\regs) 248 fstd,ma %fr17, 8(\regs) 249 fstd,ma %fr18, 8(\regs) 250 fstd,ma %fr19, 8(\regs) 251 fstd,ma %fr20, 8(\regs) 252 fstd,ma %fr21, 8(\regs) 253 fstd,ma %fr22, 8(\regs) 254 fstd,ma %fr23, 8(\regs) 255 fstd,ma %fr24, 8(\regs) 256 fstd,ma %fr25, 8(\regs) 257 fstd,ma %fr26, 8(\regs) 258 fstd,ma %fr27, 8(\regs) 259 fstd,ma %fr28, 8(\regs) 260 fstd,ma %fr29, 8(\regs) 261 fstd,ma %fr30, 8(\regs) 262 fstd %fr31, 0(\regs) 263 .endm 264 265 .macro rest_fp regs 266 fldd 0(\regs), %fr31 267 fldd,mb -8(\regs), %fr30 268 fldd,mb -8(\regs), %fr29 269 fldd,mb -8(\regs), %fr28 270 fldd,mb -8(\regs), %fr27 271 fldd,mb -8(\regs), %fr26 272 fldd,mb -8(\regs), %fr25 273 fldd,mb -8(\regs), %fr24 274 fldd,mb -8(\regs), %fr23 275 fldd,mb -8(\regs), %fr22 276 fldd,mb -8(\regs), %fr21 277 fldd,mb -8(\regs), %fr20 278 fldd,mb -8(\regs), %fr19 279 fldd,mb -8(\regs), %fr18 280 fldd,mb -8(\regs), %fr17 281 fldd,mb -8(\regs), %fr16 282 fldd,mb -8(\regs), %fr15 283 fldd,mb -8(\regs), %fr14 284 fldd,mb -8(\regs), %fr13 285 fldd,mb -8(\regs), %fr12 286 fldd,mb -8(\regs), %fr11 287 fldd,mb -8(\regs), %fr10 288 fldd,mb -8(\regs), %fr9 289 fldd,mb -8(\regs), %fr8 290 fldd,mb -8(\regs), %fr7 291 fldd,mb -8(\regs), %fr6 292 fldd,mb -8(\regs), %fr5 293 fldd,mb -8(\regs), %fr4 294 fldd,mb -8(\regs), %fr3 295 fldd,mb -8(\regs), %fr2 296 fldd,mb -8(\regs), %fr1 297 fldd,mb -8(\regs), %fr0 298 .endm 299 300 .macro callee_save_float 301 fstd,ma %fr12, 8(%r30) 302 fstd,ma %fr13, 8(%r30) 303 fstd,ma %fr14, 8(%r30) 304 fstd,ma %fr15, 8(%r30) 305 fstd,ma %fr16, 8(%r30) 306 fstd,ma %fr17, 8(%r30) 307 fstd,ma %fr18, 8(%r30) 308 fstd,ma %fr19, 8(%r30) 309 fstd,ma %fr20, 8(%r30) 310 fstd,ma %fr21, 8(%r30) 311 .endm 312 313 .macro callee_rest_float 314 fldd,mb -8(%r30), %fr21 315 fldd,mb -8(%r30), %fr20 316 fldd,mb -8(%r30), %fr19 317 fldd,mb -8(%r30), %fr18 318 fldd,mb -8(%r30), %fr17 319 fldd,mb -8(%r30), %fr16 320 fldd,mb -8(%r30), %fr15 321 fldd,mb -8(%r30), %fr14 322 fldd,mb -8(%r30), %fr13 323 fldd,mb -8(%r30), %fr12 324 .endm 325 326 #ifdef CONFIG_64BIT 327 .macro callee_save 328 std,ma %r3, CALLEE_REG_FRAME_SIZE(%r30) 329 mfctl %cr27, %r3 330 std %r4, -136(%r30) 331 std %r5, -128(%r30) 332 std %r6, -120(%r30) 333 std %r7, -112(%r30) 334 std %r8, -104(%r30) 335 std %r9, -96(%r30) 336 std %r10, -88(%r30) 337 std %r11, -80(%r30) 338 std %r12, -72(%r30) 339 std %r13, -64(%r30) 340 std %r14, -56(%r30) 341 std %r15, -48(%r30) 342 std %r16, -40(%r30) 343 std %r17, -32(%r30) 344 std %r18, -24(%r30) 345 std %r3, -16(%r30) 346 .endm 347 348 .macro callee_rest 349 ldd -16(%r30), %r3 350 ldd -24(%r30), %r18 351 ldd -32(%r30), %r17 352 ldd -40(%r30), %r16 353 ldd -48(%r30), %r15 354 ldd -56(%r30), %r14 355 ldd -64(%r30), %r13 356 ldd -72(%r30), %r12 357 ldd -80(%r30), %r11 358 ldd -88(%r30), %r10 359 ldd -96(%r30), %r9 360 ldd -104(%r30), %r8 361 ldd -112(%r30), %r7 362 ldd -120(%r30), %r6 363 ldd -128(%r30), %r5 364 ldd -136(%r30), %r4 365 mtctl %r3, %cr27 366 ldd,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3 367 .endm 368 369 #else /* ! CONFIG_64BIT */ 370 371 .macro callee_save 372 stw,ma %r3, CALLEE_REG_FRAME_SIZE(%r30) 373 mfctl %cr27, %r3 374 stw %r4, -124(%r30) 375 stw %r5, -120(%r30) 376 stw %r6, -116(%r30) 377 stw %r7, -112(%r30) 378 stw %r8, -108(%r30) 379 stw %r9, -104(%r30) 380 stw %r10, -100(%r30) 381 stw %r11, -96(%r30) 382 stw %r12, -92(%r30) 383 stw %r13, -88(%r30) 384 stw %r14, -84(%r30) 385 stw %r15, -80(%r30) 386 stw %r16, -76(%r30) 387 stw %r17, -72(%r30) 388 stw %r18, -68(%r30) 389 stw %r3, -64(%r30) 390 .endm 391 392 .macro callee_rest 393 ldw -64(%r30), %r3 394 ldw -68(%r30), %r18 395 ldw -72(%r30), %r17 396 ldw -76(%r30), %r16 397 ldw -80(%r30), %r15 398 ldw -84(%r30), %r14 399 ldw -88(%r30), %r13 400 ldw -92(%r30), %r12 401 ldw -96(%r30), %r11 402 ldw -100(%r30), %r10 403 ldw -104(%r30), %r9 404 ldw -108(%r30), %r8 405 ldw -112(%r30), %r7 406 ldw -116(%r30), %r6 407 ldw -120(%r30), %r5 408 ldw -124(%r30), %r4 409 mtctl %r3, %cr27 410 ldw,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3 411 .endm 412 #endif /* ! CONFIG_64BIT */ 413 414 .macro save_specials regs 415 416 SAVE_SP (%sr0, PT_SR0 (\regs)) 417 SAVE_SP (%sr1, PT_SR1 (\regs)) 418 SAVE_SP (%sr2, PT_SR2 (\regs)) 419 SAVE_SP (%sr3, PT_SR3 (\regs)) 420 SAVE_SP (%sr4, PT_SR4 (\regs)) 421 SAVE_SP (%sr5, PT_SR5 (\regs)) 422 SAVE_SP (%sr6, PT_SR6 (\regs)) 423 424 SAVE_CR (%cr17, PT_IASQ0(\regs)) 425 mtctl %r0, %cr17 426 SAVE_CR (%cr17, PT_IASQ1(\regs)) 427 428 SAVE_CR (%cr18, PT_IAOQ0(\regs)) 429 mtctl %r0, %cr18 430 SAVE_CR (%cr18, PT_IAOQ1(\regs)) 431 432 #ifdef CONFIG_64BIT 433 /* cr11 (sar) is a funny one. 5 bits on PA1.1 and 6 bit on PA2.0 434 * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only 435 * reads 5 bits. Use mfctl,w to read all six bits. Otherwise 436 * we lose the 6th bit on a save/restore over interrupt. 437 */ 438 mfctl,w %cr11, %r1 439 STREG %r1, PT_SAR (\regs) 440 #else 441 SAVE_CR (%cr11, PT_SAR (\regs)) 442 #endif 443 SAVE_CR (%cr19, PT_IIR (\regs)) 444 445 /* 446 * Code immediately following this macro (in intr_save) relies 447 * on r8 containing ipsw. 448 */ 449 mfctl %cr22, %r8 450 STREG %r8, PT_PSW(\regs) 451 .endm 452 453 .macro rest_specials regs 454 455 REST_SP (%sr0, PT_SR0 (\regs)) 456 REST_SP (%sr1, PT_SR1 (\regs)) 457 REST_SP (%sr2, PT_SR2 (\regs)) 458 REST_SP (%sr3, PT_SR3 (\regs)) 459 REST_SP (%sr4, PT_SR4 (\regs)) 460 REST_SP (%sr5, PT_SR5 (\regs)) 461 REST_SP (%sr6, PT_SR6 (\regs)) 462 REST_SP (%sr7, PT_SR7 (\regs)) 463 464 REST_CR (%cr17, PT_IASQ0(\regs)) 465 REST_CR (%cr17, PT_IASQ1(\regs)) 466 467 REST_CR (%cr18, PT_IAOQ0(\regs)) 468 REST_CR (%cr18, PT_IAOQ1(\regs)) 469 470 REST_CR (%cr11, PT_SAR (\regs)) 471 472 REST_CR (%cr22, PT_PSW (\regs)) 473 .endm 474 475 476 /* First step to create a "relied upon translation" 477 * See PA 2.0 Arch. page F-4 and F-5. 478 * 479 * The ssm was originally necessary due to a "PCxT bug". 480 * But someone decided it needed to be added to the architecture 481 * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual. 482 * It's been carried forward into PA 2.0 Arch as well. :^( 483 * 484 * "ssm 0,%r0" is a NOP with side effects (prefetch barrier). 485 * rsm/ssm prevents the ifetch unit from speculatively fetching 486 * instructions past this line in the code stream. 487 * PA 2.0 processor will single step all insn in the same QUAD (4 insn). 488 */ 489 .macro pcxt_ssm_bug 490 rsm PSW_SM_I,%r0 491 nop /* 1 */ 492 nop /* 2 */ 493 nop /* 3 */ 494 nop /* 4 */ 495 nop /* 5 */ 496 nop /* 6 */ 497 nop /* 7 */ 498 .endm 499 500 /* 501 * ASM_EXCEPTIONTABLE_ENTRY 502 * 503 * Creates an exception table entry. 504 * Do not convert to a assembler macro. This won't work. 505 */ 506 #define ASM_EXCEPTIONTABLE_ENTRY(fault_addr, except_addr) \ 507 .section __ex_table,"aw" ! \ 508 .word (fault_addr - .), (except_addr - .) ! \ 509 .previous 510 511 512 #endif /* __ASSEMBLY__ */ 513 #endif 514