1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand) 4 * Copyright (C) 1999 Philipp Rumpf <prumpf@tux.org> 5 * Copyright (C) 1999 SuSE GmbH 6 * Copyright (C) 2021 Helge Deller <deller@gmx.de> 7 */ 8 9 #ifndef _PARISC_ASSEMBLY_H 10 #define _PARISC_ASSEMBLY_H 11 12 #ifdef CONFIG_64BIT 13 #define RP_OFFSET 16 14 #define FRAME_SIZE 128 15 #define CALLEE_REG_FRAME_SIZE 144 16 #define REG_SZ 8 17 #define ASM_ULONG_INSN .dword 18 #else /* CONFIG_64BIT */ 19 #define RP_OFFSET 20 20 #define FRAME_SIZE 64 21 #define CALLEE_REG_FRAME_SIZE 128 22 #define REG_SZ 4 23 #define ASM_ULONG_INSN .word 24 #endif 25 26 /* Frame alignment for 32- and 64-bit */ 27 #define FRAME_ALIGN 64 28 29 #define CALLEE_FLOAT_FRAME_SIZE 80 30 #define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE) 31 32 #ifdef CONFIG_PA20 33 #define LDCW ldcw,co 34 #define BL b,l 35 # ifdef CONFIG_64BIT 36 # define PA_ASM_LEVEL 2.0w 37 # else 38 # define PA_ASM_LEVEL 2.0 39 # endif 40 #else 41 #define LDCW ldcw 42 #define BL bl 43 #define PA_ASM_LEVEL 1.1 44 #endif 45 46 /* Privilege level field in the rightmost two bits of the IA queues */ 47 #define PRIV_USER 3 48 #define PRIV_KERNEL 0 49 50 #ifdef __ASSEMBLY__ 51 52 #ifdef CONFIG_64BIT 53 #define LDREG ldd 54 #define STREG std 55 #define LDREGX ldd,s 56 #define LDREGM ldd,mb 57 #define STREGM std,ma 58 #define SHRREG shrd 59 #define SHLREG shld 60 #define ANDCM andcm,* 61 #define COND(x) * ## x 62 #else /* CONFIG_64BIT */ 63 #define LDREG ldw 64 #define STREG stw 65 #define LDREGX ldwx,s 66 #define LDREGM ldwm 67 #define STREGM stwm 68 #define SHRREG shr 69 #define SHLREG shlw 70 #define ANDCM andcm 71 #define COND(x) x 72 #endif 73 74 #ifdef CONFIG_64BIT 75 /* the 64-bit pa gnu assembler unfortunately defaults to .level 1.1 or 2.0 so 76 * work around that for now... */ 77 .level 2.0w 78 #endif 79 80 #include <asm/asm-offsets.h> 81 #include <asm/page.h> 82 #include <asm/types.h> 83 84 #include <asm/asmregs.h> 85 #include <asm/psw.h> 86 87 sp = 30 88 gp = 27 89 ipsw = 22 90 91 /* 92 * We provide two versions of each macro to convert from physical 93 * to virtual and vice versa. The "_r1" versions take one argument 94 * register, but trashes r1 to do the conversion. The other 95 * version takes two arguments: a src and destination register. 96 * However, the source and destination registers can not be 97 * the same register. 98 */ 99 100 .macro tophys grvirt, grphys 101 ldil L%(__PAGE_OFFSET), \grphys 102 sub \grvirt, \grphys, \grphys 103 .endm 104 105 .macro tovirt grphys, grvirt 106 ldil L%(__PAGE_OFFSET), \grvirt 107 add \grphys, \grvirt, \grvirt 108 .endm 109 110 .macro tophys_r1 gr 111 ldil L%(__PAGE_OFFSET), %r1 112 sub \gr, %r1, \gr 113 .endm 114 115 .macro tovirt_r1 gr 116 ldil L%(__PAGE_OFFSET), %r1 117 add \gr, %r1, \gr 118 .endm 119 120 .macro delay value 121 ldil L%\value, 1 122 ldo R%\value(1), 1 123 addib,UV,n -1,1,. 124 addib,NUV,n -1,1,.+8 125 nop 126 .endm 127 128 .macro debug value 129 .endm 130 131 .macro shlw r, sa, t 132 zdep \r, 31-(\sa), 32-(\sa), \t 133 .endm 134 135 /* And the PA 2.0W shift left */ 136 .macro shld r, sa, t 137 depd,z \r, 63-(\sa), 64-(\sa), \t 138 .endm 139 140 /* Shift Right - note the r and t can NOT be the same! */ 141 .macro shr r, sa, t 142 extru \r, 31-(\sa), 32-(\sa), \t 143 .endm 144 145 /* pa20w version of shift right */ 146 .macro shrd r, sa, t 147 extrd,u \r, 63-(\sa), 64-(\sa), \t 148 .endm 149 150 /* load 32-bit 'value' into 'reg' compensating for the ldil 151 * sign-extension when running in wide mode. 152 * WARNING!! neither 'value' nor 'reg' can be expressions 153 * containing '.'!!!! */ 154 .macro load32 value, reg 155 ldil L%\value, \reg 156 ldo R%\value(\reg), \reg 157 .endm 158 159 .macro loadgp 160 #ifdef CONFIG_64BIT 161 ldil L%__gp, %r27 162 ldo R%__gp(%r27), %r27 163 #else 164 ldil L%$global$, %r27 165 ldo R%$global$(%r27), %r27 166 #endif 167 .endm 168 169 #define SAVE_SP(r, where) mfsp r, %r1 ! STREG %r1, where 170 #define REST_SP(r, where) LDREG where, %r1 ! mtsp %r1, r 171 #define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where 172 #define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r 173 174 .macro save_general regs 175 STREG %r1, PT_GR1 (\regs) 176 STREG %r2, PT_GR2 (\regs) 177 STREG %r3, PT_GR3 (\regs) 178 STREG %r4, PT_GR4 (\regs) 179 STREG %r5, PT_GR5 (\regs) 180 STREG %r6, PT_GR6 (\regs) 181 STREG %r7, PT_GR7 (\regs) 182 STREG %r8, PT_GR8 (\regs) 183 STREG %r9, PT_GR9 (\regs) 184 STREG %r10, PT_GR10(\regs) 185 STREG %r11, PT_GR11(\regs) 186 STREG %r12, PT_GR12(\regs) 187 STREG %r13, PT_GR13(\regs) 188 STREG %r14, PT_GR14(\regs) 189 STREG %r15, PT_GR15(\regs) 190 STREG %r16, PT_GR16(\regs) 191 STREG %r17, PT_GR17(\regs) 192 STREG %r18, PT_GR18(\regs) 193 STREG %r19, PT_GR19(\regs) 194 STREG %r20, PT_GR20(\regs) 195 STREG %r21, PT_GR21(\regs) 196 STREG %r22, PT_GR22(\regs) 197 STREG %r23, PT_GR23(\regs) 198 STREG %r24, PT_GR24(\regs) 199 STREG %r25, PT_GR25(\regs) 200 /* r26 is saved in get_stack and used to preserve a value across virt_map */ 201 STREG %r27, PT_GR27(\regs) 202 STREG %r28, PT_GR28(\regs) 203 /* r29 is saved in get_stack and used to point to saved registers */ 204 /* r30 stack pointer saved in get_stack */ 205 STREG %r31, PT_GR31(\regs) 206 .endm 207 208 .macro rest_general regs 209 /* r1 used as a temp in rest_stack and is restored there */ 210 LDREG PT_GR2 (\regs), %r2 211 LDREG PT_GR3 (\regs), %r3 212 LDREG PT_GR4 (\regs), %r4 213 LDREG PT_GR5 (\regs), %r5 214 LDREG PT_GR6 (\regs), %r6 215 LDREG PT_GR7 (\regs), %r7 216 LDREG PT_GR8 (\regs), %r8 217 LDREG PT_GR9 (\regs), %r9 218 LDREG PT_GR10(\regs), %r10 219 LDREG PT_GR11(\regs), %r11 220 LDREG PT_GR12(\regs), %r12 221 LDREG PT_GR13(\regs), %r13 222 LDREG PT_GR14(\regs), %r14 223 LDREG PT_GR15(\regs), %r15 224 LDREG PT_GR16(\regs), %r16 225 LDREG PT_GR17(\regs), %r17 226 LDREG PT_GR18(\regs), %r18 227 LDREG PT_GR19(\regs), %r19 228 LDREG PT_GR20(\regs), %r20 229 LDREG PT_GR21(\regs), %r21 230 LDREG PT_GR22(\regs), %r22 231 LDREG PT_GR23(\regs), %r23 232 LDREG PT_GR24(\regs), %r24 233 LDREG PT_GR25(\regs), %r25 234 LDREG PT_GR26(\regs), %r26 235 LDREG PT_GR27(\regs), %r27 236 LDREG PT_GR28(\regs), %r28 237 /* r29 points to register save area, and is restored in rest_stack */ 238 /* r30 stack pointer restored in rest_stack */ 239 LDREG PT_GR31(\regs), %r31 240 .endm 241 242 .macro save_fp regs 243 fstd,ma %fr0, 8(\regs) 244 fstd,ma %fr1, 8(\regs) 245 fstd,ma %fr2, 8(\regs) 246 fstd,ma %fr3, 8(\regs) 247 fstd,ma %fr4, 8(\regs) 248 fstd,ma %fr5, 8(\regs) 249 fstd,ma %fr6, 8(\regs) 250 fstd,ma %fr7, 8(\regs) 251 fstd,ma %fr8, 8(\regs) 252 fstd,ma %fr9, 8(\regs) 253 fstd,ma %fr10, 8(\regs) 254 fstd,ma %fr11, 8(\regs) 255 fstd,ma %fr12, 8(\regs) 256 fstd,ma %fr13, 8(\regs) 257 fstd,ma %fr14, 8(\regs) 258 fstd,ma %fr15, 8(\regs) 259 fstd,ma %fr16, 8(\regs) 260 fstd,ma %fr17, 8(\regs) 261 fstd,ma %fr18, 8(\regs) 262 fstd,ma %fr19, 8(\regs) 263 fstd,ma %fr20, 8(\regs) 264 fstd,ma %fr21, 8(\regs) 265 fstd,ma %fr22, 8(\regs) 266 fstd,ma %fr23, 8(\regs) 267 fstd,ma %fr24, 8(\regs) 268 fstd,ma %fr25, 8(\regs) 269 fstd,ma %fr26, 8(\regs) 270 fstd,ma %fr27, 8(\regs) 271 fstd,ma %fr28, 8(\regs) 272 fstd,ma %fr29, 8(\regs) 273 fstd,ma %fr30, 8(\regs) 274 fstd %fr31, 0(\regs) 275 .endm 276 277 .macro rest_fp regs 278 fldd 0(\regs), %fr31 279 fldd,mb -8(\regs), %fr30 280 fldd,mb -8(\regs), %fr29 281 fldd,mb -8(\regs), %fr28 282 fldd,mb -8(\regs), %fr27 283 fldd,mb -8(\regs), %fr26 284 fldd,mb -8(\regs), %fr25 285 fldd,mb -8(\regs), %fr24 286 fldd,mb -8(\regs), %fr23 287 fldd,mb -8(\regs), %fr22 288 fldd,mb -8(\regs), %fr21 289 fldd,mb -8(\regs), %fr20 290 fldd,mb -8(\regs), %fr19 291 fldd,mb -8(\regs), %fr18 292 fldd,mb -8(\regs), %fr17 293 fldd,mb -8(\regs), %fr16 294 fldd,mb -8(\regs), %fr15 295 fldd,mb -8(\regs), %fr14 296 fldd,mb -8(\regs), %fr13 297 fldd,mb -8(\regs), %fr12 298 fldd,mb -8(\regs), %fr11 299 fldd,mb -8(\regs), %fr10 300 fldd,mb -8(\regs), %fr9 301 fldd,mb -8(\regs), %fr8 302 fldd,mb -8(\regs), %fr7 303 fldd,mb -8(\regs), %fr6 304 fldd,mb -8(\regs), %fr5 305 fldd,mb -8(\regs), %fr4 306 fldd,mb -8(\regs), %fr3 307 fldd,mb -8(\regs), %fr2 308 fldd,mb -8(\regs), %fr1 309 fldd,mb -8(\regs), %fr0 310 .endm 311 312 .macro callee_save_float 313 fstd,ma %fr12, 8(%r30) 314 fstd,ma %fr13, 8(%r30) 315 fstd,ma %fr14, 8(%r30) 316 fstd,ma %fr15, 8(%r30) 317 fstd,ma %fr16, 8(%r30) 318 fstd,ma %fr17, 8(%r30) 319 fstd,ma %fr18, 8(%r30) 320 fstd,ma %fr19, 8(%r30) 321 fstd,ma %fr20, 8(%r30) 322 fstd,ma %fr21, 8(%r30) 323 .endm 324 325 .macro callee_rest_float 326 fldd,mb -8(%r30), %fr21 327 fldd,mb -8(%r30), %fr20 328 fldd,mb -8(%r30), %fr19 329 fldd,mb -8(%r30), %fr18 330 fldd,mb -8(%r30), %fr17 331 fldd,mb -8(%r30), %fr16 332 fldd,mb -8(%r30), %fr15 333 fldd,mb -8(%r30), %fr14 334 fldd,mb -8(%r30), %fr13 335 fldd,mb -8(%r30), %fr12 336 .endm 337 338 #ifdef CONFIG_64BIT 339 .macro callee_save 340 std,ma %r3, CALLEE_REG_FRAME_SIZE(%r30) 341 mfctl %cr27, %r3 342 std %r4, -136(%r30) 343 std %r5, -128(%r30) 344 std %r6, -120(%r30) 345 std %r7, -112(%r30) 346 std %r8, -104(%r30) 347 std %r9, -96(%r30) 348 std %r10, -88(%r30) 349 std %r11, -80(%r30) 350 std %r12, -72(%r30) 351 std %r13, -64(%r30) 352 std %r14, -56(%r30) 353 std %r15, -48(%r30) 354 std %r16, -40(%r30) 355 std %r17, -32(%r30) 356 std %r18, -24(%r30) 357 std %r3, -16(%r30) 358 .endm 359 360 .macro callee_rest 361 ldd -16(%r30), %r3 362 ldd -24(%r30), %r18 363 ldd -32(%r30), %r17 364 ldd -40(%r30), %r16 365 ldd -48(%r30), %r15 366 ldd -56(%r30), %r14 367 ldd -64(%r30), %r13 368 ldd -72(%r30), %r12 369 ldd -80(%r30), %r11 370 ldd -88(%r30), %r10 371 ldd -96(%r30), %r9 372 ldd -104(%r30), %r8 373 ldd -112(%r30), %r7 374 ldd -120(%r30), %r6 375 ldd -128(%r30), %r5 376 ldd -136(%r30), %r4 377 mtctl %r3, %cr27 378 ldd,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3 379 .endm 380 381 #else /* ! CONFIG_64BIT */ 382 383 .macro callee_save 384 stw,ma %r3, CALLEE_REG_FRAME_SIZE(%r30) 385 mfctl %cr27, %r3 386 stw %r4, -124(%r30) 387 stw %r5, -120(%r30) 388 stw %r6, -116(%r30) 389 stw %r7, -112(%r30) 390 stw %r8, -108(%r30) 391 stw %r9, -104(%r30) 392 stw %r10, -100(%r30) 393 stw %r11, -96(%r30) 394 stw %r12, -92(%r30) 395 stw %r13, -88(%r30) 396 stw %r14, -84(%r30) 397 stw %r15, -80(%r30) 398 stw %r16, -76(%r30) 399 stw %r17, -72(%r30) 400 stw %r18, -68(%r30) 401 stw %r3, -64(%r30) 402 .endm 403 404 .macro callee_rest 405 ldw -64(%r30), %r3 406 ldw -68(%r30), %r18 407 ldw -72(%r30), %r17 408 ldw -76(%r30), %r16 409 ldw -80(%r30), %r15 410 ldw -84(%r30), %r14 411 ldw -88(%r30), %r13 412 ldw -92(%r30), %r12 413 ldw -96(%r30), %r11 414 ldw -100(%r30), %r10 415 ldw -104(%r30), %r9 416 ldw -108(%r30), %r8 417 ldw -112(%r30), %r7 418 ldw -116(%r30), %r6 419 ldw -120(%r30), %r5 420 ldw -124(%r30), %r4 421 mtctl %r3, %cr27 422 ldw,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3 423 .endm 424 #endif /* ! CONFIG_64BIT */ 425 426 .macro save_specials regs 427 428 SAVE_SP (%sr0, PT_SR0 (\regs)) 429 SAVE_SP (%sr1, PT_SR1 (\regs)) 430 SAVE_SP (%sr2, PT_SR2 (\regs)) 431 SAVE_SP (%sr3, PT_SR3 (\regs)) 432 SAVE_SP (%sr4, PT_SR4 (\regs)) 433 SAVE_SP (%sr5, PT_SR5 (\regs)) 434 SAVE_SP (%sr6, PT_SR6 (\regs)) 435 436 SAVE_CR (%cr17, PT_IASQ0(\regs)) 437 mtctl %r0, %cr17 438 SAVE_CR (%cr17, PT_IASQ1(\regs)) 439 440 SAVE_CR (%cr18, PT_IAOQ0(\regs)) 441 mtctl %r0, %cr18 442 SAVE_CR (%cr18, PT_IAOQ1(\regs)) 443 444 #ifdef CONFIG_64BIT 445 /* cr11 (sar) is a funny one. 5 bits on PA1.1 and 6 bit on PA2.0 446 * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only 447 * reads 5 bits. Use mfctl,w to read all six bits. Otherwise 448 * we lose the 6th bit on a save/restore over interrupt. 449 */ 450 mfctl,w %cr11, %r1 451 STREG %r1, PT_SAR (\regs) 452 #else 453 SAVE_CR (%cr11, PT_SAR (\regs)) 454 #endif 455 SAVE_CR (%cr19, PT_IIR (\regs)) 456 457 /* 458 * Code immediately following this macro (in intr_save) relies 459 * on r8 containing ipsw. 460 */ 461 mfctl %cr22, %r8 462 STREG %r8, PT_PSW(\regs) 463 .endm 464 465 .macro rest_specials regs 466 467 REST_SP (%sr0, PT_SR0 (\regs)) 468 REST_SP (%sr1, PT_SR1 (\regs)) 469 REST_SP (%sr2, PT_SR2 (\regs)) 470 REST_SP (%sr3, PT_SR3 (\regs)) 471 REST_SP (%sr4, PT_SR4 (\regs)) 472 REST_SP (%sr5, PT_SR5 (\regs)) 473 REST_SP (%sr6, PT_SR6 (\regs)) 474 REST_SP (%sr7, PT_SR7 (\regs)) 475 476 REST_CR (%cr17, PT_IASQ0(\regs)) 477 REST_CR (%cr17, PT_IASQ1(\regs)) 478 479 REST_CR (%cr18, PT_IAOQ0(\regs)) 480 REST_CR (%cr18, PT_IAOQ1(\regs)) 481 482 REST_CR (%cr11, PT_SAR (\regs)) 483 484 REST_CR (%cr22, PT_PSW (\regs)) 485 .endm 486 487 488 /* First step to create a "relied upon translation" 489 * See PA 2.0 Arch. page F-4 and F-5. 490 * 491 * The ssm was originally necessary due to a "PCxT bug". 492 * But someone decided it needed to be added to the architecture 493 * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual. 494 * It's been carried forward into PA 2.0 Arch as well. :^( 495 * 496 * "ssm 0,%r0" is a NOP with side effects (prefetch barrier). 497 * rsm/ssm prevents the ifetch unit from speculatively fetching 498 * instructions past this line in the code stream. 499 * PA 2.0 processor will single step all insn in the same QUAD (4 insn). 500 */ 501 .macro pcxt_ssm_bug 502 rsm PSW_SM_I,%r0 503 nop /* 1 */ 504 nop /* 2 */ 505 nop /* 3 */ 506 nop /* 4 */ 507 nop /* 5 */ 508 nop /* 6 */ 509 nop /* 7 */ 510 .endm 511 512 /* Switch to virtual mapping, trashing only %r1 */ 513 .macro virt_map 514 /* pcxt_ssm_bug */ 515 rsm PSW_SM_I, %r0 /* barrier for "Relied upon Translation */ 516 mtsp %r0, %sr4 517 mtsp %r0, %sr5 518 mtsp %r0, %sr6 519 tovirt_r1 %r29 520 load32 KERNEL_PSW, %r1 521 522 rsm PSW_SM_QUIET,%r0 /* second "heavy weight" ctl op */ 523 mtctl %r0, %cr17 /* Clear IIASQ tail */ 524 mtctl %r0, %cr17 /* Clear IIASQ head */ 525 mtctl %r1, %ipsw 526 load32 4f, %r1 527 mtctl %r1, %cr18 /* Set IIAOQ tail */ 528 ldo 4(%r1), %r1 529 mtctl %r1, %cr18 /* Set IIAOQ head */ 530 rfir 531 nop 532 4: 533 .endm 534 535 536 /* 537 * ASM_EXCEPTIONTABLE_ENTRY 538 * 539 * Creates an exception table entry. 540 * Do not convert to a assembler macro. This won't work. 541 */ 542 #define ASM_EXCEPTIONTABLE_ENTRY(fault_addr, except_addr) \ 543 .section __ex_table,"aw" ! \ 544 .word (fault_addr - .), (except_addr - .) ! \ 545 .previous 546 547 548 #endif /* __ASSEMBLY__ */ 549 #endif 550