1 /* 2 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand) 3 * Copyright (C) 1999 Philipp Rumpf <prumpf@tux.org> 4 * Copyright (C) 1999 SuSE GmbH 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2, or (at your option) 9 * any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #ifndef _PARISC_ASSEMBLY_H 22 #define _PARISC_ASSEMBLY_H 23 24 #define CALLEE_FLOAT_FRAME_SIZE 80 25 26 #ifdef CONFIG_64BIT 27 #define LDREG ldd 28 #define STREG std 29 #define LDREGX ldd,s 30 #define LDREGM ldd,mb 31 #define STREGM std,ma 32 #define SHRREG shrd 33 #define SHLREG shld 34 #define ANDCM andcm,* 35 #define COND(x) * ## x 36 #define RP_OFFSET 16 37 #define FRAME_SIZE 128 38 #define CALLEE_REG_FRAME_SIZE 144 39 #define REG_SZ 8 40 #define ASM_ULONG_INSN .dword 41 #else /* CONFIG_64BIT */ 42 #define LDREG ldw 43 #define STREG stw 44 #define LDREGX ldwx,s 45 #define LDREGM ldwm 46 #define STREGM stwm 47 #define SHRREG shr 48 #define SHLREG shlw 49 #define ANDCM andcm 50 #define COND(x) x 51 #define RP_OFFSET 20 52 #define FRAME_SIZE 64 53 #define CALLEE_REG_FRAME_SIZE 128 54 #define REG_SZ 4 55 #define ASM_ULONG_INSN .word 56 #endif 57 58 #define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE) 59 60 #ifdef CONFIG_PA20 61 #define LDCW ldcw,co 62 #define BL b,l 63 # ifdef CONFIG_64BIT 64 # define PA_ASM_LEVEL 2.0w 65 # else 66 # define PA_ASM_LEVEL 2.0 67 # endif 68 #else 69 #define LDCW ldcw 70 #define BL bl 71 #define PA_ASM_LEVEL 1.1 72 #endif 73 74 #ifdef __ASSEMBLY__ 75 76 #ifdef CONFIG_64BIT 77 /* the 64-bit pa gnu assembler unfortunately defaults to .level 1.1 or 2.0 so 78 * work around that for now... */ 79 .level 2.0w 80 #endif 81 82 #include <asm/asm-offsets.h> 83 #include <asm/page.h> 84 #include <asm/types.h> 85 86 #include <asm/asmregs.h> 87 88 sp = 30 89 gp = 27 90 ipsw = 22 91 92 /* 93 * We provide two versions of each macro to convert from physical 94 * to virtual and vice versa. The "_r1" versions take one argument 95 * register, but trashes r1 to do the conversion. The other 96 * version takes two arguments: a src and destination register. 97 * However, the source and destination registers can not be 98 * the same register. 99 */ 100 101 .macro tophys grvirt, grphys 102 ldil L%(__PAGE_OFFSET), \grphys 103 sub \grvirt, \grphys, \grphys 104 .endm 105 106 .macro tovirt grphys, grvirt 107 ldil L%(__PAGE_OFFSET), \grvirt 108 add \grphys, \grvirt, \grvirt 109 .endm 110 111 .macro tophys_r1 gr 112 ldil L%(__PAGE_OFFSET), %r1 113 sub \gr, %r1, \gr 114 .endm 115 116 .macro tovirt_r1 gr 117 ldil L%(__PAGE_OFFSET), %r1 118 add \gr, %r1, \gr 119 .endm 120 121 .macro delay value 122 ldil L%\value, 1 123 ldo R%\value(1), 1 124 addib,UV,n -1,1,. 125 addib,NUV,n -1,1,.+8 126 nop 127 .endm 128 129 .macro debug value 130 .endm 131 132 .macro shlw r, sa, t 133 zdep \r, 31-(\sa), 32-(\sa), \t 134 .endm 135 136 /* And the PA 2.0W shift left */ 137 .macro shld r, sa, t 138 depd,z \r, 63-(\sa), 64-(\sa), \t 139 .endm 140 141 /* Shift Right - note the r and t can NOT be the same! */ 142 .macro shr r, sa, t 143 extru \r, 31-(\sa), 32-(\sa), \t 144 .endm 145 146 /* pa20w version of shift right */ 147 .macro shrd r, sa, t 148 extrd,u \r, 63-(\sa), 64-(\sa), \t 149 .endm 150 151 /* load 32-bit 'value' into 'reg' compensating for the ldil 152 * sign-extension when running in wide mode. 153 * WARNING!! neither 'value' nor 'reg' can be expressions 154 * containing '.'!!!! */ 155 .macro load32 value, reg 156 ldil L%\value, \reg 157 ldo R%\value(\reg), \reg 158 .endm 159 160 .macro loadgp 161 #ifdef CONFIG_64BIT 162 ldil L%__gp, %r27 163 ldo R%__gp(%r27), %r27 164 #else 165 ldil L%$global$, %r27 166 ldo R%$global$(%r27), %r27 167 #endif 168 .endm 169 170 #define SAVE_SP(r, where) mfsp r, %r1 ! STREG %r1, where 171 #define REST_SP(r, where) LDREG where, %r1 ! mtsp %r1, r 172 #define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where 173 #define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r 174 175 .macro save_general regs 176 STREG %r1, PT_GR1 (\regs) 177 STREG %r2, PT_GR2 (\regs) 178 STREG %r3, PT_GR3 (\regs) 179 STREG %r4, PT_GR4 (\regs) 180 STREG %r5, PT_GR5 (\regs) 181 STREG %r6, PT_GR6 (\regs) 182 STREG %r7, PT_GR7 (\regs) 183 STREG %r8, PT_GR8 (\regs) 184 STREG %r9, PT_GR9 (\regs) 185 STREG %r10, PT_GR10(\regs) 186 STREG %r11, PT_GR11(\regs) 187 STREG %r12, PT_GR12(\regs) 188 STREG %r13, PT_GR13(\regs) 189 STREG %r14, PT_GR14(\regs) 190 STREG %r15, PT_GR15(\regs) 191 STREG %r16, PT_GR16(\regs) 192 STREG %r17, PT_GR17(\regs) 193 STREG %r18, PT_GR18(\regs) 194 STREG %r19, PT_GR19(\regs) 195 STREG %r20, PT_GR20(\regs) 196 STREG %r21, PT_GR21(\regs) 197 STREG %r22, PT_GR22(\regs) 198 STREG %r23, PT_GR23(\regs) 199 STREG %r24, PT_GR24(\regs) 200 STREG %r25, PT_GR25(\regs) 201 /* r26 is saved in get_stack and used to preserve a value across virt_map */ 202 STREG %r27, PT_GR27(\regs) 203 STREG %r28, PT_GR28(\regs) 204 /* r29 is saved in get_stack and used to point to saved registers */ 205 /* r30 stack pointer saved in get_stack */ 206 STREG %r31, PT_GR31(\regs) 207 .endm 208 209 .macro rest_general regs 210 /* r1 used as a temp in rest_stack and is restored there */ 211 LDREG PT_GR2 (\regs), %r2 212 LDREG PT_GR3 (\regs), %r3 213 LDREG PT_GR4 (\regs), %r4 214 LDREG PT_GR5 (\regs), %r5 215 LDREG PT_GR6 (\regs), %r6 216 LDREG PT_GR7 (\regs), %r7 217 LDREG PT_GR8 (\regs), %r8 218 LDREG PT_GR9 (\regs), %r9 219 LDREG PT_GR10(\regs), %r10 220 LDREG PT_GR11(\regs), %r11 221 LDREG PT_GR12(\regs), %r12 222 LDREG PT_GR13(\regs), %r13 223 LDREG PT_GR14(\regs), %r14 224 LDREG PT_GR15(\regs), %r15 225 LDREG PT_GR16(\regs), %r16 226 LDREG PT_GR17(\regs), %r17 227 LDREG PT_GR18(\regs), %r18 228 LDREG PT_GR19(\regs), %r19 229 LDREG PT_GR20(\regs), %r20 230 LDREG PT_GR21(\regs), %r21 231 LDREG PT_GR22(\regs), %r22 232 LDREG PT_GR23(\regs), %r23 233 LDREG PT_GR24(\regs), %r24 234 LDREG PT_GR25(\regs), %r25 235 LDREG PT_GR26(\regs), %r26 236 LDREG PT_GR27(\regs), %r27 237 LDREG PT_GR28(\regs), %r28 238 /* r29 points to register save area, and is restored in rest_stack */ 239 /* r30 stack pointer restored in rest_stack */ 240 LDREG PT_GR31(\regs), %r31 241 .endm 242 243 .macro save_fp regs 244 fstd,ma %fr0, 8(\regs) 245 fstd,ma %fr1, 8(\regs) 246 fstd,ma %fr2, 8(\regs) 247 fstd,ma %fr3, 8(\regs) 248 fstd,ma %fr4, 8(\regs) 249 fstd,ma %fr5, 8(\regs) 250 fstd,ma %fr6, 8(\regs) 251 fstd,ma %fr7, 8(\regs) 252 fstd,ma %fr8, 8(\regs) 253 fstd,ma %fr9, 8(\regs) 254 fstd,ma %fr10, 8(\regs) 255 fstd,ma %fr11, 8(\regs) 256 fstd,ma %fr12, 8(\regs) 257 fstd,ma %fr13, 8(\regs) 258 fstd,ma %fr14, 8(\regs) 259 fstd,ma %fr15, 8(\regs) 260 fstd,ma %fr16, 8(\regs) 261 fstd,ma %fr17, 8(\regs) 262 fstd,ma %fr18, 8(\regs) 263 fstd,ma %fr19, 8(\regs) 264 fstd,ma %fr20, 8(\regs) 265 fstd,ma %fr21, 8(\regs) 266 fstd,ma %fr22, 8(\regs) 267 fstd,ma %fr23, 8(\regs) 268 fstd,ma %fr24, 8(\regs) 269 fstd,ma %fr25, 8(\regs) 270 fstd,ma %fr26, 8(\regs) 271 fstd,ma %fr27, 8(\regs) 272 fstd,ma %fr28, 8(\regs) 273 fstd,ma %fr29, 8(\regs) 274 fstd,ma %fr30, 8(\regs) 275 fstd %fr31, 0(\regs) 276 .endm 277 278 .macro rest_fp regs 279 fldd 0(\regs), %fr31 280 fldd,mb -8(\regs), %fr30 281 fldd,mb -8(\regs), %fr29 282 fldd,mb -8(\regs), %fr28 283 fldd,mb -8(\regs), %fr27 284 fldd,mb -8(\regs), %fr26 285 fldd,mb -8(\regs), %fr25 286 fldd,mb -8(\regs), %fr24 287 fldd,mb -8(\regs), %fr23 288 fldd,mb -8(\regs), %fr22 289 fldd,mb -8(\regs), %fr21 290 fldd,mb -8(\regs), %fr20 291 fldd,mb -8(\regs), %fr19 292 fldd,mb -8(\regs), %fr18 293 fldd,mb -8(\regs), %fr17 294 fldd,mb -8(\regs), %fr16 295 fldd,mb -8(\regs), %fr15 296 fldd,mb -8(\regs), %fr14 297 fldd,mb -8(\regs), %fr13 298 fldd,mb -8(\regs), %fr12 299 fldd,mb -8(\regs), %fr11 300 fldd,mb -8(\regs), %fr10 301 fldd,mb -8(\regs), %fr9 302 fldd,mb -8(\regs), %fr8 303 fldd,mb -8(\regs), %fr7 304 fldd,mb -8(\regs), %fr6 305 fldd,mb -8(\regs), %fr5 306 fldd,mb -8(\regs), %fr4 307 fldd,mb -8(\regs), %fr3 308 fldd,mb -8(\regs), %fr2 309 fldd,mb -8(\regs), %fr1 310 fldd,mb -8(\regs), %fr0 311 .endm 312 313 .macro callee_save_float 314 fstd,ma %fr12, 8(%r30) 315 fstd,ma %fr13, 8(%r30) 316 fstd,ma %fr14, 8(%r30) 317 fstd,ma %fr15, 8(%r30) 318 fstd,ma %fr16, 8(%r30) 319 fstd,ma %fr17, 8(%r30) 320 fstd,ma %fr18, 8(%r30) 321 fstd,ma %fr19, 8(%r30) 322 fstd,ma %fr20, 8(%r30) 323 fstd,ma %fr21, 8(%r30) 324 .endm 325 326 .macro callee_rest_float 327 fldd,mb -8(%r30), %fr21 328 fldd,mb -8(%r30), %fr20 329 fldd,mb -8(%r30), %fr19 330 fldd,mb -8(%r30), %fr18 331 fldd,mb -8(%r30), %fr17 332 fldd,mb -8(%r30), %fr16 333 fldd,mb -8(%r30), %fr15 334 fldd,mb -8(%r30), %fr14 335 fldd,mb -8(%r30), %fr13 336 fldd,mb -8(%r30), %fr12 337 .endm 338 339 #ifdef CONFIG_64BIT 340 .macro callee_save 341 std,ma %r3, CALLEE_REG_FRAME_SIZE(%r30) 342 mfctl %cr27, %r3 343 std %r4, -136(%r30) 344 std %r5, -128(%r30) 345 std %r6, -120(%r30) 346 std %r7, -112(%r30) 347 std %r8, -104(%r30) 348 std %r9, -96(%r30) 349 std %r10, -88(%r30) 350 std %r11, -80(%r30) 351 std %r12, -72(%r30) 352 std %r13, -64(%r30) 353 std %r14, -56(%r30) 354 std %r15, -48(%r30) 355 std %r16, -40(%r30) 356 std %r17, -32(%r30) 357 std %r18, -24(%r30) 358 std %r3, -16(%r30) 359 .endm 360 361 .macro callee_rest 362 ldd -16(%r30), %r3 363 ldd -24(%r30), %r18 364 ldd -32(%r30), %r17 365 ldd -40(%r30), %r16 366 ldd -48(%r30), %r15 367 ldd -56(%r30), %r14 368 ldd -64(%r30), %r13 369 ldd -72(%r30), %r12 370 ldd -80(%r30), %r11 371 ldd -88(%r30), %r10 372 ldd -96(%r30), %r9 373 ldd -104(%r30), %r8 374 ldd -112(%r30), %r7 375 ldd -120(%r30), %r6 376 ldd -128(%r30), %r5 377 ldd -136(%r30), %r4 378 mtctl %r3, %cr27 379 ldd,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3 380 .endm 381 382 #else /* ! CONFIG_64BIT */ 383 384 .macro callee_save 385 stw,ma %r3, CALLEE_REG_FRAME_SIZE(%r30) 386 mfctl %cr27, %r3 387 stw %r4, -124(%r30) 388 stw %r5, -120(%r30) 389 stw %r6, -116(%r30) 390 stw %r7, -112(%r30) 391 stw %r8, -108(%r30) 392 stw %r9, -104(%r30) 393 stw %r10, -100(%r30) 394 stw %r11, -96(%r30) 395 stw %r12, -92(%r30) 396 stw %r13, -88(%r30) 397 stw %r14, -84(%r30) 398 stw %r15, -80(%r30) 399 stw %r16, -76(%r30) 400 stw %r17, -72(%r30) 401 stw %r18, -68(%r30) 402 stw %r3, -64(%r30) 403 .endm 404 405 .macro callee_rest 406 ldw -64(%r30), %r3 407 ldw -68(%r30), %r18 408 ldw -72(%r30), %r17 409 ldw -76(%r30), %r16 410 ldw -80(%r30), %r15 411 ldw -84(%r30), %r14 412 ldw -88(%r30), %r13 413 ldw -92(%r30), %r12 414 ldw -96(%r30), %r11 415 ldw -100(%r30), %r10 416 ldw -104(%r30), %r9 417 ldw -108(%r30), %r8 418 ldw -112(%r30), %r7 419 ldw -116(%r30), %r6 420 ldw -120(%r30), %r5 421 ldw -124(%r30), %r4 422 mtctl %r3, %cr27 423 ldw,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3 424 .endm 425 #endif /* ! CONFIG_64BIT */ 426 427 .macro save_specials regs 428 429 SAVE_SP (%sr0, PT_SR0 (\regs)) 430 SAVE_SP (%sr1, PT_SR1 (\regs)) 431 SAVE_SP (%sr2, PT_SR2 (\regs)) 432 SAVE_SP (%sr3, PT_SR3 (\regs)) 433 SAVE_SP (%sr4, PT_SR4 (\regs)) 434 SAVE_SP (%sr5, PT_SR5 (\regs)) 435 SAVE_SP (%sr6, PT_SR6 (\regs)) 436 437 SAVE_CR (%cr17, PT_IASQ0(\regs)) 438 mtctl %r0, %cr17 439 SAVE_CR (%cr17, PT_IASQ1(\regs)) 440 441 SAVE_CR (%cr18, PT_IAOQ0(\regs)) 442 mtctl %r0, %cr18 443 SAVE_CR (%cr18, PT_IAOQ1(\regs)) 444 445 #ifdef CONFIG_64BIT 446 /* cr11 (sar) is a funny one. 5 bits on PA1.1 and 6 bit on PA2.0 447 * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only 448 * reads 5 bits. Use mfctl,w to read all six bits. Otherwise 449 * we lose the 6th bit on a save/restore over interrupt. 450 */ 451 mfctl,w %cr11, %r1 452 STREG %r1, PT_SAR (\regs) 453 #else 454 SAVE_CR (%cr11, PT_SAR (\regs)) 455 #endif 456 SAVE_CR (%cr19, PT_IIR (\regs)) 457 458 /* 459 * Code immediately following this macro (in intr_save) relies 460 * on r8 containing ipsw. 461 */ 462 mfctl %cr22, %r8 463 STREG %r8, PT_PSW(\regs) 464 .endm 465 466 .macro rest_specials regs 467 468 REST_SP (%sr0, PT_SR0 (\regs)) 469 REST_SP (%sr1, PT_SR1 (\regs)) 470 REST_SP (%sr2, PT_SR2 (\regs)) 471 REST_SP (%sr3, PT_SR3 (\regs)) 472 REST_SP (%sr4, PT_SR4 (\regs)) 473 REST_SP (%sr5, PT_SR5 (\regs)) 474 REST_SP (%sr6, PT_SR6 (\regs)) 475 REST_SP (%sr7, PT_SR7 (\regs)) 476 477 REST_CR (%cr17, PT_IASQ0(\regs)) 478 REST_CR (%cr17, PT_IASQ1(\regs)) 479 480 REST_CR (%cr18, PT_IAOQ0(\regs)) 481 REST_CR (%cr18, PT_IAOQ1(\regs)) 482 483 REST_CR (%cr11, PT_SAR (\regs)) 484 485 REST_CR (%cr22, PT_PSW (\regs)) 486 .endm 487 488 489 /* First step to create a "relied upon translation" 490 * See PA 2.0 Arch. page F-4 and F-5. 491 * 492 * The ssm was originally necessary due to a "PCxT bug". 493 * But someone decided it needed to be added to the architecture 494 * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual. 495 * It's been carried forward into PA 2.0 Arch as well. :^( 496 * 497 * "ssm 0,%r0" is a NOP with side effects (prefetch barrier). 498 * rsm/ssm prevents the ifetch unit from speculatively fetching 499 * instructions past this line in the code stream. 500 * PA 2.0 processor will single step all insn in the same QUAD (4 insn). 501 */ 502 .macro pcxt_ssm_bug 503 rsm PSW_SM_I,%r0 504 nop /* 1 */ 505 nop /* 2 */ 506 nop /* 3 */ 507 nop /* 4 */ 508 nop /* 5 */ 509 nop /* 6 */ 510 nop /* 7 */ 511 .endm 512 513 /* 514 * ASM_EXCEPTIONTABLE_ENTRY 515 * 516 * Creates an exception table entry. 517 * Do not convert to a assembler macro. This won't work. 518 */ 519 #define ASM_EXCEPTIONTABLE_ENTRY(fault_addr, except_addr) \ 520 .section __ex_table,"aw" ! \ 521 .word (fault_addr - .), (except_addr - .) ! \ 522 .previous 523 524 525 #endif /* __ASSEMBLY__ */ 526 #endif 527