1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand) 4 * Copyright (C) 1999 Philipp Rumpf <prumpf@tux.org> 5 * Copyright (C) 1999 SuSE GmbH 6 * Copyright (C) 2021 Helge Deller <deller@gmx.de> 7 */ 8 9 #ifndef _PARISC_ASSEMBLY_H 10 #define _PARISC_ASSEMBLY_H 11 12 #ifdef CONFIG_64BIT 13 #define RP_OFFSET 16 14 #define FRAME_SIZE 128 15 #define CALLEE_REG_FRAME_SIZE 144 16 #define REG_SZ 8 17 #define ASM_ULONG_INSN .dword 18 #else /* CONFIG_64BIT */ 19 #define RP_OFFSET 20 20 #define FRAME_SIZE 64 21 #define CALLEE_REG_FRAME_SIZE 128 22 #define REG_SZ 4 23 #define ASM_ULONG_INSN .word 24 #endif 25 26 /* Frame alignment for 32- and 64-bit */ 27 #define FRAME_ALIGN 64 28 29 #define CALLEE_FLOAT_FRAME_SIZE 80 30 #define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE) 31 32 #ifdef CONFIG_PA20 33 #define LDCW ldcw,co 34 #define BL b,l 35 # ifdef CONFIG_64BIT 36 # define PA_ASM_LEVEL 2.0w 37 # else 38 # define PA_ASM_LEVEL 2.0 39 # endif 40 #else 41 #define LDCW ldcw 42 #define BL bl 43 #define PA_ASM_LEVEL 1.1 44 #endif 45 46 /* Privilege level field in the rightmost two bits of the IA queues */ 47 #define PRIV_USER 3 48 #define PRIV_KERNEL 0 49 50 /* Space register used inside kernel */ 51 #define SR_KERNEL 0 52 #define SR_TEMP1 1 53 #define SR_TEMP2 2 54 #define SR_USER 3 55 56 #ifdef __ASSEMBLY__ 57 58 #ifdef CONFIG_64BIT 59 #define LDREG ldd 60 #define STREG std 61 #define LDREGX ldd,s 62 #define LDREGM ldd,mb 63 #define STREGM std,ma 64 #define SHRREG shrd 65 #define SHLREG shld 66 #define ANDCM andcm,* 67 #define COND(x) * ## x 68 #else /* CONFIG_64BIT */ 69 #define LDREG ldw 70 #define STREG stw 71 #define LDREGX ldwx,s 72 #define LDREGM ldwm 73 #define STREGM stwm 74 #define SHRREG shr 75 #define SHLREG shlw 76 #define ANDCM andcm 77 #define COND(x) x 78 #endif 79 80 #ifdef CONFIG_64BIT 81 /* the 64-bit pa gnu assembler unfortunately defaults to .level 1.1 or 2.0 so 82 * work around that for now... */ 83 .level 2.0w 84 #endif 85 86 #include <asm/asm-offsets.h> 87 #include <asm/page.h> 88 #include <asm/types.h> 89 90 #include <asm/asmregs.h> 91 #include <asm/psw.h> 92 93 sp = 30 94 gp = 27 95 ipsw = 22 96 97 /* 98 * We provide two versions of each macro to convert from physical 99 * to virtual and vice versa. The "_r1" versions take one argument 100 * register, but trashes r1 to do the conversion. The other 101 * version takes two arguments: a src and destination register. 102 * However, the source and destination registers can not be 103 * the same register. 104 */ 105 106 .macro tophys grvirt, grphys 107 ldil L%(__PAGE_OFFSET), \grphys 108 sub \grvirt, \grphys, \grphys 109 .endm 110 111 .macro tovirt grphys, grvirt 112 ldil L%(__PAGE_OFFSET), \grvirt 113 add \grphys, \grvirt, \grvirt 114 .endm 115 116 .macro tophys_r1 gr 117 ldil L%(__PAGE_OFFSET), %r1 118 sub \gr, %r1, \gr 119 .endm 120 121 .macro tovirt_r1 gr 122 ldil L%(__PAGE_OFFSET), %r1 123 add \gr, %r1, \gr 124 .endm 125 126 .macro delay value 127 ldil L%\value, 1 128 ldo R%\value(1), 1 129 addib,UV,n -1,1,. 130 addib,NUV,n -1,1,.+8 131 nop 132 .endm 133 134 .macro debug value 135 .endm 136 137 .macro shlw r, sa, t 138 zdep \r, 31-(\sa), 32-(\sa), \t 139 .endm 140 141 /* And the PA 2.0W shift left */ 142 .macro shld r, sa, t 143 depd,z \r, 63-(\sa), 64-(\sa), \t 144 .endm 145 146 /* Shift Right - note the r and t can NOT be the same! */ 147 .macro shr r, sa, t 148 extru \r, 31-(\sa), 32-(\sa), \t 149 .endm 150 151 /* pa20w version of shift right */ 152 .macro shrd r, sa, t 153 extrd,u \r, 63-(\sa), 64-(\sa), \t 154 .endm 155 156 /* Extract unsigned for 32- and 64-bit 157 * The extru instruction leaves the most significant 32 bits of the 158 * target register in an undefined state on PA 2.0 systems. */ 159 .macro extru_safe r, p, len, t 160 #ifdef CONFIG_64BIT 161 extrd,u \r, 32+(\p), \len, \t 162 #else 163 extru \r, \p, \len, \t 164 #endif 165 .endm 166 167 /* The depi instruction leaves the most significant 32 bits of the 168 * target register in an undefined state on PA 2.0 systems. */ 169 .macro depi_safe i, p, len, t 170 #ifdef CONFIG_64BIT 171 depdi \i, 32+(\p), \len, \t 172 #else 173 depi \i, \p, \len, \t 174 #endif 175 .endm 176 177 /* load 32-bit 'value' into 'reg' compensating for the ldil 178 * sign-extension when running in wide mode. 179 * WARNING!! neither 'value' nor 'reg' can be expressions 180 * containing '.'!!!! */ 181 .macro load32 value, reg 182 ldil L%\value, \reg 183 ldo R%\value(\reg), \reg 184 .endm 185 186 .macro loadgp 187 #ifdef CONFIG_64BIT 188 ldil L%__gp, %r27 189 ldo R%__gp(%r27), %r27 190 #else 191 ldil L%$global$, %r27 192 ldo R%$global$(%r27), %r27 193 #endif 194 .endm 195 196 #define SAVE_SP(r, where) mfsp r, %r1 ! STREG %r1, where 197 #define REST_SP(r, where) LDREG where, %r1 ! mtsp %r1, r 198 #define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where 199 #define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r 200 201 .macro save_general regs 202 STREG %r1, PT_GR1 (\regs) 203 STREG %r2, PT_GR2 (\regs) 204 STREG %r3, PT_GR3 (\regs) 205 STREG %r4, PT_GR4 (\regs) 206 STREG %r5, PT_GR5 (\regs) 207 STREG %r6, PT_GR6 (\regs) 208 STREG %r7, PT_GR7 (\regs) 209 STREG %r8, PT_GR8 (\regs) 210 STREG %r9, PT_GR9 (\regs) 211 STREG %r10, PT_GR10(\regs) 212 STREG %r11, PT_GR11(\regs) 213 STREG %r12, PT_GR12(\regs) 214 STREG %r13, PT_GR13(\regs) 215 STREG %r14, PT_GR14(\regs) 216 STREG %r15, PT_GR15(\regs) 217 STREG %r16, PT_GR16(\regs) 218 STREG %r17, PT_GR17(\regs) 219 STREG %r18, PT_GR18(\regs) 220 STREG %r19, PT_GR19(\regs) 221 STREG %r20, PT_GR20(\regs) 222 STREG %r21, PT_GR21(\regs) 223 STREG %r22, PT_GR22(\regs) 224 STREG %r23, PT_GR23(\regs) 225 STREG %r24, PT_GR24(\regs) 226 STREG %r25, PT_GR25(\regs) 227 /* r26 is saved in get_stack and used to preserve a value across virt_map */ 228 STREG %r27, PT_GR27(\regs) 229 STREG %r28, PT_GR28(\regs) 230 /* r29 is saved in get_stack and used to point to saved registers */ 231 /* r30 stack pointer saved in get_stack */ 232 STREG %r31, PT_GR31(\regs) 233 .endm 234 235 .macro rest_general regs 236 /* r1 used as a temp in rest_stack and is restored there */ 237 LDREG PT_GR2 (\regs), %r2 238 LDREG PT_GR3 (\regs), %r3 239 LDREG PT_GR4 (\regs), %r4 240 LDREG PT_GR5 (\regs), %r5 241 LDREG PT_GR6 (\regs), %r6 242 LDREG PT_GR7 (\regs), %r7 243 LDREG PT_GR8 (\regs), %r8 244 LDREG PT_GR9 (\regs), %r9 245 LDREG PT_GR10(\regs), %r10 246 LDREG PT_GR11(\regs), %r11 247 LDREG PT_GR12(\regs), %r12 248 LDREG PT_GR13(\regs), %r13 249 LDREG PT_GR14(\regs), %r14 250 LDREG PT_GR15(\regs), %r15 251 LDREG PT_GR16(\regs), %r16 252 LDREG PT_GR17(\regs), %r17 253 LDREG PT_GR18(\regs), %r18 254 LDREG PT_GR19(\regs), %r19 255 LDREG PT_GR20(\regs), %r20 256 LDREG PT_GR21(\regs), %r21 257 LDREG PT_GR22(\regs), %r22 258 LDREG PT_GR23(\regs), %r23 259 LDREG PT_GR24(\regs), %r24 260 LDREG PT_GR25(\regs), %r25 261 LDREG PT_GR26(\regs), %r26 262 LDREG PT_GR27(\regs), %r27 263 LDREG PT_GR28(\regs), %r28 264 /* r29 points to register save area, and is restored in rest_stack */ 265 /* r30 stack pointer restored in rest_stack */ 266 LDREG PT_GR31(\regs), %r31 267 .endm 268 269 .macro save_fp regs 270 fstd,ma %fr0, 8(\regs) 271 fstd,ma %fr1, 8(\regs) 272 fstd,ma %fr2, 8(\regs) 273 fstd,ma %fr3, 8(\regs) 274 fstd,ma %fr4, 8(\regs) 275 fstd,ma %fr5, 8(\regs) 276 fstd,ma %fr6, 8(\regs) 277 fstd,ma %fr7, 8(\regs) 278 fstd,ma %fr8, 8(\regs) 279 fstd,ma %fr9, 8(\regs) 280 fstd,ma %fr10, 8(\regs) 281 fstd,ma %fr11, 8(\regs) 282 fstd,ma %fr12, 8(\regs) 283 fstd,ma %fr13, 8(\regs) 284 fstd,ma %fr14, 8(\regs) 285 fstd,ma %fr15, 8(\regs) 286 fstd,ma %fr16, 8(\regs) 287 fstd,ma %fr17, 8(\regs) 288 fstd,ma %fr18, 8(\regs) 289 fstd,ma %fr19, 8(\regs) 290 fstd,ma %fr20, 8(\regs) 291 fstd,ma %fr21, 8(\regs) 292 fstd,ma %fr22, 8(\regs) 293 fstd,ma %fr23, 8(\regs) 294 fstd,ma %fr24, 8(\regs) 295 fstd,ma %fr25, 8(\regs) 296 fstd,ma %fr26, 8(\regs) 297 fstd,ma %fr27, 8(\regs) 298 fstd,ma %fr28, 8(\regs) 299 fstd,ma %fr29, 8(\regs) 300 fstd,ma %fr30, 8(\regs) 301 fstd %fr31, 0(\regs) 302 .endm 303 304 .macro rest_fp regs 305 fldd 0(\regs), %fr31 306 fldd,mb -8(\regs), %fr30 307 fldd,mb -8(\regs), %fr29 308 fldd,mb -8(\regs), %fr28 309 fldd,mb -8(\regs), %fr27 310 fldd,mb -8(\regs), %fr26 311 fldd,mb -8(\regs), %fr25 312 fldd,mb -8(\regs), %fr24 313 fldd,mb -8(\regs), %fr23 314 fldd,mb -8(\regs), %fr22 315 fldd,mb -8(\regs), %fr21 316 fldd,mb -8(\regs), %fr20 317 fldd,mb -8(\regs), %fr19 318 fldd,mb -8(\regs), %fr18 319 fldd,mb -8(\regs), %fr17 320 fldd,mb -8(\regs), %fr16 321 fldd,mb -8(\regs), %fr15 322 fldd,mb -8(\regs), %fr14 323 fldd,mb -8(\regs), %fr13 324 fldd,mb -8(\regs), %fr12 325 fldd,mb -8(\regs), %fr11 326 fldd,mb -8(\regs), %fr10 327 fldd,mb -8(\regs), %fr9 328 fldd,mb -8(\regs), %fr8 329 fldd,mb -8(\regs), %fr7 330 fldd,mb -8(\regs), %fr6 331 fldd,mb -8(\regs), %fr5 332 fldd,mb -8(\regs), %fr4 333 fldd,mb -8(\regs), %fr3 334 fldd,mb -8(\regs), %fr2 335 fldd,mb -8(\regs), %fr1 336 fldd,mb -8(\regs), %fr0 337 .endm 338 339 .macro callee_save_float 340 fstd,ma %fr12, 8(%r30) 341 fstd,ma %fr13, 8(%r30) 342 fstd,ma %fr14, 8(%r30) 343 fstd,ma %fr15, 8(%r30) 344 fstd,ma %fr16, 8(%r30) 345 fstd,ma %fr17, 8(%r30) 346 fstd,ma %fr18, 8(%r30) 347 fstd,ma %fr19, 8(%r30) 348 fstd,ma %fr20, 8(%r30) 349 fstd,ma %fr21, 8(%r30) 350 .endm 351 352 .macro callee_rest_float 353 fldd,mb -8(%r30), %fr21 354 fldd,mb -8(%r30), %fr20 355 fldd,mb -8(%r30), %fr19 356 fldd,mb -8(%r30), %fr18 357 fldd,mb -8(%r30), %fr17 358 fldd,mb -8(%r30), %fr16 359 fldd,mb -8(%r30), %fr15 360 fldd,mb -8(%r30), %fr14 361 fldd,mb -8(%r30), %fr13 362 fldd,mb -8(%r30), %fr12 363 .endm 364 365 #ifdef CONFIG_64BIT 366 .macro callee_save 367 std,ma %r3, CALLEE_REG_FRAME_SIZE(%r30) 368 mfctl %cr27, %r3 369 std %r4, -136(%r30) 370 std %r5, -128(%r30) 371 std %r6, -120(%r30) 372 std %r7, -112(%r30) 373 std %r8, -104(%r30) 374 std %r9, -96(%r30) 375 std %r10, -88(%r30) 376 std %r11, -80(%r30) 377 std %r12, -72(%r30) 378 std %r13, -64(%r30) 379 std %r14, -56(%r30) 380 std %r15, -48(%r30) 381 std %r16, -40(%r30) 382 std %r17, -32(%r30) 383 std %r18, -24(%r30) 384 std %r3, -16(%r30) 385 .endm 386 387 .macro callee_rest 388 ldd -16(%r30), %r3 389 ldd -24(%r30), %r18 390 ldd -32(%r30), %r17 391 ldd -40(%r30), %r16 392 ldd -48(%r30), %r15 393 ldd -56(%r30), %r14 394 ldd -64(%r30), %r13 395 ldd -72(%r30), %r12 396 ldd -80(%r30), %r11 397 ldd -88(%r30), %r10 398 ldd -96(%r30), %r9 399 ldd -104(%r30), %r8 400 ldd -112(%r30), %r7 401 ldd -120(%r30), %r6 402 ldd -128(%r30), %r5 403 ldd -136(%r30), %r4 404 mtctl %r3, %cr27 405 ldd,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3 406 .endm 407 408 #else /* ! CONFIG_64BIT */ 409 410 .macro callee_save 411 stw,ma %r3, CALLEE_REG_FRAME_SIZE(%r30) 412 mfctl %cr27, %r3 413 stw %r4, -124(%r30) 414 stw %r5, -120(%r30) 415 stw %r6, -116(%r30) 416 stw %r7, -112(%r30) 417 stw %r8, -108(%r30) 418 stw %r9, -104(%r30) 419 stw %r10, -100(%r30) 420 stw %r11, -96(%r30) 421 stw %r12, -92(%r30) 422 stw %r13, -88(%r30) 423 stw %r14, -84(%r30) 424 stw %r15, -80(%r30) 425 stw %r16, -76(%r30) 426 stw %r17, -72(%r30) 427 stw %r18, -68(%r30) 428 stw %r3, -64(%r30) 429 .endm 430 431 .macro callee_rest 432 ldw -64(%r30), %r3 433 ldw -68(%r30), %r18 434 ldw -72(%r30), %r17 435 ldw -76(%r30), %r16 436 ldw -80(%r30), %r15 437 ldw -84(%r30), %r14 438 ldw -88(%r30), %r13 439 ldw -92(%r30), %r12 440 ldw -96(%r30), %r11 441 ldw -100(%r30), %r10 442 ldw -104(%r30), %r9 443 ldw -108(%r30), %r8 444 ldw -112(%r30), %r7 445 ldw -116(%r30), %r6 446 ldw -120(%r30), %r5 447 ldw -124(%r30), %r4 448 mtctl %r3, %cr27 449 ldw,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3 450 .endm 451 #endif /* ! CONFIG_64BIT */ 452 453 .macro save_specials regs 454 455 SAVE_SP (%sr0, PT_SR0 (\regs)) 456 SAVE_SP (%sr1, PT_SR1 (\regs)) 457 SAVE_SP (%sr2, PT_SR2 (\regs)) 458 SAVE_SP (%sr3, PT_SR3 (\regs)) 459 SAVE_SP (%sr4, PT_SR4 (\regs)) 460 SAVE_SP (%sr5, PT_SR5 (\regs)) 461 SAVE_SP (%sr6, PT_SR6 (\regs)) 462 463 SAVE_CR (%cr17, PT_IASQ0(\regs)) 464 mtctl %r0, %cr17 465 SAVE_CR (%cr17, PT_IASQ1(\regs)) 466 467 SAVE_CR (%cr18, PT_IAOQ0(\regs)) 468 mtctl %r0, %cr18 469 SAVE_CR (%cr18, PT_IAOQ1(\regs)) 470 471 #ifdef CONFIG_64BIT 472 /* cr11 (sar) is a funny one. 5 bits on PA1.1 and 6 bit on PA2.0 473 * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only 474 * reads 5 bits. Use mfctl,w to read all six bits. Otherwise 475 * we lose the 6th bit on a save/restore over interrupt. 476 */ 477 mfctl,w %cr11, %r1 478 STREG %r1, PT_SAR (\regs) 479 #else 480 SAVE_CR (%cr11, PT_SAR (\regs)) 481 #endif 482 SAVE_CR (%cr19, PT_IIR (\regs)) 483 484 /* 485 * Code immediately following this macro (in intr_save) relies 486 * on r8 containing ipsw. 487 */ 488 mfctl %cr22, %r8 489 STREG %r8, PT_PSW(\regs) 490 .endm 491 492 .macro rest_specials regs 493 494 REST_SP (%sr0, PT_SR0 (\regs)) 495 REST_SP (%sr1, PT_SR1 (\regs)) 496 REST_SP (%sr2, PT_SR2 (\regs)) 497 REST_SP (%sr3, PT_SR3 (\regs)) 498 REST_SP (%sr4, PT_SR4 (\regs)) 499 REST_SP (%sr5, PT_SR5 (\regs)) 500 REST_SP (%sr6, PT_SR6 (\regs)) 501 REST_SP (%sr7, PT_SR7 (\regs)) 502 503 REST_CR (%cr17, PT_IASQ0(\regs)) 504 REST_CR (%cr17, PT_IASQ1(\regs)) 505 506 REST_CR (%cr18, PT_IAOQ0(\regs)) 507 REST_CR (%cr18, PT_IAOQ1(\regs)) 508 509 REST_CR (%cr11, PT_SAR (\regs)) 510 511 REST_CR (%cr22, PT_PSW (\regs)) 512 .endm 513 514 515 /* First step to create a "relied upon translation" 516 * See PA 2.0 Arch. page F-4 and F-5. 517 * 518 * The ssm was originally necessary due to a "PCxT bug". 519 * But someone decided it needed to be added to the architecture 520 * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual. 521 * It's been carried forward into PA 2.0 Arch as well. :^( 522 * 523 * "ssm 0,%r0" is a NOP with side effects (prefetch barrier). 524 * rsm/ssm prevents the ifetch unit from speculatively fetching 525 * instructions past this line in the code stream. 526 * PA 2.0 processor will single step all insn in the same QUAD (4 insn). 527 */ 528 .macro pcxt_ssm_bug 529 rsm PSW_SM_I,%r0 530 nop /* 1 */ 531 nop /* 2 */ 532 nop /* 3 */ 533 nop /* 4 */ 534 nop /* 5 */ 535 nop /* 6 */ 536 nop /* 7 */ 537 .endm 538 539 /* Switch to virtual mapping, trashing only %r1 */ 540 .macro virt_map 541 /* pcxt_ssm_bug */ 542 rsm PSW_SM_I, %r0 /* barrier for "Relied upon Translation */ 543 mtsp %r0, %sr4 544 mtsp %r0, %sr5 545 mtsp %r0, %sr6 546 tovirt_r1 %r29 547 load32 KERNEL_PSW, %r1 548 549 rsm PSW_SM_QUIET,%r0 /* second "heavy weight" ctl op */ 550 mtctl %r0, %cr17 /* Clear IIASQ tail */ 551 mtctl %r0, %cr17 /* Clear IIASQ head */ 552 mtctl %r1, %ipsw 553 load32 4f, %r1 554 mtctl %r1, %cr18 /* Set IIAOQ tail */ 555 ldo 4(%r1), %r1 556 mtctl %r1, %cr18 /* Set IIAOQ head */ 557 rfir 558 nop 559 4: 560 .endm 561 562 563 /* 564 * ASM_EXCEPTIONTABLE_ENTRY 565 * 566 * Creates an exception table entry. 567 * Do not convert to a assembler macro. This won't work. 568 */ 569 #define ASM_EXCEPTIONTABLE_ENTRY(fault_addr, except_addr) \ 570 .section __ex_table,"aw" ! \ 571 .word (fault_addr - .), (except_addr - .) ! \ 572 .previous 573 574 575 #endif /* __ASSEMBLY__ */ 576 #endif 577