1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand) 4 * Copyright (C) 1999 Philipp Rumpf <prumpf@tux.org> 5 * Copyright (C) 1999 SuSE GmbH 6 */ 7 8 #ifndef _PARISC_ASSEMBLY_H 9 #define _PARISC_ASSEMBLY_H 10 11 #define CALLEE_FLOAT_FRAME_SIZE 80 12 13 #ifdef CONFIG_64BIT 14 #define LDREG ldd 15 #define STREG std 16 #define LDREGX ldd,s 17 #define LDREGM ldd,mb 18 #define STREGM std,ma 19 #define SHRREG shrd 20 #define SHLREG shld 21 #define ANDCM andcm,* 22 #define COND(x) * ## x 23 #define RP_OFFSET 16 24 #define FRAME_SIZE 128 25 #define CALLEE_REG_FRAME_SIZE 144 26 #define REG_SZ 8 27 #define ASM_ULONG_INSN .dword 28 #else /* CONFIG_64BIT */ 29 #define LDREG ldw 30 #define STREG stw 31 #define LDREGX ldwx,s 32 #define LDREGM ldwm 33 #define STREGM stwm 34 #define SHRREG shr 35 #define SHLREG shlw 36 #define ANDCM andcm 37 #define COND(x) x 38 #define RP_OFFSET 20 39 #define FRAME_SIZE 64 40 #define CALLEE_REG_FRAME_SIZE 128 41 #define REG_SZ 4 42 #define ASM_ULONG_INSN .word 43 #endif 44 45 /* Frame alignment for 32- and 64-bit */ 46 #define FRAME_ALIGN 64 47 48 #define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE) 49 50 #ifdef CONFIG_PA20 51 #define LDCW ldcw,co 52 #define BL b,l 53 # ifdef CONFIG_64BIT 54 # define PA_ASM_LEVEL 2.0w 55 # else 56 # define PA_ASM_LEVEL 2.0 57 # endif 58 #else 59 #define LDCW ldcw 60 #define BL bl 61 #define PA_ASM_LEVEL 1.1 62 #endif 63 64 /* Privilege level field in the rightmost two bits of the IA queues */ 65 #define PRIV_USER 3 66 #define PRIV_KERNEL 0 67 68 #ifdef __ASSEMBLY__ 69 70 #ifdef CONFIG_64BIT 71 /* the 64-bit pa gnu assembler unfortunately defaults to .level 1.1 or 2.0 so 72 * work around that for now... */ 73 .level 2.0w 74 #endif 75 76 #include <asm/asm-offsets.h> 77 #include <asm/page.h> 78 #include <asm/types.h> 79 80 #include <asm/asmregs.h> 81 #include <asm/psw.h> 82 83 sp = 30 84 gp = 27 85 ipsw = 22 86 87 /* 88 * We provide two versions of each macro to convert from physical 89 * to virtual and vice versa. The "_r1" versions take one argument 90 * register, but trashes r1 to do the conversion. The other 91 * version takes two arguments: a src and destination register. 92 * However, the source and destination registers can not be 93 * the same register. 94 */ 95 96 .macro tophys grvirt, grphys 97 ldil L%(__PAGE_OFFSET), \grphys 98 sub \grvirt, \grphys, \grphys 99 .endm 100 101 .macro tovirt grphys, grvirt 102 ldil L%(__PAGE_OFFSET), \grvirt 103 add \grphys, \grvirt, \grvirt 104 .endm 105 106 .macro tophys_r1 gr 107 ldil L%(__PAGE_OFFSET), %r1 108 sub \gr, %r1, \gr 109 .endm 110 111 .macro tovirt_r1 gr 112 ldil L%(__PAGE_OFFSET), %r1 113 add \gr, %r1, \gr 114 .endm 115 116 .macro delay value 117 ldil L%\value, 1 118 ldo R%\value(1), 1 119 addib,UV,n -1,1,. 120 addib,NUV,n -1,1,.+8 121 nop 122 .endm 123 124 .macro debug value 125 .endm 126 127 .macro shlw r, sa, t 128 zdep \r, 31-(\sa), 32-(\sa), \t 129 .endm 130 131 /* And the PA 2.0W shift left */ 132 .macro shld r, sa, t 133 depd,z \r, 63-(\sa), 64-(\sa), \t 134 .endm 135 136 /* Shift Right - note the r and t can NOT be the same! */ 137 .macro shr r, sa, t 138 extru \r, 31-(\sa), 32-(\sa), \t 139 .endm 140 141 /* pa20w version of shift right */ 142 .macro shrd r, sa, t 143 extrd,u \r, 63-(\sa), 64-(\sa), \t 144 .endm 145 146 /* load 32-bit 'value' into 'reg' compensating for the ldil 147 * sign-extension when running in wide mode. 148 * WARNING!! neither 'value' nor 'reg' can be expressions 149 * containing '.'!!!! */ 150 .macro load32 value, reg 151 ldil L%\value, \reg 152 ldo R%\value(\reg), \reg 153 .endm 154 155 .macro loadgp 156 #ifdef CONFIG_64BIT 157 ldil L%__gp, %r27 158 ldo R%__gp(%r27), %r27 159 #else 160 ldil L%$global$, %r27 161 ldo R%$global$(%r27), %r27 162 #endif 163 .endm 164 165 #define SAVE_SP(r, where) mfsp r, %r1 ! STREG %r1, where 166 #define REST_SP(r, where) LDREG where, %r1 ! mtsp %r1, r 167 #define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where 168 #define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r 169 170 .macro save_general regs 171 STREG %r1, PT_GR1 (\regs) 172 STREG %r2, PT_GR2 (\regs) 173 STREG %r3, PT_GR3 (\regs) 174 STREG %r4, PT_GR4 (\regs) 175 STREG %r5, PT_GR5 (\regs) 176 STREG %r6, PT_GR6 (\regs) 177 STREG %r7, PT_GR7 (\regs) 178 STREG %r8, PT_GR8 (\regs) 179 STREG %r9, PT_GR9 (\regs) 180 STREG %r10, PT_GR10(\regs) 181 STREG %r11, PT_GR11(\regs) 182 STREG %r12, PT_GR12(\regs) 183 STREG %r13, PT_GR13(\regs) 184 STREG %r14, PT_GR14(\regs) 185 STREG %r15, PT_GR15(\regs) 186 STREG %r16, PT_GR16(\regs) 187 STREG %r17, PT_GR17(\regs) 188 STREG %r18, PT_GR18(\regs) 189 STREG %r19, PT_GR19(\regs) 190 STREG %r20, PT_GR20(\regs) 191 STREG %r21, PT_GR21(\regs) 192 STREG %r22, PT_GR22(\regs) 193 STREG %r23, PT_GR23(\regs) 194 STREG %r24, PT_GR24(\regs) 195 STREG %r25, PT_GR25(\regs) 196 /* r26 is saved in get_stack and used to preserve a value across virt_map */ 197 STREG %r27, PT_GR27(\regs) 198 STREG %r28, PT_GR28(\regs) 199 /* r29 is saved in get_stack and used to point to saved registers */ 200 /* r30 stack pointer saved in get_stack */ 201 STREG %r31, PT_GR31(\regs) 202 .endm 203 204 .macro rest_general regs 205 /* r1 used as a temp in rest_stack and is restored there */ 206 LDREG PT_GR2 (\regs), %r2 207 LDREG PT_GR3 (\regs), %r3 208 LDREG PT_GR4 (\regs), %r4 209 LDREG PT_GR5 (\regs), %r5 210 LDREG PT_GR6 (\regs), %r6 211 LDREG PT_GR7 (\regs), %r7 212 LDREG PT_GR8 (\regs), %r8 213 LDREG PT_GR9 (\regs), %r9 214 LDREG PT_GR10(\regs), %r10 215 LDREG PT_GR11(\regs), %r11 216 LDREG PT_GR12(\regs), %r12 217 LDREG PT_GR13(\regs), %r13 218 LDREG PT_GR14(\regs), %r14 219 LDREG PT_GR15(\regs), %r15 220 LDREG PT_GR16(\regs), %r16 221 LDREG PT_GR17(\regs), %r17 222 LDREG PT_GR18(\regs), %r18 223 LDREG PT_GR19(\regs), %r19 224 LDREG PT_GR20(\regs), %r20 225 LDREG PT_GR21(\regs), %r21 226 LDREG PT_GR22(\regs), %r22 227 LDREG PT_GR23(\regs), %r23 228 LDREG PT_GR24(\regs), %r24 229 LDREG PT_GR25(\regs), %r25 230 LDREG PT_GR26(\regs), %r26 231 LDREG PT_GR27(\regs), %r27 232 LDREG PT_GR28(\regs), %r28 233 /* r29 points to register save area, and is restored in rest_stack */ 234 /* r30 stack pointer restored in rest_stack */ 235 LDREG PT_GR31(\regs), %r31 236 .endm 237 238 .macro save_fp regs 239 fstd,ma %fr0, 8(\regs) 240 fstd,ma %fr1, 8(\regs) 241 fstd,ma %fr2, 8(\regs) 242 fstd,ma %fr3, 8(\regs) 243 fstd,ma %fr4, 8(\regs) 244 fstd,ma %fr5, 8(\regs) 245 fstd,ma %fr6, 8(\regs) 246 fstd,ma %fr7, 8(\regs) 247 fstd,ma %fr8, 8(\regs) 248 fstd,ma %fr9, 8(\regs) 249 fstd,ma %fr10, 8(\regs) 250 fstd,ma %fr11, 8(\regs) 251 fstd,ma %fr12, 8(\regs) 252 fstd,ma %fr13, 8(\regs) 253 fstd,ma %fr14, 8(\regs) 254 fstd,ma %fr15, 8(\regs) 255 fstd,ma %fr16, 8(\regs) 256 fstd,ma %fr17, 8(\regs) 257 fstd,ma %fr18, 8(\regs) 258 fstd,ma %fr19, 8(\regs) 259 fstd,ma %fr20, 8(\regs) 260 fstd,ma %fr21, 8(\regs) 261 fstd,ma %fr22, 8(\regs) 262 fstd,ma %fr23, 8(\regs) 263 fstd,ma %fr24, 8(\regs) 264 fstd,ma %fr25, 8(\regs) 265 fstd,ma %fr26, 8(\regs) 266 fstd,ma %fr27, 8(\regs) 267 fstd,ma %fr28, 8(\regs) 268 fstd,ma %fr29, 8(\regs) 269 fstd,ma %fr30, 8(\regs) 270 fstd %fr31, 0(\regs) 271 .endm 272 273 .macro rest_fp regs 274 fldd 0(\regs), %fr31 275 fldd,mb -8(\regs), %fr30 276 fldd,mb -8(\regs), %fr29 277 fldd,mb -8(\regs), %fr28 278 fldd,mb -8(\regs), %fr27 279 fldd,mb -8(\regs), %fr26 280 fldd,mb -8(\regs), %fr25 281 fldd,mb -8(\regs), %fr24 282 fldd,mb -8(\regs), %fr23 283 fldd,mb -8(\regs), %fr22 284 fldd,mb -8(\regs), %fr21 285 fldd,mb -8(\regs), %fr20 286 fldd,mb -8(\regs), %fr19 287 fldd,mb -8(\regs), %fr18 288 fldd,mb -8(\regs), %fr17 289 fldd,mb -8(\regs), %fr16 290 fldd,mb -8(\regs), %fr15 291 fldd,mb -8(\regs), %fr14 292 fldd,mb -8(\regs), %fr13 293 fldd,mb -8(\regs), %fr12 294 fldd,mb -8(\regs), %fr11 295 fldd,mb -8(\regs), %fr10 296 fldd,mb -8(\regs), %fr9 297 fldd,mb -8(\regs), %fr8 298 fldd,mb -8(\regs), %fr7 299 fldd,mb -8(\regs), %fr6 300 fldd,mb -8(\regs), %fr5 301 fldd,mb -8(\regs), %fr4 302 fldd,mb -8(\regs), %fr3 303 fldd,mb -8(\regs), %fr2 304 fldd,mb -8(\regs), %fr1 305 fldd,mb -8(\regs), %fr0 306 .endm 307 308 .macro callee_save_float 309 fstd,ma %fr12, 8(%r30) 310 fstd,ma %fr13, 8(%r30) 311 fstd,ma %fr14, 8(%r30) 312 fstd,ma %fr15, 8(%r30) 313 fstd,ma %fr16, 8(%r30) 314 fstd,ma %fr17, 8(%r30) 315 fstd,ma %fr18, 8(%r30) 316 fstd,ma %fr19, 8(%r30) 317 fstd,ma %fr20, 8(%r30) 318 fstd,ma %fr21, 8(%r30) 319 .endm 320 321 .macro callee_rest_float 322 fldd,mb -8(%r30), %fr21 323 fldd,mb -8(%r30), %fr20 324 fldd,mb -8(%r30), %fr19 325 fldd,mb -8(%r30), %fr18 326 fldd,mb -8(%r30), %fr17 327 fldd,mb -8(%r30), %fr16 328 fldd,mb -8(%r30), %fr15 329 fldd,mb -8(%r30), %fr14 330 fldd,mb -8(%r30), %fr13 331 fldd,mb -8(%r30), %fr12 332 .endm 333 334 #ifdef CONFIG_64BIT 335 .macro callee_save 336 std,ma %r3, CALLEE_REG_FRAME_SIZE(%r30) 337 mfctl %cr27, %r3 338 std %r4, -136(%r30) 339 std %r5, -128(%r30) 340 std %r6, -120(%r30) 341 std %r7, -112(%r30) 342 std %r8, -104(%r30) 343 std %r9, -96(%r30) 344 std %r10, -88(%r30) 345 std %r11, -80(%r30) 346 std %r12, -72(%r30) 347 std %r13, -64(%r30) 348 std %r14, -56(%r30) 349 std %r15, -48(%r30) 350 std %r16, -40(%r30) 351 std %r17, -32(%r30) 352 std %r18, -24(%r30) 353 std %r3, -16(%r30) 354 .endm 355 356 .macro callee_rest 357 ldd -16(%r30), %r3 358 ldd -24(%r30), %r18 359 ldd -32(%r30), %r17 360 ldd -40(%r30), %r16 361 ldd -48(%r30), %r15 362 ldd -56(%r30), %r14 363 ldd -64(%r30), %r13 364 ldd -72(%r30), %r12 365 ldd -80(%r30), %r11 366 ldd -88(%r30), %r10 367 ldd -96(%r30), %r9 368 ldd -104(%r30), %r8 369 ldd -112(%r30), %r7 370 ldd -120(%r30), %r6 371 ldd -128(%r30), %r5 372 ldd -136(%r30), %r4 373 mtctl %r3, %cr27 374 ldd,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3 375 .endm 376 377 #else /* ! CONFIG_64BIT */ 378 379 .macro callee_save 380 stw,ma %r3, CALLEE_REG_FRAME_SIZE(%r30) 381 mfctl %cr27, %r3 382 stw %r4, -124(%r30) 383 stw %r5, -120(%r30) 384 stw %r6, -116(%r30) 385 stw %r7, -112(%r30) 386 stw %r8, -108(%r30) 387 stw %r9, -104(%r30) 388 stw %r10, -100(%r30) 389 stw %r11, -96(%r30) 390 stw %r12, -92(%r30) 391 stw %r13, -88(%r30) 392 stw %r14, -84(%r30) 393 stw %r15, -80(%r30) 394 stw %r16, -76(%r30) 395 stw %r17, -72(%r30) 396 stw %r18, -68(%r30) 397 stw %r3, -64(%r30) 398 .endm 399 400 .macro callee_rest 401 ldw -64(%r30), %r3 402 ldw -68(%r30), %r18 403 ldw -72(%r30), %r17 404 ldw -76(%r30), %r16 405 ldw -80(%r30), %r15 406 ldw -84(%r30), %r14 407 ldw -88(%r30), %r13 408 ldw -92(%r30), %r12 409 ldw -96(%r30), %r11 410 ldw -100(%r30), %r10 411 ldw -104(%r30), %r9 412 ldw -108(%r30), %r8 413 ldw -112(%r30), %r7 414 ldw -116(%r30), %r6 415 ldw -120(%r30), %r5 416 ldw -124(%r30), %r4 417 mtctl %r3, %cr27 418 ldw,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3 419 .endm 420 #endif /* ! CONFIG_64BIT */ 421 422 .macro save_specials regs 423 424 SAVE_SP (%sr0, PT_SR0 (\regs)) 425 SAVE_SP (%sr1, PT_SR1 (\regs)) 426 SAVE_SP (%sr2, PT_SR2 (\regs)) 427 SAVE_SP (%sr3, PT_SR3 (\regs)) 428 SAVE_SP (%sr4, PT_SR4 (\regs)) 429 SAVE_SP (%sr5, PT_SR5 (\regs)) 430 SAVE_SP (%sr6, PT_SR6 (\regs)) 431 432 SAVE_CR (%cr17, PT_IASQ0(\regs)) 433 mtctl %r0, %cr17 434 SAVE_CR (%cr17, PT_IASQ1(\regs)) 435 436 SAVE_CR (%cr18, PT_IAOQ0(\regs)) 437 mtctl %r0, %cr18 438 SAVE_CR (%cr18, PT_IAOQ1(\regs)) 439 440 #ifdef CONFIG_64BIT 441 /* cr11 (sar) is a funny one. 5 bits on PA1.1 and 6 bit on PA2.0 442 * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only 443 * reads 5 bits. Use mfctl,w to read all six bits. Otherwise 444 * we lose the 6th bit on a save/restore over interrupt. 445 */ 446 mfctl,w %cr11, %r1 447 STREG %r1, PT_SAR (\regs) 448 #else 449 SAVE_CR (%cr11, PT_SAR (\regs)) 450 #endif 451 SAVE_CR (%cr19, PT_IIR (\regs)) 452 453 /* 454 * Code immediately following this macro (in intr_save) relies 455 * on r8 containing ipsw. 456 */ 457 mfctl %cr22, %r8 458 STREG %r8, PT_PSW(\regs) 459 .endm 460 461 .macro rest_specials regs 462 463 REST_SP (%sr0, PT_SR0 (\regs)) 464 REST_SP (%sr1, PT_SR1 (\regs)) 465 REST_SP (%sr2, PT_SR2 (\regs)) 466 REST_SP (%sr3, PT_SR3 (\regs)) 467 REST_SP (%sr4, PT_SR4 (\regs)) 468 REST_SP (%sr5, PT_SR5 (\regs)) 469 REST_SP (%sr6, PT_SR6 (\regs)) 470 REST_SP (%sr7, PT_SR7 (\regs)) 471 472 REST_CR (%cr17, PT_IASQ0(\regs)) 473 REST_CR (%cr17, PT_IASQ1(\regs)) 474 475 REST_CR (%cr18, PT_IAOQ0(\regs)) 476 REST_CR (%cr18, PT_IAOQ1(\regs)) 477 478 REST_CR (%cr11, PT_SAR (\regs)) 479 480 REST_CR (%cr22, PT_PSW (\regs)) 481 .endm 482 483 484 /* First step to create a "relied upon translation" 485 * See PA 2.0 Arch. page F-4 and F-5. 486 * 487 * The ssm was originally necessary due to a "PCxT bug". 488 * But someone decided it needed to be added to the architecture 489 * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual. 490 * It's been carried forward into PA 2.0 Arch as well. :^( 491 * 492 * "ssm 0,%r0" is a NOP with side effects (prefetch barrier). 493 * rsm/ssm prevents the ifetch unit from speculatively fetching 494 * instructions past this line in the code stream. 495 * PA 2.0 processor will single step all insn in the same QUAD (4 insn). 496 */ 497 .macro pcxt_ssm_bug 498 rsm PSW_SM_I,%r0 499 nop /* 1 */ 500 nop /* 2 */ 501 nop /* 3 */ 502 nop /* 4 */ 503 nop /* 5 */ 504 nop /* 6 */ 505 nop /* 7 */ 506 .endm 507 508 /* Switch to virtual mapping, trashing only %r1 */ 509 .macro virt_map 510 /* pcxt_ssm_bug */ 511 rsm PSW_SM_I, %r0 /* barrier for "Relied upon Translation */ 512 mtsp %r0, %sr4 513 mtsp %r0, %sr5 514 mtsp %r0, %sr6 515 tovirt_r1 %r29 516 load32 KERNEL_PSW, %r1 517 518 rsm PSW_SM_QUIET,%r0 /* second "heavy weight" ctl op */ 519 mtctl %r0, %cr17 /* Clear IIASQ tail */ 520 mtctl %r0, %cr17 /* Clear IIASQ head */ 521 mtctl %r1, %ipsw 522 load32 4f, %r1 523 mtctl %r1, %cr18 /* Set IIAOQ tail */ 524 ldo 4(%r1), %r1 525 mtctl %r1, %cr18 /* Set IIAOQ head */ 526 rfir 527 nop 528 4: 529 .endm 530 531 532 /* 533 * ASM_EXCEPTIONTABLE_ENTRY 534 * 535 * Creates an exception table entry. 536 * Do not convert to a assembler macro. This won't work. 537 */ 538 #define ASM_EXCEPTIONTABLE_ENTRY(fault_addr, except_addr) \ 539 .section __ex_table,"aw" ! \ 540 .word (fault_addr - .), (except_addr - .) ! \ 541 .previous 542 543 544 #endif /* __ASSEMBLY__ */ 545 #endif 546