1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 1999 Hewlett-Packard (Frank Rowand) 4 * Copyright (C) 1999 Philipp Rumpf <prumpf@tux.org> 5 * Copyright (C) 1999 SuSE GmbH 6 * Copyright (C) 2021 Helge Deller <deller@gmx.de> 7 */ 8 9 #ifndef _PARISC_ASSEMBLY_H 10 #define _PARISC_ASSEMBLY_H 11 12 #ifdef CONFIG_64BIT 13 #define RP_OFFSET 16 14 #define FRAME_SIZE 128 15 #define CALLEE_REG_FRAME_SIZE 144 16 #define REG_SZ 8 17 #define ASM_ULONG_INSN .dword 18 #else /* CONFIG_64BIT */ 19 #define RP_OFFSET 20 20 #define FRAME_SIZE 64 21 #define CALLEE_REG_FRAME_SIZE 128 22 #define REG_SZ 4 23 #define ASM_ULONG_INSN .word 24 #endif 25 26 /* Frame alignment for 32- and 64-bit */ 27 #define FRAME_ALIGN 64 28 29 #define CALLEE_FLOAT_FRAME_SIZE 80 30 #define CALLEE_SAVE_FRAME_SIZE (CALLEE_REG_FRAME_SIZE + CALLEE_FLOAT_FRAME_SIZE) 31 32 #ifdef CONFIG_PA20 33 #define LDCW ldcw,co 34 #define BL b,l 35 # ifdef CONFIG_64BIT 36 # define PA_ASM_LEVEL 2.0w 37 # else 38 # define PA_ASM_LEVEL 2.0 39 # endif 40 #else 41 #define LDCW ldcw 42 #define BL bl 43 #define PA_ASM_LEVEL 1.1 44 #endif 45 46 /* Privilege level field in the rightmost two bits of the IA queues */ 47 #define PRIV_USER 3 48 #define PRIV_KERNEL 0 49 50 #ifdef __ASSEMBLY__ 51 52 #ifdef CONFIG_64BIT 53 #define LDREG ldd 54 #define STREG std 55 #define LDREGX ldd,s 56 #define LDREGM ldd,mb 57 #define STREGM std,ma 58 #define SHRREG shrd 59 #define SHLREG shld 60 #define ANDCM andcm,* 61 #define COND(x) * ## x 62 #else /* CONFIG_64BIT */ 63 #define LDREG ldw 64 #define STREG stw 65 #define LDREGX ldwx,s 66 #define LDREGM ldwm 67 #define STREGM stwm 68 #define SHRREG shr 69 #define SHLREG shlw 70 #define ANDCM andcm 71 #define COND(x) x 72 #endif 73 74 #ifdef CONFIG_64BIT 75 /* the 64-bit pa gnu assembler unfortunately defaults to .level 1.1 or 2.0 so 76 * work around that for now... */ 77 .level 2.0w 78 #endif 79 80 #include <asm/asm-offsets.h> 81 #include <asm/page.h> 82 #include <asm/types.h> 83 84 #include <asm/asmregs.h> 85 #include <asm/psw.h> 86 87 sp = 30 88 gp = 27 89 ipsw = 22 90 91 /* 92 * We provide two versions of each macro to convert from physical 93 * to virtual and vice versa. The "_r1" versions take one argument 94 * register, but trashes r1 to do the conversion. The other 95 * version takes two arguments: a src and destination register. 96 * However, the source and destination registers can not be 97 * the same register. 98 */ 99 100 .macro tophys grvirt, grphys 101 ldil L%(__PAGE_OFFSET), \grphys 102 sub \grvirt, \grphys, \grphys 103 .endm 104 105 .macro tovirt grphys, grvirt 106 ldil L%(__PAGE_OFFSET), \grvirt 107 add \grphys, \grvirt, \grvirt 108 .endm 109 110 .macro tophys_r1 gr 111 ldil L%(__PAGE_OFFSET), %r1 112 sub \gr, %r1, \gr 113 .endm 114 115 .macro tovirt_r1 gr 116 ldil L%(__PAGE_OFFSET), %r1 117 add \gr, %r1, \gr 118 .endm 119 120 .macro delay value 121 ldil L%\value, 1 122 ldo R%\value(1), 1 123 addib,UV,n -1,1,. 124 addib,NUV,n -1,1,.+8 125 nop 126 .endm 127 128 .macro debug value 129 .endm 130 131 .macro shlw r, sa, t 132 zdep \r, 31-(\sa), 32-(\sa), \t 133 .endm 134 135 /* And the PA 2.0W shift left */ 136 .macro shld r, sa, t 137 depd,z \r, 63-(\sa), 64-(\sa), \t 138 .endm 139 140 /* Shift Right - note the r and t can NOT be the same! */ 141 .macro shr r, sa, t 142 extru \r, 31-(\sa), 32-(\sa), \t 143 .endm 144 145 /* pa20w version of shift right */ 146 .macro shrd r, sa, t 147 extrd,u \r, 63-(\sa), 64-(\sa), \t 148 .endm 149 150 /* Extract unsigned for 32- and 64-bit 151 * The extru instruction leaves the most significant 32 bits of the 152 * target register in an undefined state on PA 2.0 systems. */ 153 .macro extru_safe r, p, len, t 154 #ifdef CONFIG_64BIT 155 extrd,u \r, 32+(\p), \len, \t 156 #else 157 extru \r, \p, \len, \t 158 #endif 159 .endm 160 161 /* The depi instruction leaves the most significant 32 bits of the 162 * target register in an undefined state on PA 2.0 systems. */ 163 .macro depi_safe i, p, len, t 164 #ifdef CONFIG_64BIT 165 depdi \i, 32+(\p), \len, \t 166 #else 167 depi \i, \p, \len, \t 168 #endif 169 .endm 170 171 /* load 32-bit 'value' into 'reg' compensating for the ldil 172 * sign-extension when running in wide mode. 173 * WARNING!! neither 'value' nor 'reg' can be expressions 174 * containing '.'!!!! */ 175 .macro load32 value, reg 176 ldil L%\value, \reg 177 ldo R%\value(\reg), \reg 178 .endm 179 180 .macro loadgp 181 #ifdef CONFIG_64BIT 182 ldil L%__gp, %r27 183 ldo R%__gp(%r27), %r27 184 #else 185 ldil L%$global$, %r27 186 ldo R%$global$(%r27), %r27 187 #endif 188 .endm 189 190 #define SAVE_SP(r, where) mfsp r, %r1 ! STREG %r1, where 191 #define REST_SP(r, where) LDREG where, %r1 ! mtsp %r1, r 192 #define SAVE_CR(r, where) mfctl r, %r1 ! STREG %r1, where 193 #define REST_CR(r, where) LDREG where, %r1 ! mtctl %r1, r 194 195 .macro save_general regs 196 STREG %r1, PT_GR1 (\regs) 197 STREG %r2, PT_GR2 (\regs) 198 STREG %r3, PT_GR3 (\regs) 199 STREG %r4, PT_GR4 (\regs) 200 STREG %r5, PT_GR5 (\regs) 201 STREG %r6, PT_GR6 (\regs) 202 STREG %r7, PT_GR7 (\regs) 203 STREG %r8, PT_GR8 (\regs) 204 STREG %r9, PT_GR9 (\regs) 205 STREG %r10, PT_GR10(\regs) 206 STREG %r11, PT_GR11(\regs) 207 STREG %r12, PT_GR12(\regs) 208 STREG %r13, PT_GR13(\regs) 209 STREG %r14, PT_GR14(\regs) 210 STREG %r15, PT_GR15(\regs) 211 STREG %r16, PT_GR16(\regs) 212 STREG %r17, PT_GR17(\regs) 213 STREG %r18, PT_GR18(\regs) 214 STREG %r19, PT_GR19(\regs) 215 STREG %r20, PT_GR20(\regs) 216 STREG %r21, PT_GR21(\regs) 217 STREG %r22, PT_GR22(\regs) 218 STREG %r23, PT_GR23(\regs) 219 STREG %r24, PT_GR24(\regs) 220 STREG %r25, PT_GR25(\regs) 221 /* r26 is saved in get_stack and used to preserve a value across virt_map */ 222 STREG %r27, PT_GR27(\regs) 223 STREG %r28, PT_GR28(\regs) 224 /* r29 is saved in get_stack and used to point to saved registers */ 225 /* r30 stack pointer saved in get_stack */ 226 STREG %r31, PT_GR31(\regs) 227 .endm 228 229 .macro rest_general regs 230 /* r1 used as a temp in rest_stack and is restored there */ 231 LDREG PT_GR2 (\regs), %r2 232 LDREG PT_GR3 (\regs), %r3 233 LDREG PT_GR4 (\regs), %r4 234 LDREG PT_GR5 (\regs), %r5 235 LDREG PT_GR6 (\regs), %r6 236 LDREG PT_GR7 (\regs), %r7 237 LDREG PT_GR8 (\regs), %r8 238 LDREG PT_GR9 (\regs), %r9 239 LDREG PT_GR10(\regs), %r10 240 LDREG PT_GR11(\regs), %r11 241 LDREG PT_GR12(\regs), %r12 242 LDREG PT_GR13(\regs), %r13 243 LDREG PT_GR14(\regs), %r14 244 LDREG PT_GR15(\regs), %r15 245 LDREG PT_GR16(\regs), %r16 246 LDREG PT_GR17(\regs), %r17 247 LDREG PT_GR18(\regs), %r18 248 LDREG PT_GR19(\regs), %r19 249 LDREG PT_GR20(\regs), %r20 250 LDREG PT_GR21(\regs), %r21 251 LDREG PT_GR22(\regs), %r22 252 LDREG PT_GR23(\regs), %r23 253 LDREG PT_GR24(\regs), %r24 254 LDREG PT_GR25(\regs), %r25 255 LDREG PT_GR26(\regs), %r26 256 LDREG PT_GR27(\regs), %r27 257 LDREG PT_GR28(\regs), %r28 258 /* r29 points to register save area, and is restored in rest_stack */ 259 /* r30 stack pointer restored in rest_stack */ 260 LDREG PT_GR31(\regs), %r31 261 .endm 262 263 .macro save_fp regs 264 fstd,ma %fr0, 8(\regs) 265 fstd,ma %fr1, 8(\regs) 266 fstd,ma %fr2, 8(\regs) 267 fstd,ma %fr3, 8(\regs) 268 fstd,ma %fr4, 8(\regs) 269 fstd,ma %fr5, 8(\regs) 270 fstd,ma %fr6, 8(\regs) 271 fstd,ma %fr7, 8(\regs) 272 fstd,ma %fr8, 8(\regs) 273 fstd,ma %fr9, 8(\regs) 274 fstd,ma %fr10, 8(\regs) 275 fstd,ma %fr11, 8(\regs) 276 fstd,ma %fr12, 8(\regs) 277 fstd,ma %fr13, 8(\regs) 278 fstd,ma %fr14, 8(\regs) 279 fstd,ma %fr15, 8(\regs) 280 fstd,ma %fr16, 8(\regs) 281 fstd,ma %fr17, 8(\regs) 282 fstd,ma %fr18, 8(\regs) 283 fstd,ma %fr19, 8(\regs) 284 fstd,ma %fr20, 8(\regs) 285 fstd,ma %fr21, 8(\regs) 286 fstd,ma %fr22, 8(\regs) 287 fstd,ma %fr23, 8(\regs) 288 fstd,ma %fr24, 8(\regs) 289 fstd,ma %fr25, 8(\regs) 290 fstd,ma %fr26, 8(\regs) 291 fstd,ma %fr27, 8(\regs) 292 fstd,ma %fr28, 8(\regs) 293 fstd,ma %fr29, 8(\regs) 294 fstd,ma %fr30, 8(\regs) 295 fstd %fr31, 0(\regs) 296 .endm 297 298 .macro rest_fp regs 299 fldd 0(\regs), %fr31 300 fldd,mb -8(\regs), %fr30 301 fldd,mb -8(\regs), %fr29 302 fldd,mb -8(\regs), %fr28 303 fldd,mb -8(\regs), %fr27 304 fldd,mb -8(\regs), %fr26 305 fldd,mb -8(\regs), %fr25 306 fldd,mb -8(\regs), %fr24 307 fldd,mb -8(\regs), %fr23 308 fldd,mb -8(\regs), %fr22 309 fldd,mb -8(\regs), %fr21 310 fldd,mb -8(\regs), %fr20 311 fldd,mb -8(\regs), %fr19 312 fldd,mb -8(\regs), %fr18 313 fldd,mb -8(\regs), %fr17 314 fldd,mb -8(\regs), %fr16 315 fldd,mb -8(\regs), %fr15 316 fldd,mb -8(\regs), %fr14 317 fldd,mb -8(\regs), %fr13 318 fldd,mb -8(\regs), %fr12 319 fldd,mb -8(\regs), %fr11 320 fldd,mb -8(\regs), %fr10 321 fldd,mb -8(\regs), %fr9 322 fldd,mb -8(\regs), %fr8 323 fldd,mb -8(\regs), %fr7 324 fldd,mb -8(\regs), %fr6 325 fldd,mb -8(\regs), %fr5 326 fldd,mb -8(\regs), %fr4 327 fldd,mb -8(\regs), %fr3 328 fldd,mb -8(\regs), %fr2 329 fldd,mb -8(\regs), %fr1 330 fldd,mb -8(\regs), %fr0 331 .endm 332 333 .macro callee_save_float 334 fstd,ma %fr12, 8(%r30) 335 fstd,ma %fr13, 8(%r30) 336 fstd,ma %fr14, 8(%r30) 337 fstd,ma %fr15, 8(%r30) 338 fstd,ma %fr16, 8(%r30) 339 fstd,ma %fr17, 8(%r30) 340 fstd,ma %fr18, 8(%r30) 341 fstd,ma %fr19, 8(%r30) 342 fstd,ma %fr20, 8(%r30) 343 fstd,ma %fr21, 8(%r30) 344 .endm 345 346 .macro callee_rest_float 347 fldd,mb -8(%r30), %fr21 348 fldd,mb -8(%r30), %fr20 349 fldd,mb -8(%r30), %fr19 350 fldd,mb -8(%r30), %fr18 351 fldd,mb -8(%r30), %fr17 352 fldd,mb -8(%r30), %fr16 353 fldd,mb -8(%r30), %fr15 354 fldd,mb -8(%r30), %fr14 355 fldd,mb -8(%r30), %fr13 356 fldd,mb -8(%r30), %fr12 357 .endm 358 359 #ifdef CONFIG_64BIT 360 .macro callee_save 361 std,ma %r3, CALLEE_REG_FRAME_SIZE(%r30) 362 mfctl %cr27, %r3 363 std %r4, -136(%r30) 364 std %r5, -128(%r30) 365 std %r6, -120(%r30) 366 std %r7, -112(%r30) 367 std %r8, -104(%r30) 368 std %r9, -96(%r30) 369 std %r10, -88(%r30) 370 std %r11, -80(%r30) 371 std %r12, -72(%r30) 372 std %r13, -64(%r30) 373 std %r14, -56(%r30) 374 std %r15, -48(%r30) 375 std %r16, -40(%r30) 376 std %r17, -32(%r30) 377 std %r18, -24(%r30) 378 std %r3, -16(%r30) 379 .endm 380 381 .macro callee_rest 382 ldd -16(%r30), %r3 383 ldd -24(%r30), %r18 384 ldd -32(%r30), %r17 385 ldd -40(%r30), %r16 386 ldd -48(%r30), %r15 387 ldd -56(%r30), %r14 388 ldd -64(%r30), %r13 389 ldd -72(%r30), %r12 390 ldd -80(%r30), %r11 391 ldd -88(%r30), %r10 392 ldd -96(%r30), %r9 393 ldd -104(%r30), %r8 394 ldd -112(%r30), %r7 395 ldd -120(%r30), %r6 396 ldd -128(%r30), %r5 397 ldd -136(%r30), %r4 398 mtctl %r3, %cr27 399 ldd,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3 400 .endm 401 402 #else /* ! CONFIG_64BIT */ 403 404 .macro callee_save 405 stw,ma %r3, CALLEE_REG_FRAME_SIZE(%r30) 406 mfctl %cr27, %r3 407 stw %r4, -124(%r30) 408 stw %r5, -120(%r30) 409 stw %r6, -116(%r30) 410 stw %r7, -112(%r30) 411 stw %r8, -108(%r30) 412 stw %r9, -104(%r30) 413 stw %r10, -100(%r30) 414 stw %r11, -96(%r30) 415 stw %r12, -92(%r30) 416 stw %r13, -88(%r30) 417 stw %r14, -84(%r30) 418 stw %r15, -80(%r30) 419 stw %r16, -76(%r30) 420 stw %r17, -72(%r30) 421 stw %r18, -68(%r30) 422 stw %r3, -64(%r30) 423 .endm 424 425 .macro callee_rest 426 ldw -64(%r30), %r3 427 ldw -68(%r30), %r18 428 ldw -72(%r30), %r17 429 ldw -76(%r30), %r16 430 ldw -80(%r30), %r15 431 ldw -84(%r30), %r14 432 ldw -88(%r30), %r13 433 ldw -92(%r30), %r12 434 ldw -96(%r30), %r11 435 ldw -100(%r30), %r10 436 ldw -104(%r30), %r9 437 ldw -108(%r30), %r8 438 ldw -112(%r30), %r7 439 ldw -116(%r30), %r6 440 ldw -120(%r30), %r5 441 ldw -124(%r30), %r4 442 mtctl %r3, %cr27 443 ldw,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3 444 .endm 445 #endif /* ! CONFIG_64BIT */ 446 447 .macro save_specials regs 448 449 SAVE_SP (%sr0, PT_SR0 (\regs)) 450 SAVE_SP (%sr1, PT_SR1 (\regs)) 451 SAVE_SP (%sr2, PT_SR2 (\regs)) 452 SAVE_SP (%sr3, PT_SR3 (\regs)) 453 SAVE_SP (%sr4, PT_SR4 (\regs)) 454 SAVE_SP (%sr5, PT_SR5 (\regs)) 455 SAVE_SP (%sr6, PT_SR6 (\regs)) 456 457 SAVE_CR (%cr17, PT_IASQ0(\regs)) 458 mtctl %r0, %cr17 459 SAVE_CR (%cr17, PT_IASQ1(\regs)) 460 461 SAVE_CR (%cr18, PT_IAOQ0(\regs)) 462 mtctl %r0, %cr18 463 SAVE_CR (%cr18, PT_IAOQ1(\regs)) 464 465 #ifdef CONFIG_64BIT 466 /* cr11 (sar) is a funny one. 5 bits on PA1.1 and 6 bit on PA2.0 467 * For PA2.0 mtsar or mtctl always write 6 bits, but mfctl only 468 * reads 5 bits. Use mfctl,w to read all six bits. Otherwise 469 * we lose the 6th bit on a save/restore over interrupt. 470 */ 471 mfctl,w %cr11, %r1 472 STREG %r1, PT_SAR (\regs) 473 #else 474 SAVE_CR (%cr11, PT_SAR (\regs)) 475 #endif 476 SAVE_CR (%cr19, PT_IIR (\regs)) 477 478 /* 479 * Code immediately following this macro (in intr_save) relies 480 * on r8 containing ipsw. 481 */ 482 mfctl %cr22, %r8 483 STREG %r8, PT_PSW(\regs) 484 .endm 485 486 .macro rest_specials regs 487 488 REST_SP (%sr0, PT_SR0 (\regs)) 489 REST_SP (%sr1, PT_SR1 (\regs)) 490 REST_SP (%sr2, PT_SR2 (\regs)) 491 REST_SP (%sr3, PT_SR3 (\regs)) 492 REST_SP (%sr4, PT_SR4 (\regs)) 493 REST_SP (%sr5, PT_SR5 (\regs)) 494 REST_SP (%sr6, PT_SR6 (\regs)) 495 REST_SP (%sr7, PT_SR7 (\regs)) 496 497 REST_CR (%cr17, PT_IASQ0(\regs)) 498 REST_CR (%cr17, PT_IASQ1(\regs)) 499 500 REST_CR (%cr18, PT_IAOQ0(\regs)) 501 REST_CR (%cr18, PT_IAOQ1(\regs)) 502 503 REST_CR (%cr11, PT_SAR (\regs)) 504 505 REST_CR (%cr22, PT_PSW (\regs)) 506 .endm 507 508 509 /* First step to create a "relied upon translation" 510 * See PA 2.0 Arch. page F-4 and F-5. 511 * 512 * The ssm was originally necessary due to a "PCxT bug". 513 * But someone decided it needed to be added to the architecture 514 * and this "feature" went into rev3 of PA-RISC 1.1 Arch Manual. 515 * It's been carried forward into PA 2.0 Arch as well. :^( 516 * 517 * "ssm 0,%r0" is a NOP with side effects (prefetch barrier). 518 * rsm/ssm prevents the ifetch unit from speculatively fetching 519 * instructions past this line in the code stream. 520 * PA 2.0 processor will single step all insn in the same QUAD (4 insn). 521 */ 522 .macro pcxt_ssm_bug 523 rsm PSW_SM_I,%r0 524 nop /* 1 */ 525 nop /* 2 */ 526 nop /* 3 */ 527 nop /* 4 */ 528 nop /* 5 */ 529 nop /* 6 */ 530 nop /* 7 */ 531 .endm 532 533 /* Switch to virtual mapping, trashing only %r1 */ 534 .macro virt_map 535 /* pcxt_ssm_bug */ 536 rsm PSW_SM_I, %r0 /* barrier for "Relied upon Translation */ 537 mtsp %r0, %sr4 538 mtsp %r0, %sr5 539 mtsp %r0, %sr6 540 tovirt_r1 %r29 541 load32 KERNEL_PSW, %r1 542 543 rsm PSW_SM_QUIET,%r0 /* second "heavy weight" ctl op */ 544 mtctl %r0, %cr17 /* Clear IIASQ tail */ 545 mtctl %r0, %cr17 /* Clear IIASQ head */ 546 mtctl %r1, %ipsw 547 load32 4f, %r1 548 mtctl %r1, %cr18 /* Set IIAOQ tail */ 549 ldo 4(%r1), %r1 550 mtctl %r1, %cr18 /* Set IIAOQ head */ 551 rfir 552 nop 553 4: 554 .endm 555 556 557 /* 558 * ASM_EXCEPTIONTABLE_ENTRY 559 * 560 * Creates an exception table entry. 561 * Do not convert to a assembler macro. This won't work. 562 */ 563 #define ASM_EXCEPTIONTABLE_ENTRY(fault_addr, except_addr) \ 564 .section __ex_table,"aw" ! \ 565 .word (fault_addr - .), (except_addr - .) ! \ 566 .previous 567 568 569 #endif /* __ASSEMBLY__ */ 570 #endif 571