1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * OpenRISC tlb.c 4 * 5 * Linux architectural port borrowing liberally from similar works of 6 * others. All original copyrights apply as per the original source 7 * declaration. 8 * 9 * Modifications for the OpenRISC architecture: 10 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com> 11 * Copyright (C) 2010-2011 Julius Baxter <julius.baxter@orsoc.se> 12 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> 13 */ 14 15 #include <linux/sched.h> 16 #include <linux/kernel.h> 17 #include <linux/errno.h> 18 #include <linux/string.h> 19 #include <linux/types.h> 20 #include <linux/ptrace.h> 21 #include <linux/mman.h> 22 #include <linux/mm.h> 23 #include <linux/init.h> 24 25 #include <asm/tlbflush.h> 26 #include <asm/mmu_context.h> 27 #include <asm/spr_defs.h> 28 29 #define NO_CONTEXT -1 30 31 #define NUM_DTLB_SETS (1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> \ 32 SPR_DMMUCFGR_NTS_OFF)) 33 #define NUM_ITLB_SETS (1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> \ 34 SPR_IMMUCFGR_NTS_OFF)) 35 #define DTLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_DTLB_SETS-1)) 36 #define ITLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_ITLB_SETS-1)) 37 /* 38 * Invalidate all TLB entries. 39 * 40 * This comes down to setting the 'valid' bit for all xTLBMR registers to 0. 41 * Easiest way to accomplish this is to just zero out the xTLBMR register 42 * completely. 43 * 44 */ 45 46 void local_flush_tlb_all(void) 47 { 48 int i; 49 unsigned long num_tlb_sets; 50 51 /* Determine number of sets for IMMU. */ 52 /* FIXME: Assumption is I & D nsets equal. */ 53 num_tlb_sets = NUM_ITLB_SETS; 54 55 for (i = 0; i < num_tlb_sets; i++) { 56 mtspr_off(SPR_DTLBMR_BASE(0), i, 0); 57 mtspr_off(SPR_ITLBMR_BASE(0), i, 0); 58 } 59 } 60 61 #define have_dtlbeir (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_TEIRI) 62 #define have_itlbeir (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_TEIRI) 63 64 /* 65 * Invalidate a single page. This is what the xTLBEIR register is for. 66 * 67 * There's no point in checking the vma for PAGE_EXEC to determine whether it's 68 * the data or instruction TLB that should be flushed... that would take more 69 * than the few instructions that the following compiles down to! 70 * 71 * The case where we don't have the xTLBEIR register really only works for 72 * MMU's with a single way and is hard-coded that way. 73 */ 74 75 #define flush_dtlb_page_eir(addr) mtspr(SPR_DTLBEIR, addr) 76 #define flush_dtlb_page_no_eir(addr) \ 77 mtspr_off(SPR_DTLBMR_BASE(0), DTLB_OFFSET(addr), 0); 78 79 #define flush_itlb_page_eir(addr) mtspr(SPR_ITLBEIR, addr) 80 #define flush_itlb_page_no_eir(addr) \ 81 mtspr_off(SPR_ITLBMR_BASE(0), ITLB_OFFSET(addr), 0); 82 83 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) 84 { 85 if (have_dtlbeir) 86 flush_dtlb_page_eir(addr); 87 else 88 flush_dtlb_page_no_eir(addr); 89 90 if (have_itlbeir) 91 flush_itlb_page_eir(addr); 92 else 93 flush_itlb_page_no_eir(addr); 94 } 95 96 void local_flush_tlb_range(struct vm_area_struct *vma, 97 unsigned long start, unsigned long end) 98 { 99 int addr; 100 bool dtlbeir; 101 bool itlbeir; 102 103 dtlbeir = have_dtlbeir; 104 itlbeir = have_itlbeir; 105 106 for (addr = start; addr < end; addr += PAGE_SIZE) { 107 if (dtlbeir) 108 flush_dtlb_page_eir(addr); 109 else 110 flush_dtlb_page_no_eir(addr); 111 112 if (itlbeir) 113 flush_itlb_page_eir(addr); 114 else 115 flush_itlb_page_no_eir(addr); 116 } 117 } 118 119 /* 120 * Invalidate the selected mm context only. 121 * 122 * FIXME: Due to some bug here, we're flushing everything for now. 123 * This should be changed to loop over over mm and call flush_tlb_range. 124 */ 125 126 void local_flush_tlb_mm(struct mm_struct *mm) 127 { 128 129 /* Was seeing bugs with the mm struct passed to us. Scrapped most of 130 this function. */ 131 /* Several architectures do this */ 132 local_flush_tlb_all(); 133 } 134 135 /* called in schedule() just before actually doing the switch_to */ 136 137 void switch_mm(struct mm_struct *prev, struct mm_struct *next, 138 struct task_struct *next_tsk) 139 { 140 unsigned int cpu; 141 142 if (unlikely(prev == next)) 143 return; 144 145 cpu = smp_processor_id(); 146 147 cpumask_clear_cpu(cpu, mm_cpumask(prev)); 148 cpumask_set_cpu(cpu, mm_cpumask(next)); 149 150 /* remember the pgd for the fault handlers 151 * this is similar to the pgd register in some other CPU's. 152 * we need our own copy of it because current and active_mm 153 * might be invalid at points where we still need to derefer 154 * the pgd. 155 */ 156 current_pgd[cpu] = next->pgd; 157 158 /* We don't have context support implemented, so flush all 159 * entries belonging to previous map 160 */ 161 local_flush_tlb_mm(prev); 162 } 163 164 /* 165 * Initialize the context related info for a new mm_struct 166 * instance. 167 */ 168 169 int init_new_context(struct task_struct *tsk, struct mm_struct *mm) 170 { 171 mm->context = NO_CONTEXT; 172 return 0; 173 } 174 175 /* called by __exit_mm to destroy the used MMU context if any before 176 * destroying the mm itself. this is only called when the last user of the mm 177 * drops it. 178 */ 179 180 void destroy_context(struct mm_struct *mm) 181 { 182 flush_tlb_mm(mm); 183 184 } 185 186 /* called once during VM initialization, from init.c */ 187 188 void __init tlb_init(void) 189 { 190 /* Do nothing... */ 191 /* invalidate the entire TLB */ 192 /* flush_tlb_all(); */ 193 } 194