1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * OpenRISC idle.c 4 * 5 * Linux architectural port borrowing liberally from similar works of 6 * others. All original copyrights apply as per the original source 7 * declaration. 8 * 9 * Modifications for the OpenRISC architecture: 10 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com> 11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> 12 */ 13 14 #include <linux/signal.h> 15 #include <linux/sched.h> 16 #include <linux/kernel.h> 17 #include <linux/errno.h> 18 #include <linux/string.h> 19 #include <linux/types.h> 20 #include <linux/ptrace.h> 21 #include <linux/mman.h> 22 #include <linux/mm.h> 23 #include <linux/swap.h> 24 #include <linux/smp.h> 25 #include <linux/memblock.h> 26 #include <linux/init.h> 27 #include <linux/delay.h> 28 #include <linux/pagemap.h> 29 30 #include <asm/pgalloc.h> 31 #include <asm/dma.h> 32 #include <asm/io.h> 33 #include <asm/tlb.h> 34 #include <asm/mmu_context.h> 35 #include <asm/fixmap.h> 36 #include <asm/tlbflush.h> 37 #include <asm/sections.h> 38 39 int mem_init_done; 40 41 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); 42 43 static void __init zone_sizes_init(void) 44 { 45 unsigned long max_zone_pfn[MAX_NR_ZONES] = { 0 }; 46 47 /* 48 * We use only ZONE_NORMAL 49 */ 50 max_zone_pfn[ZONE_NORMAL] = max_low_pfn; 51 52 free_area_init(max_zone_pfn); 53 } 54 55 extern const char _s_kernel_ro[], _e_kernel_ro[]; 56 57 /* 58 * Map all physical memory into kernel's address space. 59 * 60 * This is explicitly coded for two-level page tables, so if you need 61 * something else then this needs to change. 62 */ 63 static void __init map_ram(void) 64 { 65 phys_addr_t start, end; 66 unsigned long v, p, e; 67 pgprot_t prot; 68 pgd_t *pge; 69 p4d_t *p4e; 70 pud_t *pue; 71 pmd_t *pme; 72 pte_t *pte; 73 u64 i; 74 /* These mark extents of read-only kernel pages... 75 * ...from vmlinux.lds.S 76 */ 77 78 v = PAGE_OFFSET; 79 80 for_each_mem_range(i, &start, &end) { 81 p = (u32) start & PAGE_MASK; 82 e = (u32) end; 83 84 v = (u32) __va(p); 85 pge = pgd_offset_k(v); 86 87 while (p < e) { 88 int j; 89 p4e = p4d_offset(pge, v); 90 pue = pud_offset(p4e, v); 91 pme = pmd_offset(pue, v); 92 93 if ((u32) pue != (u32) pge || (u32) pme != (u32) pge) { 94 panic("%s: OR1K kernel hardcoded for " 95 "two-level page tables", 96 __func__); 97 } 98 99 /* Alloc one page for holding PTE's... */ 100 pte = memblock_alloc_raw(PAGE_SIZE, PAGE_SIZE); 101 if (!pte) 102 panic("%s: Failed to allocate page for PTEs\n", 103 __func__); 104 set_pmd(pme, __pmd(_KERNPG_TABLE + __pa(pte))); 105 106 /* Fill the newly allocated page with PTE'S */ 107 for (j = 0; p < e && j < PTRS_PER_PTE; 108 v += PAGE_SIZE, p += PAGE_SIZE, j++, pte++) { 109 if (v >= (u32) _e_kernel_ro || 110 v < (u32) _s_kernel_ro) 111 prot = PAGE_KERNEL; 112 else 113 prot = PAGE_KERNEL_RO; 114 115 set_pte(pte, mk_pte_phys(p, prot)); 116 } 117 118 pge++; 119 } 120 121 printk(KERN_INFO "%s: Memory: 0x%x-0x%x\n", __func__, 122 start, end); 123 } 124 } 125 126 void __init paging_init(void) 127 { 128 extern void tlb_init(void); 129 130 int i; 131 132 printk(KERN_INFO "Setting up paging and PTEs.\n"); 133 134 /* clear out the init_mm.pgd that will contain the kernel's mappings */ 135 136 for (i = 0; i < PTRS_PER_PGD; i++) 137 swapper_pg_dir[i] = __pgd(0); 138 139 /* make sure the current pgd table points to something sane 140 * (even if it is most probably not used until the next 141 * switch_mm) 142 */ 143 current_pgd[smp_processor_id()] = init_mm.pgd; 144 145 map_ram(); 146 147 zone_sizes_init(); 148 149 /* self modifying code ;) */ 150 /* Since the old TLB miss handler has been running up until now, 151 * the kernel pages are still all RW, so we can still modify the 152 * text directly... after this change and a TLB flush, the kernel 153 * pages will become RO. 154 */ 155 { 156 extern unsigned long dtlb_miss_handler; 157 extern unsigned long itlb_miss_handler; 158 159 unsigned long *dtlb_vector = __va(0x900); 160 unsigned long *itlb_vector = __va(0xa00); 161 162 printk(KERN_INFO "itlb_miss_handler %p\n", &itlb_miss_handler); 163 *itlb_vector = ((unsigned long)&itlb_miss_handler - 164 (unsigned long)itlb_vector) >> 2; 165 166 /* Soft ordering constraint to ensure that dtlb_vector is 167 * the last thing updated 168 */ 169 barrier(); 170 171 printk(KERN_INFO "dtlb_miss_handler %p\n", &dtlb_miss_handler); 172 *dtlb_vector = ((unsigned long)&dtlb_miss_handler - 173 (unsigned long)dtlb_vector) >> 2; 174 175 } 176 177 /* Soft ordering constraint to ensure that cache invalidation and 178 * TLB flush really happen _after_ code has been modified. 179 */ 180 barrier(); 181 182 /* Invalidate instruction caches after code modification */ 183 mtspr(SPR_ICBIR, 0x900); 184 mtspr(SPR_ICBIR, 0xa00); 185 186 /* New TLB miss handlers and kernel page tables are in now place. 187 * Make sure that page flags get updated for all pages in TLB by 188 * flushing the TLB and forcing all TLB entries to be recreated 189 * from their page table flags. 190 */ 191 flush_tlb_all(); 192 } 193 194 /* References to section boundaries */ 195 196 void __init mem_init(void) 197 { 198 BUG_ON(!mem_map); 199 200 max_mapnr = max_low_pfn; 201 high_memory = (void *)__va(max_low_pfn * PAGE_SIZE); 202 203 /* clear the zero-page */ 204 memset((void *)empty_zero_page, 0, PAGE_SIZE); 205 206 /* this will put all low memory onto the freelists */ 207 memblock_free_all(); 208 209 printk("mem_init_done ...........................................\n"); 210 mem_init_done = 1; 211 return; 212 } 213