1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * OpenRISC time.c 4 * 5 * Linux architectural port borrowing liberally from similar works of 6 * others. All original copyrights apply as per the original source 7 * declaration. 8 * 9 * Modifications for the OpenRISC architecture: 10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/time.h> 15 #include <linux/timex.h> 16 #include <linux/interrupt.h> 17 #include <linux/ftrace.h> 18 19 #include <linux/clocksource.h> 20 #include <linux/clockchips.h> 21 #include <linux/irq.h> 22 #include <linux/io.h> 23 #include <linux/of_clk.h> 24 25 #include <asm/cpuinfo.h> 26 27 /* Test the timer ticks to count, used in sync routine */ 28 inline void openrisc_timer_set(unsigned long count) 29 { 30 mtspr(SPR_TTCR, count); 31 } 32 33 /* Set the timer to trigger in delta cycles */ 34 inline void openrisc_timer_set_next(unsigned long delta) 35 { 36 u32 c; 37 38 /* Read 32-bit counter value, add delta, mask off the low 28 bits. 39 * We're guaranteed delta won't be bigger than 28 bits because the 40 * generic timekeeping code ensures that for us. 41 */ 42 c = mfspr(SPR_TTCR); 43 c += delta; 44 c &= SPR_TTMR_TP; 45 46 /* Set counter and enable interrupt. 47 * Keep timer in continuous mode always. 48 */ 49 mtspr(SPR_TTMR, SPR_TTMR_CR | SPR_TTMR_IE | c); 50 } 51 52 static int openrisc_timer_set_next_event(unsigned long delta, 53 struct clock_event_device *dev) 54 { 55 openrisc_timer_set_next(delta); 56 return 0; 57 } 58 59 /* This is the clock event device based on the OR1K tick timer. 60 * As the timer is being used as a continuous clock-source (required for HR 61 * timers) we cannot enable the PERIODIC feature. The tick timer can run using 62 * one-shot events, so no problem. 63 */ 64 DEFINE_PER_CPU(struct clock_event_device, clockevent_openrisc_timer); 65 66 void openrisc_clockevent_init(void) 67 { 68 unsigned int cpu = smp_processor_id(); 69 struct clock_event_device *evt = 70 &per_cpu(clockevent_openrisc_timer, cpu); 71 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu]; 72 73 mtspr(SPR_TTMR, SPR_TTMR_CR); 74 75 #ifdef CONFIG_SMP 76 evt->broadcast = tick_broadcast; 77 #endif 78 evt->name = "openrisc_timer_clockevent", 79 evt->features = CLOCK_EVT_FEAT_ONESHOT, 80 evt->rating = 300, 81 evt->set_next_event = openrisc_timer_set_next_event, 82 83 evt->cpumask = cpumask_of(cpu); 84 85 /* We only have 28 bits */ 86 clockevents_config_and_register(evt, cpuinfo->clock_frequency, 87 100, 0x0fffffff); 88 89 } 90 91 static inline void timer_ack(void) 92 { 93 /* Clear the IP bit and disable further interrupts */ 94 /* This can be done very simply... we just need to keep the timer 95 running, so just maintain the CR bits while clearing the rest 96 of the register 97 */ 98 mtspr(SPR_TTMR, SPR_TTMR_CR); 99 } 100 101 /* 102 * The timer interrupt is mostly handled in generic code nowadays... this 103 * function just acknowledges the interrupt and fires the event handler that 104 * has been set on the clockevent device by the generic time management code. 105 * 106 * This function needs to be called by the timer exception handler and that's 107 * all the exception handler needs to do. 108 */ 109 110 irqreturn_t __irq_entry timer_interrupt(struct pt_regs *regs) 111 { 112 struct pt_regs *old_regs = set_irq_regs(regs); 113 unsigned int cpu = smp_processor_id(); 114 struct clock_event_device *evt = 115 &per_cpu(clockevent_openrisc_timer, cpu); 116 117 timer_ack(); 118 119 /* 120 * update_process_times() expects us to have called irq_enter(). 121 */ 122 irq_enter(); 123 evt->event_handler(evt); 124 irq_exit(); 125 126 set_irq_regs(old_regs); 127 128 return IRQ_HANDLED; 129 } 130 131 /* 132 * Clocksource: Based on OpenRISC timer/counter 133 * 134 * This sets up the OpenRISC Tick Timer as a clock source. The tick timer 135 * is 32 bits wide and runs at the CPU clock frequency. 136 */ 137 static u64 openrisc_timer_read(struct clocksource *cs) 138 { 139 return (u64) mfspr(SPR_TTCR); 140 } 141 142 static struct clocksource openrisc_timer = { 143 .name = "openrisc_timer", 144 .rating = 200, 145 .read = openrisc_timer_read, 146 .mask = CLOCKSOURCE_MASK(32), 147 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 148 }; 149 150 static int __init openrisc_timer_init(void) 151 { 152 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()]; 153 154 if (clocksource_register_hz(&openrisc_timer, cpuinfo->clock_frequency)) 155 panic("failed to register clocksource"); 156 157 /* Enable the incrementer: 'continuous' mode with interrupt disabled */ 158 mtspr(SPR_TTMR, SPR_TTMR_CR); 159 160 return 0; 161 } 162 163 void __init time_init(void) 164 { 165 u32 upr; 166 167 upr = mfspr(SPR_UPR); 168 if (!(upr & SPR_UPR_TTP)) 169 panic("Linux not supported on devices without tick timer"); 170 171 openrisc_timer_init(); 172 openrisc_clockevent_init(); 173 174 of_clk_init(NULL); 175 timer_probe(); 176 } 177