1 /* 2 * OpenRISC setup.c 3 * 4 * Linux architectural port borrowing liberally from similar works of 5 * others. All original copyrights apply as per the original source 6 * declaration. 7 * 8 * Modifications for the OpenRISC architecture: 9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com> 10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License 14 * as published by the Free Software Foundation; either version 15 * 2 of the License, or (at your option) any later version. 16 * 17 * This file handles the architecture-dependent parts of initialization 18 */ 19 20 #include <linux/errno.h> 21 #include <linux/sched.h> 22 #include <linux/kernel.h> 23 #include <linux/mm.h> 24 #include <linux/stddef.h> 25 #include <linux/unistd.h> 26 #include <linux/ptrace.h> 27 #include <linux/slab.h> 28 #include <linux/tty.h> 29 #include <linux/ioport.h> 30 #include <linux/delay.h> 31 #include <linux/console.h> 32 #include <linux/init.h> 33 #include <linux/bootmem.h> 34 #include <linux/seq_file.h> 35 #include <linux/serial.h> 36 #include <linux/initrd.h> 37 #include <linux/of_fdt.h> 38 #include <linux/of.h> 39 #include <linux/memblock.h> 40 #include <linux/device.h> 41 #include <linux/of_platform.h> 42 43 #include <asm/segment.h> 44 #include <asm/pgtable.h> 45 #include <asm/types.h> 46 #include <asm/setup.h> 47 #include <asm/io.h> 48 #include <asm/cpuinfo.h> 49 #include <asm/delay.h> 50 51 #include "vmlinux.h" 52 53 char __initdata cmd_line[COMMAND_LINE_SIZE] = CONFIG_CMDLINE; 54 55 static unsigned long __init setup_memory(void) 56 { 57 unsigned long bootmap_size; 58 unsigned long ram_start_pfn; 59 unsigned long free_ram_start_pfn; 60 unsigned long ram_end_pfn; 61 phys_addr_t memory_start, memory_end; 62 struct memblock_region *region; 63 64 memory_end = memory_start = 0; 65 66 /* Find main memory where is the kernel */ 67 for_each_memblock(memory, region) { 68 memory_start = region->base; 69 memory_end = region->base + region->size; 70 printk(KERN_INFO "%s: Memory: 0x%x-0x%x\n", __func__, 71 memory_start, memory_end); 72 } 73 74 if (!memory_end) { 75 panic("No memory!"); 76 } 77 78 ram_start_pfn = PFN_UP(memory_start); 79 /* free_ram_start_pfn is first page after kernel */ 80 free_ram_start_pfn = PFN_UP(__pa(&_end)); 81 ram_end_pfn = PFN_DOWN(memblock_end_of_DRAM()); 82 83 max_pfn = ram_end_pfn; 84 85 /* 86 * initialize the boot-time allocator (with low memory only). 87 * 88 * This makes the memory from the end of the kernel to the end of 89 * RAM usable. 90 * init_bootmem sets the global values min_low_pfn, max_low_pfn. 91 */ 92 bootmap_size = init_bootmem(free_ram_start_pfn, 93 ram_end_pfn - ram_start_pfn); 94 free_bootmem(PFN_PHYS(free_ram_start_pfn), 95 (ram_end_pfn - free_ram_start_pfn) << PAGE_SHIFT); 96 reserve_bootmem(PFN_PHYS(free_ram_start_pfn), bootmap_size, 97 BOOTMEM_DEFAULT); 98 99 for_each_memblock(reserved, region) { 100 printk(KERN_INFO "Reserved - 0x%08x-0x%08x\n", 101 (u32) region->base, (u32) region->size); 102 reserve_bootmem(region->base, region->size, BOOTMEM_DEFAULT); 103 } 104 105 return ram_end_pfn; 106 } 107 108 struct cpuinfo cpuinfo; 109 110 static void print_cpuinfo(void) 111 { 112 unsigned long upr = mfspr(SPR_UPR); 113 unsigned long vr = mfspr(SPR_VR); 114 unsigned int version; 115 unsigned int revision; 116 117 version = (vr & SPR_VR_VER) >> 24; 118 revision = (vr & SPR_VR_REV); 119 120 printk(KERN_INFO "CPU: OpenRISC-%x (revision %d) @%d MHz\n", 121 version, revision, cpuinfo.clock_frequency / 1000000); 122 123 if (!(upr & SPR_UPR_UP)) { 124 printk(KERN_INFO 125 "-- no UPR register... unable to detect configuration\n"); 126 return; 127 } 128 129 if (upr & SPR_UPR_DCP) 130 printk(KERN_INFO 131 "-- dcache: %4d bytes total, %2d bytes/line, %d way(s)\n", 132 cpuinfo.dcache_size, cpuinfo.dcache_block_size, 1); 133 else 134 printk(KERN_INFO "-- dcache disabled\n"); 135 if (upr & SPR_UPR_ICP) 136 printk(KERN_INFO 137 "-- icache: %4d bytes total, %2d bytes/line, %d way(s)\n", 138 cpuinfo.icache_size, cpuinfo.icache_block_size, 1); 139 else 140 printk(KERN_INFO "-- icache disabled\n"); 141 142 if (upr & SPR_UPR_DMP) 143 printk(KERN_INFO "-- dmmu: %4d entries, %lu way(s)\n", 144 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2), 145 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW)); 146 if (upr & SPR_UPR_IMP) 147 printk(KERN_INFO "-- immu: %4d entries, %lu way(s)\n", 148 1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2), 149 1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW)); 150 151 printk(KERN_INFO "-- additional features:\n"); 152 if (upr & SPR_UPR_DUP) 153 printk(KERN_INFO "-- debug unit\n"); 154 if (upr & SPR_UPR_PCUP) 155 printk(KERN_INFO "-- performance counters\n"); 156 if (upr & SPR_UPR_PMP) 157 printk(KERN_INFO "-- power management\n"); 158 if (upr & SPR_UPR_PICP) 159 printk(KERN_INFO "-- PIC\n"); 160 if (upr & SPR_UPR_TTP) 161 printk(KERN_INFO "-- timer\n"); 162 if (upr & SPR_UPR_CUP) 163 printk(KERN_INFO "-- custom unit(s)\n"); 164 } 165 166 void __init setup_cpuinfo(void) 167 { 168 struct device_node *cpu; 169 unsigned long iccfgr, dccfgr; 170 unsigned long cache_set_size, cache_ways; 171 172 cpu = of_find_compatible_node(NULL, NULL, "opencores,or1200-rtlsvn481"); 173 if (!cpu) 174 panic("No compatible CPU found in device tree...\n"); 175 176 iccfgr = mfspr(SPR_ICCFGR); 177 cache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW); 178 cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3); 179 cpuinfo.icache_block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7); 180 cpuinfo.icache_size = 181 cache_set_size * cache_ways * cpuinfo.icache_block_size; 182 183 dccfgr = mfspr(SPR_DCCFGR); 184 cache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW); 185 cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3); 186 cpuinfo.dcache_block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7); 187 cpuinfo.dcache_size = 188 cache_set_size * cache_ways * cpuinfo.dcache_block_size; 189 190 if (of_property_read_u32(cpu, "clock-frequency", 191 &cpuinfo.clock_frequency)) { 192 printk(KERN_WARNING 193 "Device tree missing CPU 'clock-frequency' parameter." 194 "Assuming frequency 25MHZ" 195 "This is probably not what you want."); 196 } 197 198 of_node_put(cpu); 199 200 print_cpuinfo(); 201 } 202 203 /** 204 * or32_early_setup 205 * 206 * Handles the pointer to the device tree that this kernel is to use 207 * for establishing the available platform devices. 208 * 209 * Falls back on built-in device tree in case null pointer is passed. 210 */ 211 212 void __init or32_early_setup(unsigned int fdt) 213 { 214 if (fdt) { 215 early_init_devtree((void*) fdt); 216 printk(KERN_INFO "FDT at 0x%08x\n", fdt); 217 } else { 218 early_init_devtree(__dtb_start); 219 printk(KERN_INFO "Compiled-in FDT at %p\n", __dtb_start); 220 } 221 } 222 223 static int __init openrisc_device_probe(void) 224 { 225 of_platform_populate(NULL, NULL, NULL, NULL); 226 227 return 0; 228 } 229 230 device_initcall(openrisc_device_probe); 231 232 static inline unsigned long extract_value_bits(unsigned long reg, 233 short bit_nr, short width) 234 { 235 return (reg >> bit_nr) & (0 << width); 236 } 237 238 static inline unsigned long extract_value(unsigned long reg, unsigned long mask) 239 { 240 while (!(mask & 0x1)) { 241 reg = reg >> 1; 242 mask = mask >> 1; 243 } 244 return mask & reg; 245 } 246 247 void __init detect_unit_config(unsigned long upr, unsigned long mask, 248 char *text, void (*func) (void)) 249 { 250 if (text != NULL) 251 printk("%s", text); 252 253 if (upr & mask) { 254 if (func != NULL) 255 func(); 256 else 257 printk("present\n"); 258 } else 259 printk("not present\n"); 260 } 261 262 /* 263 * calibrate_delay 264 * 265 * Lightweight calibrate_delay implementation that calculates loops_per_jiffy 266 * from the clock frequency passed in via the device tree 267 * 268 */ 269 270 void calibrate_delay(void) 271 { 272 const int *val; 273 struct device_node *cpu = NULL; 274 cpu = of_find_compatible_node(NULL, NULL, "opencores,or1200-rtlsvn481"); 275 val = of_get_property(cpu, "clock-frequency", NULL); 276 if (!val) 277 panic("no cpu 'clock-frequency' parameter in device tree"); 278 loops_per_jiffy = *val / HZ; 279 pr_cont("%lu.%02lu BogoMIPS (lpj=%lu)\n", 280 loops_per_jiffy / (500000 / HZ), 281 (loops_per_jiffy / (5000 / HZ)) % 100, loops_per_jiffy); 282 } 283 284 void __init setup_arch(char **cmdline_p) 285 { 286 unsigned long max_low_pfn; 287 288 unflatten_device_tree(); 289 290 setup_cpuinfo(); 291 292 /* process 1's initial memory region is the kernel code/data */ 293 init_mm.start_code = (unsigned long)&_stext; 294 init_mm.end_code = (unsigned long)&_etext; 295 init_mm.end_data = (unsigned long)&_edata; 296 init_mm.brk = (unsigned long)&_end; 297 298 #ifdef CONFIG_BLK_DEV_INITRD 299 initrd_start = (unsigned long)&__initrd_start; 300 initrd_end = (unsigned long)&__initrd_end; 301 if (initrd_start == initrd_end) { 302 initrd_start = 0; 303 initrd_end = 0; 304 } 305 initrd_below_start_ok = 1; 306 #endif 307 308 /* setup bootmem allocator */ 309 max_low_pfn = setup_memory(); 310 311 /* paging_init() sets up the MMU and marks all pages as reserved */ 312 paging_init(); 313 314 #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE) 315 if (!conswitchp) 316 conswitchp = &dummy_con; 317 #endif 318 319 *cmdline_p = cmd_line; 320 321 printk(KERN_INFO "OpenRISC Linux -- http://openrisc.net\n"); 322 } 323 324 static int show_cpuinfo(struct seq_file *m, void *v) 325 { 326 unsigned long vr; 327 int version, revision; 328 329 vr = mfspr(SPR_VR); 330 version = (vr & SPR_VR_VER) >> 24; 331 revision = vr & SPR_VR_REV; 332 333 return seq_printf(m, 334 "cpu\t\t: OpenRISC-%x\n" 335 "revision\t: %d\n" 336 "frequency\t: %ld\n" 337 "dcache size\t: %d bytes\n" 338 "dcache block size\t: %d bytes\n" 339 "icache size\t: %d bytes\n" 340 "icache block size\t: %d bytes\n" 341 "immu\t\t: %d entries, %lu ways\n" 342 "dmmu\t\t: %d entries, %lu ways\n" 343 "bogomips\t: %lu.%02lu\n", 344 version, 345 revision, 346 loops_per_jiffy * HZ, 347 cpuinfo.dcache_size, 348 cpuinfo.dcache_block_size, 349 cpuinfo.icache_size, 350 cpuinfo.icache_block_size, 351 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2), 352 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW), 353 1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2), 354 1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW), 355 (loops_per_jiffy * HZ) / 500000, 356 ((loops_per_jiffy * HZ) / 5000) % 100); 357 } 358 359 static void *c_start(struct seq_file *m, loff_t * pos) 360 { 361 /* We only have one CPU... */ 362 return *pos < 1 ? (void *)1 : NULL; 363 } 364 365 static void *c_next(struct seq_file *m, void *v, loff_t * pos) 366 { 367 ++*pos; 368 return NULL; 369 } 370 371 static void c_stop(struct seq_file *m, void *v) 372 { 373 } 374 375 const struct seq_operations cpuinfo_op = { 376 .start = c_start, 377 .next = c_next, 378 .stop = c_stop, 379 .show = show_cpuinfo, 380 }; 381