1 /* 2 * OpenRISC setup.c 3 * 4 * Linux architectural port borrowing liberally from similar works of 5 * others. All original copyrights apply as per the original source 6 * declaration. 7 * 8 * Modifications for the OpenRISC architecture: 9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com> 10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License 14 * as published by the Free Software Foundation; either version 15 * 2 of the License, or (at your option) any later version. 16 * 17 * This file handles the architecture-dependent parts of initialization 18 */ 19 20 #include <linux/errno.h> 21 #include <linux/sched.h> 22 #include <linux/kernel.h> 23 #include <linux/mm.h> 24 #include <linux/stddef.h> 25 #include <linux/unistd.h> 26 #include <linux/ptrace.h> 27 #include <linux/slab.h> 28 #include <linux/tty.h> 29 #include <linux/ioport.h> 30 #include <linux/delay.h> 31 #include <linux/console.h> 32 #include <linux/init.h> 33 #include <linux/bootmem.h> 34 #include <linux/seq_file.h> 35 #include <linux/serial.h> 36 #include <linux/initrd.h> 37 #include <linux/of_fdt.h> 38 #include <linux/of.h> 39 #include <linux/memblock.h> 40 #include <linux/device.h> 41 42 #include <asm/sections.h> 43 #include <asm/segment.h> 44 #include <asm/pgtable.h> 45 #include <asm/types.h> 46 #include <asm/setup.h> 47 #include <asm/io.h> 48 #include <asm/cpuinfo.h> 49 #include <asm/delay.h> 50 51 #include "vmlinux.h" 52 53 static void __init setup_memory(void) 54 { 55 unsigned long ram_start_pfn; 56 unsigned long ram_end_pfn; 57 phys_addr_t memory_start, memory_end; 58 struct memblock_region *region; 59 60 memory_end = memory_start = 0; 61 62 /* Find main memory where is the kernel, we assume its the only one */ 63 for_each_memblock(memory, region) { 64 memory_start = region->base; 65 memory_end = region->base + region->size; 66 printk(KERN_INFO "%s: Memory: 0x%x-0x%x\n", __func__, 67 memory_start, memory_end); 68 } 69 70 if (!memory_end) { 71 panic("No memory!"); 72 } 73 74 ram_start_pfn = PFN_UP(memory_start); 75 ram_end_pfn = PFN_DOWN(memblock_end_of_DRAM()); 76 77 /* setup bootmem globals (we use no_bootmem, but mm still depends on this) */ 78 min_low_pfn = ram_start_pfn; 79 max_low_pfn = ram_end_pfn; 80 max_pfn = ram_end_pfn; 81 82 /* 83 * initialize the boot-time allocator (with low memory only). 84 * 85 * This makes the memory from the end of the kernel to the end of 86 * RAM usable. 87 */ 88 memblock_reserve(__pa(_stext), _end - _stext); 89 90 early_init_fdt_reserve_self(); 91 early_init_fdt_scan_reserved_mem(); 92 93 memblock_dump_all(); 94 } 95 96 struct cpuinfo_or1k cpuinfo_or1k[NR_CPUS]; 97 98 static void print_cpuinfo(void) 99 { 100 unsigned long upr = mfspr(SPR_UPR); 101 unsigned long vr = mfspr(SPR_VR); 102 unsigned int version; 103 unsigned int revision; 104 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()]; 105 106 version = (vr & SPR_VR_VER) >> 24; 107 revision = (vr & SPR_VR_REV); 108 109 printk(KERN_INFO "CPU: OpenRISC-%x (revision %d) @%d MHz\n", 110 version, revision, cpuinfo->clock_frequency / 1000000); 111 112 if (!(upr & SPR_UPR_UP)) { 113 printk(KERN_INFO 114 "-- no UPR register... unable to detect configuration\n"); 115 return; 116 } 117 118 if (upr & SPR_UPR_DCP) 119 printk(KERN_INFO 120 "-- dcache: %4d bytes total, %2d bytes/line, %d way(s)\n", 121 cpuinfo->dcache_size, cpuinfo->dcache_block_size, 122 cpuinfo->dcache_ways); 123 else 124 printk(KERN_INFO "-- dcache disabled\n"); 125 if (upr & SPR_UPR_ICP) 126 printk(KERN_INFO 127 "-- icache: %4d bytes total, %2d bytes/line, %d way(s)\n", 128 cpuinfo->icache_size, cpuinfo->icache_block_size, 129 cpuinfo->icache_ways); 130 else 131 printk(KERN_INFO "-- icache disabled\n"); 132 133 if (upr & SPR_UPR_DMP) 134 printk(KERN_INFO "-- dmmu: %4d entries, %lu way(s)\n", 135 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2), 136 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW)); 137 if (upr & SPR_UPR_IMP) 138 printk(KERN_INFO "-- immu: %4d entries, %lu way(s)\n", 139 1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2), 140 1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW)); 141 142 printk(KERN_INFO "-- additional features:\n"); 143 if (upr & SPR_UPR_DUP) 144 printk(KERN_INFO "-- debug unit\n"); 145 if (upr & SPR_UPR_PCUP) 146 printk(KERN_INFO "-- performance counters\n"); 147 if (upr & SPR_UPR_PMP) 148 printk(KERN_INFO "-- power management\n"); 149 if (upr & SPR_UPR_PICP) 150 printk(KERN_INFO "-- PIC\n"); 151 if (upr & SPR_UPR_TTP) 152 printk(KERN_INFO "-- timer\n"); 153 if (upr & SPR_UPR_CUP) 154 printk(KERN_INFO "-- custom unit(s)\n"); 155 } 156 157 static struct device_node *setup_find_cpu_node(int cpu) 158 { 159 u32 hwid; 160 struct device_node *cpun; 161 162 for_each_of_cpu_node(cpun) { 163 if (of_property_read_u32(cpun, "reg", &hwid)) 164 continue; 165 if (hwid == cpu) 166 return cpun; 167 } 168 169 return NULL; 170 } 171 172 void __init setup_cpuinfo(void) 173 { 174 struct device_node *cpu; 175 unsigned long iccfgr, dccfgr; 176 unsigned long cache_set_size; 177 int cpu_id = smp_processor_id(); 178 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu_id]; 179 180 cpu = setup_find_cpu_node(cpu_id); 181 if (!cpu) 182 panic("Couldn't find CPU%d in device tree...\n", cpu_id); 183 184 iccfgr = mfspr(SPR_ICCFGR); 185 cpuinfo->icache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW); 186 cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3); 187 cpuinfo->icache_block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7); 188 cpuinfo->icache_size = 189 cache_set_size * cpuinfo->icache_ways * cpuinfo->icache_block_size; 190 191 dccfgr = mfspr(SPR_DCCFGR); 192 cpuinfo->dcache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW); 193 cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3); 194 cpuinfo->dcache_block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7); 195 cpuinfo->dcache_size = 196 cache_set_size * cpuinfo->dcache_ways * cpuinfo->dcache_block_size; 197 198 if (of_property_read_u32(cpu, "clock-frequency", 199 &cpuinfo->clock_frequency)) { 200 printk(KERN_WARNING 201 "Device tree missing CPU 'clock-frequency' parameter." 202 "Assuming frequency 25MHZ" 203 "This is probably not what you want."); 204 } 205 206 cpuinfo->coreid = mfspr(SPR_COREID); 207 208 of_node_put(cpu); 209 210 print_cpuinfo(); 211 } 212 213 /** 214 * or32_early_setup 215 * 216 * Handles the pointer to the device tree that this kernel is to use 217 * for establishing the available platform devices. 218 * 219 * Falls back on built-in device tree in case null pointer is passed. 220 */ 221 222 void __init or32_early_setup(void *fdt) 223 { 224 if (fdt) 225 pr_info("FDT at %p\n", fdt); 226 else { 227 fdt = __dtb_start; 228 pr_info("Compiled-in FDT at %p\n", fdt); 229 } 230 early_init_devtree(fdt); 231 } 232 233 static inline unsigned long extract_value_bits(unsigned long reg, 234 short bit_nr, short width) 235 { 236 return (reg >> bit_nr) & (0 << width); 237 } 238 239 static inline unsigned long extract_value(unsigned long reg, unsigned long mask) 240 { 241 while (!(mask & 0x1)) { 242 reg = reg >> 1; 243 mask = mask >> 1; 244 } 245 return mask & reg; 246 } 247 248 void __init detect_unit_config(unsigned long upr, unsigned long mask, 249 char *text, void (*func) (void)) 250 { 251 if (text != NULL) 252 printk("%s", text); 253 254 if (upr & mask) { 255 if (func != NULL) 256 func(); 257 else 258 printk("present\n"); 259 } else 260 printk("not present\n"); 261 } 262 263 /* 264 * calibrate_delay 265 * 266 * Lightweight calibrate_delay implementation that calculates loops_per_jiffy 267 * from the clock frequency passed in via the device tree 268 * 269 */ 270 271 void calibrate_delay(void) 272 { 273 const int *val; 274 struct device_node *cpu = setup_find_cpu_node(smp_processor_id()); 275 276 val = of_get_property(cpu, "clock-frequency", NULL); 277 if (!val) 278 panic("no cpu 'clock-frequency' parameter in device tree"); 279 loops_per_jiffy = *val / HZ; 280 pr_cont("%lu.%02lu BogoMIPS (lpj=%lu)\n", 281 loops_per_jiffy / (500000 / HZ), 282 (loops_per_jiffy / (5000 / HZ)) % 100, loops_per_jiffy); 283 } 284 285 void __init setup_arch(char **cmdline_p) 286 { 287 unflatten_and_copy_device_tree(); 288 289 setup_cpuinfo(); 290 291 #ifdef CONFIG_SMP 292 smp_init_cpus(); 293 #endif 294 295 /* process 1's initial memory region is the kernel code/data */ 296 init_mm.start_code = (unsigned long)_stext; 297 init_mm.end_code = (unsigned long)_etext; 298 init_mm.end_data = (unsigned long)_edata; 299 init_mm.brk = (unsigned long)_end; 300 301 #ifdef CONFIG_BLK_DEV_INITRD 302 initrd_start = (unsigned long)&__initrd_start; 303 initrd_end = (unsigned long)&__initrd_end; 304 if (initrd_start == initrd_end) { 305 initrd_start = 0; 306 initrd_end = 0; 307 } 308 initrd_below_start_ok = 1; 309 #endif 310 311 /* setup memblock allocator */ 312 setup_memory(); 313 314 /* paging_init() sets up the MMU and marks all pages as reserved */ 315 paging_init(); 316 317 #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE) 318 if (!conswitchp) 319 conswitchp = &dummy_con; 320 #endif 321 322 *cmdline_p = boot_command_line; 323 324 printk(KERN_INFO "OpenRISC Linux -- http://openrisc.io\n"); 325 } 326 327 static int show_cpuinfo(struct seq_file *m, void *v) 328 { 329 unsigned int vr, cpucfgr; 330 unsigned int avr; 331 unsigned int version; 332 struct cpuinfo_or1k *cpuinfo = v; 333 334 vr = mfspr(SPR_VR); 335 cpucfgr = mfspr(SPR_CPUCFGR); 336 337 #ifdef CONFIG_SMP 338 seq_printf(m, "processor\t\t: %d\n", cpuinfo->coreid); 339 #endif 340 if (vr & SPR_VR_UVRP) { 341 vr = mfspr(SPR_VR2); 342 version = vr & SPR_VR2_VER; 343 avr = mfspr(SPR_AVR); 344 seq_printf(m, "cpu architecture\t: " 345 "OpenRISC 1000 (%d.%d-rev%d)\n", 346 (avr >> 24) & 0xff, 347 (avr >> 16) & 0xff, 348 (avr >> 8) & 0xff); 349 seq_printf(m, "cpu implementation id\t: 0x%x\n", 350 (vr & SPR_VR2_CPUID) >> 24); 351 seq_printf(m, "cpu version\t\t: 0x%x\n", version); 352 } else { 353 version = (vr & SPR_VR_VER) >> 24; 354 seq_printf(m, "cpu\t\t\t: OpenRISC-%x\n", version); 355 seq_printf(m, "revision\t\t: %d\n", vr & SPR_VR_REV); 356 } 357 seq_printf(m, "frequency\t\t: %ld\n", loops_per_jiffy * HZ); 358 seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache_size); 359 seq_printf(m, "dcache block size\t: %d bytes\n", 360 cpuinfo->dcache_block_size); 361 seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache_ways); 362 seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache_size); 363 seq_printf(m, "icache block size\t: %d bytes\n", 364 cpuinfo->icache_block_size); 365 seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache_ways); 366 seq_printf(m, "immu\t\t\t: %d entries, %lu ways\n", 367 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2), 368 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW)); 369 seq_printf(m, "dmmu\t\t\t: %d entries, %lu ways\n", 370 1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2), 371 1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW)); 372 seq_printf(m, "bogomips\t\t: %lu.%02lu\n", 373 (loops_per_jiffy * HZ) / 500000, 374 ((loops_per_jiffy * HZ) / 5000) % 100); 375 376 seq_puts(m, "features\t\t: "); 377 seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OB32S ? "orbis32" : ""); 378 seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OB64S ? "orbis64" : ""); 379 seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OF32S ? "orfpx32" : ""); 380 seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OF64S ? "orfpx64" : ""); 381 seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OV64S ? "orvdx64" : ""); 382 seq_puts(m, "\n"); 383 384 seq_puts(m, "\n"); 385 386 return 0; 387 } 388 389 static void *c_start(struct seq_file *m, loff_t *pos) 390 { 391 *pos = cpumask_next(*pos - 1, cpu_online_mask); 392 if ((*pos) < nr_cpu_ids) 393 return &cpuinfo_or1k[*pos]; 394 return NULL; 395 } 396 397 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 398 { 399 (*pos)++; 400 return c_start(m, pos); 401 } 402 403 static void c_stop(struct seq_file *m, void *v) 404 { 405 } 406 407 const struct seq_operations cpuinfo_op = { 408 .start = c_start, 409 .next = c_next, 410 .stop = c_stop, 411 .show = show_cpuinfo, 412 }; 413