1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * OpenRISC setup.c 4 * 5 * Linux architectural port borrowing liberally from similar works of 6 * others. All original copyrights apply as per the original source 7 * declaration. 8 * 9 * Modifications for the OpenRISC architecture: 10 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com> 11 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> 12 * 13 * This file handles the architecture-dependent parts of initialization 14 */ 15 16 #include <linux/errno.h> 17 #include <linux/sched.h> 18 #include <linux/kernel.h> 19 #include <linux/mm.h> 20 #include <linux/stddef.h> 21 #include <linux/unistd.h> 22 #include <linux/ptrace.h> 23 #include <linux/slab.h> 24 #include <linux/tty.h> 25 #include <linux/ioport.h> 26 #include <linux/delay.h> 27 #include <linux/console.h> 28 #include <linux/init.h> 29 #include <linux/memblock.h> 30 #include <linux/seq_file.h> 31 #include <linux/serial.h> 32 #include <linux/initrd.h> 33 #include <linux/of_fdt.h> 34 #include <linux/of.h> 35 #include <linux/device.h> 36 37 #include <asm/sections.h> 38 #include <asm/types.h> 39 #include <asm/setup.h> 40 #include <asm/io.h> 41 #include <asm/cpuinfo.h> 42 #include <asm/delay.h> 43 44 #include "vmlinux.h" 45 46 static void __init setup_memory(void) 47 { 48 unsigned long ram_start_pfn; 49 unsigned long ram_end_pfn; 50 phys_addr_t memory_start, memory_end; 51 struct memblock_region *region; 52 53 memory_end = memory_start = 0; 54 55 /* Find main memory where is the kernel, we assume its the only one */ 56 for_each_memblock(memory, region) { 57 memory_start = region->base; 58 memory_end = region->base + region->size; 59 printk(KERN_INFO "%s: Memory: 0x%x-0x%x\n", __func__, 60 memory_start, memory_end); 61 } 62 63 if (!memory_end) { 64 panic("No memory!"); 65 } 66 67 ram_start_pfn = PFN_UP(memory_start); 68 ram_end_pfn = PFN_DOWN(memblock_end_of_DRAM()); 69 70 /* setup bootmem globals (we use no_bootmem, but mm still depends on this) */ 71 min_low_pfn = ram_start_pfn; 72 max_low_pfn = ram_end_pfn; 73 max_pfn = ram_end_pfn; 74 75 /* 76 * initialize the boot-time allocator (with low memory only). 77 * 78 * This makes the memory from the end of the kernel to the end of 79 * RAM usable. 80 */ 81 memblock_reserve(__pa(_stext), _end - _stext); 82 83 early_init_fdt_reserve_self(); 84 early_init_fdt_scan_reserved_mem(); 85 86 memblock_dump_all(); 87 } 88 89 struct cpuinfo_or1k cpuinfo_or1k[NR_CPUS]; 90 91 static void print_cpuinfo(void) 92 { 93 unsigned long upr = mfspr(SPR_UPR); 94 unsigned long vr = mfspr(SPR_VR); 95 unsigned int version; 96 unsigned int revision; 97 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()]; 98 99 version = (vr & SPR_VR_VER) >> 24; 100 revision = (vr & SPR_VR_REV); 101 102 printk(KERN_INFO "CPU: OpenRISC-%x (revision %d) @%d MHz\n", 103 version, revision, cpuinfo->clock_frequency / 1000000); 104 105 if (!(upr & SPR_UPR_UP)) { 106 printk(KERN_INFO 107 "-- no UPR register... unable to detect configuration\n"); 108 return; 109 } 110 111 if (upr & SPR_UPR_DCP) 112 printk(KERN_INFO 113 "-- dcache: %4d bytes total, %2d bytes/line, %d way(s)\n", 114 cpuinfo->dcache_size, cpuinfo->dcache_block_size, 115 cpuinfo->dcache_ways); 116 else 117 printk(KERN_INFO "-- dcache disabled\n"); 118 if (upr & SPR_UPR_ICP) 119 printk(KERN_INFO 120 "-- icache: %4d bytes total, %2d bytes/line, %d way(s)\n", 121 cpuinfo->icache_size, cpuinfo->icache_block_size, 122 cpuinfo->icache_ways); 123 else 124 printk(KERN_INFO "-- icache disabled\n"); 125 126 if (upr & SPR_UPR_DMP) 127 printk(KERN_INFO "-- dmmu: %4d entries, %lu way(s)\n", 128 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2), 129 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW)); 130 if (upr & SPR_UPR_IMP) 131 printk(KERN_INFO "-- immu: %4d entries, %lu way(s)\n", 132 1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2), 133 1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW)); 134 135 printk(KERN_INFO "-- additional features:\n"); 136 if (upr & SPR_UPR_DUP) 137 printk(KERN_INFO "-- debug unit\n"); 138 if (upr & SPR_UPR_PCUP) 139 printk(KERN_INFO "-- performance counters\n"); 140 if (upr & SPR_UPR_PMP) 141 printk(KERN_INFO "-- power management\n"); 142 if (upr & SPR_UPR_PICP) 143 printk(KERN_INFO "-- PIC\n"); 144 if (upr & SPR_UPR_TTP) 145 printk(KERN_INFO "-- timer\n"); 146 if (upr & SPR_UPR_CUP) 147 printk(KERN_INFO "-- custom unit(s)\n"); 148 } 149 150 static struct device_node *setup_find_cpu_node(int cpu) 151 { 152 u32 hwid; 153 struct device_node *cpun; 154 155 for_each_of_cpu_node(cpun) { 156 if (of_property_read_u32(cpun, "reg", &hwid)) 157 continue; 158 if (hwid == cpu) 159 return cpun; 160 } 161 162 return NULL; 163 } 164 165 void __init setup_cpuinfo(void) 166 { 167 struct device_node *cpu; 168 unsigned long iccfgr, dccfgr; 169 unsigned long cache_set_size; 170 int cpu_id = smp_processor_id(); 171 struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu_id]; 172 173 cpu = setup_find_cpu_node(cpu_id); 174 if (!cpu) 175 panic("Couldn't find CPU%d in device tree...\n", cpu_id); 176 177 iccfgr = mfspr(SPR_ICCFGR); 178 cpuinfo->icache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW); 179 cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3); 180 cpuinfo->icache_block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7); 181 cpuinfo->icache_size = 182 cache_set_size * cpuinfo->icache_ways * cpuinfo->icache_block_size; 183 184 dccfgr = mfspr(SPR_DCCFGR); 185 cpuinfo->dcache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW); 186 cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3); 187 cpuinfo->dcache_block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7); 188 cpuinfo->dcache_size = 189 cache_set_size * cpuinfo->dcache_ways * cpuinfo->dcache_block_size; 190 191 if (of_property_read_u32(cpu, "clock-frequency", 192 &cpuinfo->clock_frequency)) { 193 printk(KERN_WARNING 194 "Device tree missing CPU 'clock-frequency' parameter." 195 "Assuming frequency 25MHZ" 196 "This is probably not what you want."); 197 } 198 199 cpuinfo->coreid = mfspr(SPR_COREID); 200 201 of_node_put(cpu); 202 203 print_cpuinfo(); 204 } 205 206 /** 207 * or32_early_setup 208 * 209 * Handles the pointer to the device tree that this kernel is to use 210 * for establishing the available platform devices. 211 * 212 * Falls back on built-in device tree in case null pointer is passed. 213 */ 214 215 void __init or32_early_setup(void *fdt) 216 { 217 if (fdt) 218 pr_info("FDT at %p\n", fdt); 219 else { 220 fdt = __dtb_start; 221 pr_info("Compiled-in FDT at %p\n", fdt); 222 } 223 early_init_devtree(fdt); 224 } 225 226 static inline unsigned long extract_value_bits(unsigned long reg, 227 short bit_nr, short width) 228 { 229 return (reg >> bit_nr) & (0 << width); 230 } 231 232 static inline unsigned long extract_value(unsigned long reg, unsigned long mask) 233 { 234 while (!(mask & 0x1)) { 235 reg = reg >> 1; 236 mask = mask >> 1; 237 } 238 return mask & reg; 239 } 240 241 void __init detect_unit_config(unsigned long upr, unsigned long mask, 242 char *text, void (*func) (void)) 243 { 244 if (text != NULL) 245 printk("%s", text); 246 247 if (upr & mask) { 248 if (func != NULL) 249 func(); 250 else 251 printk("present\n"); 252 } else 253 printk("not present\n"); 254 } 255 256 /* 257 * calibrate_delay 258 * 259 * Lightweight calibrate_delay implementation that calculates loops_per_jiffy 260 * from the clock frequency passed in via the device tree 261 * 262 */ 263 264 void calibrate_delay(void) 265 { 266 const int *val; 267 struct device_node *cpu = setup_find_cpu_node(smp_processor_id()); 268 269 val = of_get_property(cpu, "clock-frequency", NULL); 270 if (!val) 271 panic("no cpu 'clock-frequency' parameter in device tree"); 272 loops_per_jiffy = *val / HZ; 273 pr_cont("%lu.%02lu BogoMIPS (lpj=%lu)\n", 274 loops_per_jiffy / (500000 / HZ), 275 (loops_per_jiffy / (5000 / HZ)) % 100, loops_per_jiffy); 276 } 277 278 void __init setup_arch(char **cmdline_p) 279 { 280 unflatten_and_copy_device_tree(); 281 282 setup_cpuinfo(); 283 284 #ifdef CONFIG_SMP 285 smp_init_cpus(); 286 #endif 287 288 /* process 1's initial memory region is the kernel code/data */ 289 init_mm.start_code = (unsigned long)_stext; 290 init_mm.end_code = (unsigned long)_etext; 291 init_mm.end_data = (unsigned long)_edata; 292 init_mm.brk = (unsigned long)_end; 293 294 #ifdef CONFIG_BLK_DEV_INITRD 295 if (initrd_start == initrd_end) { 296 printk(KERN_INFO "Initial ramdisk not found\n"); 297 initrd_start = 0; 298 initrd_end = 0; 299 } else { 300 printk(KERN_INFO "Initial ramdisk at: 0x%p (%lu bytes)\n", 301 (void *)(initrd_start), initrd_end - initrd_start); 302 initrd_below_start_ok = 1; 303 } 304 #endif 305 306 /* setup memblock allocator */ 307 setup_memory(); 308 309 /* paging_init() sets up the MMU and marks all pages as reserved */ 310 paging_init(); 311 312 *cmdline_p = boot_command_line; 313 314 printk(KERN_INFO "OpenRISC Linux -- http://openrisc.io\n"); 315 } 316 317 static int show_cpuinfo(struct seq_file *m, void *v) 318 { 319 unsigned int vr, cpucfgr; 320 unsigned int avr; 321 unsigned int version; 322 struct cpuinfo_or1k *cpuinfo = v; 323 324 vr = mfspr(SPR_VR); 325 cpucfgr = mfspr(SPR_CPUCFGR); 326 327 #ifdef CONFIG_SMP 328 seq_printf(m, "processor\t\t: %d\n", cpuinfo->coreid); 329 #endif 330 if (vr & SPR_VR_UVRP) { 331 vr = mfspr(SPR_VR2); 332 version = vr & SPR_VR2_VER; 333 avr = mfspr(SPR_AVR); 334 seq_printf(m, "cpu architecture\t: " 335 "OpenRISC 1000 (%d.%d-rev%d)\n", 336 (avr >> 24) & 0xff, 337 (avr >> 16) & 0xff, 338 (avr >> 8) & 0xff); 339 seq_printf(m, "cpu implementation id\t: 0x%x\n", 340 (vr & SPR_VR2_CPUID) >> 24); 341 seq_printf(m, "cpu version\t\t: 0x%x\n", version); 342 } else { 343 version = (vr & SPR_VR_VER) >> 24; 344 seq_printf(m, "cpu\t\t\t: OpenRISC-%x\n", version); 345 seq_printf(m, "revision\t\t: %d\n", vr & SPR_VR_REV); 346 } 347 seq_printf(m, "frequency\t\t: %ld\n", loops_per_jiffy * HZ); 348 seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache_size); 349 seq_printf(m, "dcache block size\t: %d bytes\n", 350 cpuinfo->dcache_block_size); 351 seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache_ways); 352 seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache_size); 353 seq_printf(m, "icache block size\t: %d bytes\n", 354 cpuinfo->icache_block_size); 355 seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache_ways); 356 seq_printf(m, "immu\t\t\t: %d entries, %lu ways\n", 357 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2), 358 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW)); 359 seq_printf(m, "dmmu\t\t\t: %d entries, %lu ways\n", 360 1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2), 361 1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW)); 362 seq_printf(m, "bogomips\t\t: %lu.%02lu\n", 363 (loops_per_jiffy * HZ) / 500000, 364 ((loops_per_jiffy * HZ) / 5000) % 100); 365 366 seq_puts(m, "features\t\t: "); 367 seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OB32S ? "orbis32" : ""); 368 seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OB64S ? "orbis64" : ""); 369 seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OF32S ? "orfpx32" : ""); 370 seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OF64S ? "orfpx64" : ""); 371 seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OV64S ? "orvdx64" : ""); 372 seq_puts(m, "\n"); 373 374 seq_puts(m, "\n"); 375 376 return 0; 377 } 378 379 static void *c_start(struct seq_file *m, loff_t *pos) 380 { 381 *pos = cpumask_next(*pos - 1, cpu_online_mask); 382 if ((*pos) < nr_cpu_ids) 383 return &cpuinfo_or1k[*pos]; 384 return NULL; 385 } 386 387 static void *c_next(struct seq_file *m, void *v, loff_t *pos) 388 { 389 (*pos)++; 390 return c_start(m, pos); 391 } 392 393 static void c_stop(struct seq_file *m, void *v) 394 { 395 } 396 397 const struct seq_operations cpuinfo_op = { 398 .start = c_start, 399 .next = c_next, 400 .stop = c_stop, 401 .show = show_cpuinfo, 402 }; 403