1/* 2 * OpenRISC head.S 3 * 4 * Linux architectural port borrowing liberally from similar works of 5 * others. All original copyrights apply as per the original source 6 * declaration. 7 * 8 * Modifications for the OpenRISC architecture: 9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com> 10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License 14 * as published by the Free Software Foundation; either version 15 * 2 of the License, or (at your option) any later version. 16 */ 17 18#include <linux/linkage.h> 19#include <linux/threads.h> 20#include <linux/errno.h> 21#include <linux/init.h> 22#include <linux/serial_reg.h> 23#include <asm/processor.h> 24#include <asm/page.h> 25#include <asm/mmu.h> 26#include <asm/pgtable.h> 27#include <asm/thread_info.h> 28#include <asm/cache.h> 29#include <asm/spr_defs.h> 30#include <asm/asm-offsets.h> 31#include <linux/of_fdt.h> 32 33#define tophys(rd,rs) \ 34 l.movhi rd,hi(-KERNELBASE) ;\ 35 l.add rd,rd,rs 36 37#define CLEAR_GPR(gpr) \ 38 l.movhi gpr,0x0 39 40#define LOAD_SYMBOL_2_GPR(gpr,symbol) \ 41 l.movhi gpr,hi(symbol) ;\ 42 l.ori gpr,gpr,lo(symbol) 43 44 45#define UART_BASE_ADD 0x90000000 46 47#define EXCEPTION_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_SM) 48#define SYSCALL_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_IEE | SPR_SR_TEE | SPR_SR_SM) 49 50/* ============================================[ tmp store locations ]=== */ 51 52/* 53 * emergency_print temporary stores 54 */ 55#define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4 56#define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0) 57 58#define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5 59#define EMERGENCY_PRINT_LOAD_GPR5 l.lwz r5,0x24(r0) 60 61#define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6 62#define EMERGENCY_PRINT_LOAD_GPR6 l.lwz r6,0x28(r0) 63 64#define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7 65#define EMERGENCY_PRINT_LOAD_GPR7 l.lwz r7,0x2c(r0) 66 67#define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8 68#define EMERGENCY_PRINT_LOAD_GPR8 l.lwz r8,0x30(r0) 69 70#define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9 71#define EMERGENCY_PRINT_LOAD_GPR9 l.lwz r9,0x34(r0) 72 73 74/* 75 * TLB miss handlers temorary stores 76 */ 77#define EXCEPTION_STORE_GPR9 l.sw 0x10(r0),r9 78#define EXCEPTION_LOAD_GPR9 l.lwz r9,0x10(r0) 79 80#define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2 81#define EXCEPTION_LOAD_GPR2 l.lwz r2,0x64(r0) 82 83#define EXCEPTION_STORE_GPR3 l.sw 0x68(r0),r3 84#define EXCEPTION_LOAD_GPR3 l.lwz r3,0x68(r0) 85 86#define EXCEPTION_STORE_GPR4 l.sw 0x6c(r0),r4 87#define EXCEPTION_LOAD_GPR4 l.lwz r4,0x6c(r0) 88 89#define EXCEPTION_STORE_GPR5 l.sw 0x70(r0),r5 90#define EXCEPTION_LOAD_GPR5 l.lwz r5,0x70(r0) 91 92#define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6 93#define EXCEPTION_LOAD_GPR6 l.lwz r6,0x74(r0) 94 95 96/* 97 * EXCEPTION_HANDLE temporary stores 98 */ 99 100#define EXCEPTION_T_STORE_GPR30 l.sw 0x78(r0),r30 101#define EXCEPTION_T_LOAD_GPR30(reg) l.lwz reg,0x78(r0) 102 103#define EXCEPTION_T_STORE_GPR10 l.sw 0x7c(r0),r10 104#define EXCEPTION_T_LOAD_GPR10(reg) l.lwz reg,0x7c(r0) 105 106#define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1 107#define EXCEPTION_T_LOAD_SP(reg) l.lwz reg,0x80(r0) 108 109/* 110 * For UNHANLDED_EXCEPTION 111 */ 112 113#define EXCEPTION_T_STORE_GPR31 l.sw 0x84(r0),r31 114#define EXCEPTION_T_LOAD_GPR31(reg) l.lwz reg,0x84(r0) 115 116/* =========================================================[ macros ]=== */ 117 118 119#define GET_CURRENT_PGD(reg,t1) \ 120 LOAD_SYMBOL_2_GPR(reg,current_pgd) ;\ 121 tophys (t1,reg) ;\ 122 l.lwz reg,0(t1) 123 124 125/* 126 * DSCR: this is a common hook for handling exceptions. it will save 127 * the needed registers, set up stack and pointer to current 128 * then jump to the handler while enabling MMU 129 * 130 * PRMS: handler - a function to jump to. it has to save the 131 * remaining registers to kernel stack, call 132 * appropriate arch-independant exception handler 133 * and finaly jump to ret_from_except 134 * 135 * PREQ: unchanged state from the time exception happened 136 * 137 * POST: SAVED the following registers original value 138 * to the new created exception frame pointed to by r1 139 * 140 * r1 - ksp pointing to the new (exception) frame 141 * r4 - EEAR exception EA 142 * r10 - current pointing to current_thread_info struct 143 * r12 - syscall 0, since we didn't come from syscall 144 * r13 - temp it actually contains new SR, not needed anymore 145 * r31 - handler address of the handler we'll jump to 146 * 147 * handler has to save remaining registers to the exception 148 * ksp frame *before* tainting them! 149 * 150 * NOTE: this function is not reentrant per se. reentrancy is guaranteed 151 * by processor disabling all exceptions/interrupts when exception 152 * accours. 153 * 154 * OPTM: no need to make it so wasteful to extract ksp when in user mode 155 */ 156 157#define EXCEPTION_HANDLE(handler) \ 158 EXCEPTION_T_STORE_GPR30 ;\ 159 l.mfspr r30,r0,SPR_ESR_BASE ;\ 160 l.andi r30,r30,SPR_SR_SM ;\ 161 l.sfeqi r30,0 ;\ 162 EXCEPTION_T_STORE_GPR10 ;\ 163 l.bnf 2f /* kernel_mode */ ;\ 164 EXCEPTION_T_STORE_SP /* delay slot */ ;\ 1651: /* user_mode: */ ;\ 166 LOAD_SYMBOL_2_GPR(r1,current_thread_info_set) ;\ 167 tophys (r30,r1) ;\ 168 /* r10: current_thread_info */ ;\ 169 l.lwz r10,0(r30) ;\ 170 tophys (r30,r10) ;\ 171 l.lwz r1,(TI_KSP)(r30) ;\ 172 /* fall through */ ;\ 1732: /* kernel_mode: */ ;\ 174 /* create new stack frame, save only needed gprs */ ;\ 175 /* r1: KSP, r10: current, r4: EEAR, r31: __pa(KSP) */ ;\ 176 /* r12: temp, syscall indicator */ ;\ 177 l.addi r1,r1,-(INT_FRAME_SIZE) ;\ 178 /* r1 is KSP, r30 is __pa(KSP) */ ;\ 179 tophys (r30,r1) ;\ 180 l.sw PT_GPR12(r30),r12 ;\ 181 l.mfspr r12,r0,SPR_EPCR_BASE ;\ 182 l.sw PT_PC(r30),r12 ;\ 183 l.mfspr r12,r0,SPR_ESR_BASE ;\ 184 l.sw PT_SR(r30),r12 ;\ 185 /* save r30 */ ;\ 186 EXCEPTION_T_LOAD_GPR30(r12) ;\ 187 l.sw PT_GPR30(r30),r12 ;\ 188 /* save r10 as was prior to exception */ ;\ 189 EXCEPTION_T_LOAD_GPR10(r12) ;\ 190 l.sw PT_GPR10(r30),r12 ;\ 191 /* save PT_SP as was prior to exception */ ;\ 192 EXCEPTION_T_LOAD_SP(r12) ;\ 193 l.sw PT_SP(r30),r12 ;\ 194 /* save exception r4, set r4 = EA */ ;\ 195 l.sw PT_GPR4(r30),r4 ;\ 196 l.mfspr r4,r0,SPR_EEAR_BASE ;\ 197 /* r12 == 1 if we come from syscall */ ;\ 198 CLEAR_GPR(r12) ;\ 199 /* ----- turn on MMU ----- */ ;\ 200 l.ori r30,r0,(EXCEPTION_SR) ;\ 201 l.mtspr r0,r30,SPR_ESR_BASE ;\ 202 /* r30: EA address of handler */ ;\ 203 LOAD_SYMBOL_2_GPR(r30,handler) ;\ 204 l.mtspr r0,r30,SPR_EPCR_BASE ;\ 205 l.rfe 206 207/* 208 * this doesn't work 209 * 210 * 211 * #ifdef CONFIG_JUMP_UPON_UNHANDLED_EXCEPTION 212 * #define UNHANDLED_EXCEPTION(handler) \ 213 * l.ori r3,r0,0x1 ;\ 214 * l.mtspr r0,r3,SPR_SR ;\ 215 * l.movhi r3,hi(0xf0000100) ;\ 216 * l.ori r3,r3,lo(0xf0000100) ;\ 217 * l.jr r3 ;\ 218 * l.nop 1 219 * 220 * #endif 221 */ 222 223/* DSCR: this is the same as EXCEPTION_HANDLE(), we are just 224 * a bit more carefull (if we have a PT_SP or current pointer 225 * corruption) and set them up from 'current_set' 226 * 227 */ 228#define UNHANDLED_EXCEPTION(handler) \ 229 EXCEPTION_T_STORE_GPR31 ;\ 230 EXCEPTION_T_STORE_GPR10 ;\ 231 EXCEPTION_T_STORE_SP ;\ 232 /* temporary store r3, r9 into r1, r10 */ ;\ 233 l.addi r1,r3,0x0 ;\ 234 l.addi r10,r9,0x0 ;\ 235 /* the string referenced by r3 must be low enough */ ;\ 236 l.jal _emergency_print ;\ 237 l.ori r3,r0,lo(_string_unhandled_exception) ;\ 238 l.mfspr r3,r0,SPR_NPC ;\ 239 l.jal _emergency_print_nr ;\ 240 l.andi r3,r3,0x1f00 ;\ 241 /* the string referenced by r3 must be low enough */ ;\ 242 l.jal _emergency_print ;\ 243 l.ori r3,r0,lo(_string_epc_prefix) ;\ 244 l.jal _emergency_print_nr ;\ 245 l.mfspr r3,r0,SPR_EPCR_BASE ;\ 246 l.jal _emergency_print ;\ 247 l.ori r3,r0,lo(_string_nl) ;\ 248 /* end of printing */ ;\ 249 l.addi r3,r1,0x0 ;\ 250 l.addi r9,r10,0x0 ;\ 251 /* extract current, ksp from current_set */ ;\ 252 LOAD_SYMBOL_2_GPR(r1,_unhandled_stack_top) ;\ 253 LOAD_SYMBOL_2_GPR(r10,init_thread_union) ;\ 254 /* create new stack frame, save only needed gprs */ ;\ 255 /* r1: KSP, r10: current, r31: __pa(KSP) */ ;\ 256 /* r12: temp, syscall indicator, r13 temp */ ;\ 257 l.addi r1,r1,-(INT_FRAME_SIZE) ;\ 258 /* r1 is KSP, r31 is __pa(KSP) */ ;\ 259 tophys (r31,r1) ;\ 260 l.sw PT_GPR12(r31),r12 ;\ 261 l.mfspr r12,r0,SPR_EPCR_BASE ;\ 262 l.sw PT_PC(r31),r12 ;\ 263 l.mfspr r12,r0,SPR_ESR_BASE ;\ 264 l.sw PT_SR(r31),r12 ;\ 265 /* save r31 */ ;\ 266 EXCEPTION_T_LOAD_GPR31(r12) ;\ 267 l.sw PT_GPR31(r31),r12 ;\ 268 /* save r10 as was prior to exception */ ;\ 269 EXCEPTION_T_LOAD_GPR10(r12) ;\ 270 l.sw PT_GPR10(r31),r12 ;\ 271 /* save PT_SP as was prior to exception */ ;\ 272 EXCEPTION_T_LOAD_SP(r12) ;\ 273 l.sw PT_SP(r31),r12 ;\ 274 l.sw PT_GPR13(r31),r13 ;\ 275 /* --> */ ;\ 276 /* save exception r4, set r4 = EA */ ;\ 277 l.sw PT_GPR4(r31),r4 ;\ 278 l.mfspr r4,r0,SPR_EEAR_BASE ;\ 279 /* r12 == 1 if we come from syscall */ ;\ 280 CLEAR_GPR(r12) ;\ 281 /* ----- play a MMU trick ----- */ ;\ 282 l.ori r31,r0,(EXCEPTION_SR) ;\ 283 l.mtspr r0,r31,SPR_ESR_BASE ;\ 284 /* r31: EA address of handler */ ;\ 285 LOAD_SYMBOL_2_GPR(r31,handler) ;\ 286 l.mtspr r0,r31,SPR_EPCR_BASE ;\ 287 l.rfe 288 289/* =====================================================[ exceptions] === */ 290 291/* ---[ 0x100: RESET exception ]----------------------------------------- */ 292 .org 0x100 293 /* Jump to .init code at _start which lives in the .head section 294 * and will be discarded after boot. 295 */ 296 LOAD_SYMBOL_2_GPR(r15, _start) 297 tophys (r13,r15) /* MMU disabled */ 298 l.jr r13 299 l.nop 300 301/* ---[ 0x200: BUS exception ]------------------------------------------- */ 302 .org 0x200 303_dispatch_bus_fault: 304 EXCEPTION_HANDLE(_bus_fault_handler) 305 306/* ---[ 0x300: Data Page Fault exception ]------------------------------- */ 307 .org 0x300 308_dispatch_do_dpage_fault: 309// totaly disable timer interrupt 310// l.mtspr r0,r0,SPR_TTMR 311// DEBUG_TLB_PROBE(0x300) 312// EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x300) 313 EXCEPTION_HANDLE(_data_page_fault_handler) 314 315/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */ 316 .org 0x400 317_dispatch_do_ipage_fault: 318// totaly disable timer interrupt 319// l.mtspr r0,r0,SPR_TTMR 320// DEBUG_TLB_PROBE(0x400) 321// EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x400) 322 EXCEPTION_HANDLE(_insn_page_fault_handler) 323 324/* ---[ 0x500: Timer exception ]----------------------------------------- */ 325 .org 0x500 326 EXCEPTION_HANDLE(_timer_handler) 327 328/* ---[ 0x600: Alignment exception ]-------------------------------------- */ 329 .org 0x600 330 EXCEPTION_HANDLE(_alignment_handler) 331 332/* ---[ 0x700: Illegal insn exception ]---------------------------------- */ 333 .org 0x700 334 EXCEPTION_HANDLE(_illegal_instruction_handler) 335 336/* ---[ 0x800: External interrupt exception ]---------------------------- */ 337 .org 0x800 338 EXCEPTION_HANDLE(_external_irq_handler) 339 340/* ---[ 0x900: DTLB miss exception ]------------------------------------- */ 341 .org 0x900 342 l.j boot_dtlb_miss_handler 343 l.nop 344 345/* ---[ 0xa00: ITLB miss exception ]------------------------------------- */ 346 .org 0xa00 347 l.j boot_itlb_miss_handler 348 l.nop 349 350/* ---[ 0xb00: Range exception ]----------------------------------------- */ 351 .org 0xb00 352 UNHANDLED_EXCEPTION(_vector_0xb00) 353 354/* ---[ 0xc00: Syscall exception ]--------------------------------------- */ 355 .org 0xc00 356 EXCEPTION_HANDLE(_sys_call_handler) 357 358/* ---[ 0xd00: Trap exception ]------------------------------------------ */ 359 .org 0xd00 360 UNHANDLED_EXCEPTION(_vector_0xd00) 361 362/* ---[ 0xe00: Trap exception ]------------------------------------------ */ 363 .org 0xe00 364// UNHANDLED_EXCEPTION(_vector_0xe00) 365 EXCEPTION_HANDLE(_trap_handler) 366 367/* ---[ 0xf00: Reserved exception ]-------------------------------------- */ 368 .org 0xf00 369 UNHANDLED_EXCEPTION(_vector_0xf00) 370 371/* ---[ 0x1000: Reserved exception ]------------------------------------- */ 372 .org 0x1000 373 UNHANDLED_EXCEPTION(_vector_0x1000) 374 375/* ---[ 0x1100: Reserved exception ]------------------------------------- */ 376 .org 0x1100 377 UNHANDLED_EXCEPTION(_vector_0x1100) 378 379/* ---[ 0x1200: Reserved exception ]------------------------------------- */ 380 .org 0x1200 381 UNHANDLED_EXCEPTION(_vector_0x1200) 382 383/* ---[ 0x1300: Reserved exception ]------------------------------------- */ 384 .org 0x1300 385 UNHANDLED_EXCEPTION(_vector_0x1300) 386 387/* ---[ 0x1400: Reserved exception ]------------------------------------- */ 388 .org 0x1400 389 UNHANDLED_EXCEPTION(_vector_0x1400) 390 391/* ---[ 0x1500: Reserved exception ]------------------------------------- */ 392 .org 0x1500 393 UNHANDLED_EXCEPTION(_vector_0x1500) 394 395/* ---[ 0x1600: Reserved exception ]------------------------------------- */ 396 .org 0x1600 397 UNHANDLED_EXCEPTION(_vector_0x1600) 398 399/* ---[ 0x1700: Reserved exception ]------------------------------------- */ 400 .org 0x1700 401 UNHANDLED_EXCEPTION(_vector_0x1700) 402 403/* ---[ 0x1800: Reserved exception ]------------------------------------- */ 404 .org 0x1800 405 UNHANDLED_EXCEPTION(_vector_0x1800) 406 407/* ---[ 0x1900: Reserved exception ]------------------------------------- */ 408 .org 0x1900 409 UNHANDLED_EXCEPTION(_vector_0x1900) 410 411/* ---[ 0x1a00: Reserved exception ]------------------------------------- */ 412 .org 0x1a00 413 UNHANDLED_EXCEPTION(_vector_0x1a00) 414 415/* ---[ 0x1b00: Reserved exception ]------------------------------------- */ 416 .org 0x1b00 417 UNHANDLED_EXCEPTION(_vector_0x1b00) 418 419/* ---[ 0x1c00: Reserved exception ]------------------------------------- */ 420 .org 0x1c00 421 UNHANDLED_EXCEPTION(_vector_0x1c00) 422 423/* ---[ 0x1d00: Reserved exception ]------------------------------------- */ 424 .org 0x1d00 425 UNHANDLED_EXCEPTION(_vector_0x1d00) 426 427/* ---[ 0x1e00: Reserved exception ]------------------------------------- */ 428 .org 0x1e00 429 UNHANDLED_EXCEPTION(_vector_0x1e00) 430 431/* ---[ 0x1f00: Reserved exception ]------------------------------------- */ 432 .org 0x1f00 433 UNHANDLED_EXCEPTION(_vector_0x1f00) 434 435 .org 0x2000 436/* ===================================================[ kernel start ]=== */ 437 438/* .text*/ 439 440/* This early stuff belongs in HEAD, but some of the functions below definitely 441 * don't... */ 442 443 __HEAD 444 .global _start 445_start: 446 /* Init r0 to zero as per spec */ 447 CLEAR_GPR(r0) 448 449 /* save kernel parameters */ 450 l.or r25,r0,r3 /* pointer to fdt */ 451 452 /* 453 * ensure a deterministic start 454 */ 455 456 l.ori r3,r0,0x1 457 l.mtspr r0,r3,SPR_SR 458 459 CLEAR_GPR(r1) 460 CLEAR_GPR(r2) 461 CLEAR_GPR(r3) 462 CLEAR_GPR(r4) 463 CLEAR_GPR(r5) 464 CLEAR_GPR(r6) 465 CLEAR_GPR(r7) 466 CLEAR_GPR(r8) 467 CLEAR_GPR(r9) 468 CLEAR_GPR(r10) 469 CLEAR_GPR(r11) 470 CLEAR_GPR(r12) 471 CLEAR_GPR(r13) 472 CLEAR_GPR(r14) 473 CLEAR_GPR(r15) 474 CLEAR_GPR(r16) 475 CLEAR_GPR(r17) 476 CLEAR_GPR(r18) 477 CLEAR_GPR(r19) 478 CLEAR_GPR(r20) 479 CLEAR_GPR(r21) 480 CLEAR_GPR(r22) 481 CLEAR_GPR(r23) 482 CLEAR_GPR(r24) 483 CLEAR_GPR(r26) 484 CLEAR_GPR(r27) 485 CLEAR_GPR(r28) 486 CLEAR_GPR(r29) 487 CLEAR_GPR(r30) 488 CLEAR_GPR(r31) 489 490 /* 491 * set up initial ksp and current 492 */ 493 /* setup kernel stack */ 494 LOAD_SYMBOL_2_GPR(r1,init_thread_union + THREAD_SIZE) 495 LOAD_SYMBOL_2_GPR(r10,init_thread_union) // setup current 496 tophys (r31,r10) 497 l.sw TI_KSP(r31), r1 498 499 l.ori r4,r0,0x0 500 501 502 /* 503 * .data contains initialized data, 504 * .bss contains uninitialized data - clear it up 505 */ 506clear_bss: 507 LOAD_SYMBOL_2_GPR(r24, __bss_start) 508 LOAD_SYMBOL_2_GPR(r26, _end) 509 tophys(r28,r24) 510 tophys(r30,r26) 511 CLEAR_GPR(r24) 512 CLEAR_GPR(r26) 5131: 514 l.sw (0)(r28),r0 515 l.sfltu r28,r30 516 l.bf 1b 517 l.addi r28,r28,4 518 519enable_ic: 520 l.jal _ic_enable 521 l.nop 522 523enable_dc: 524 l.jal _dc_enable 525 l.nop 526 527flush_tlb: 528 l.jal _flush_tlb 529 l.nop 530 531/* The MMU needs to be enabled before or32_early_setup is called */ 532 533enable_mmu: 534 /* 535 * enable dmmu & immu 536 * SR[5] = 0, SR[6] = 0, 6th and 7th bit of SR set to 0 537 */ 538 l.mfspr r30,r0,SPR_SR 539 l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME) 540 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME) 541 l.or r30,r30,r28 542 l.mtspr r0,r30,SPR_SR 543 l.nop 544 l.nop 545 l.nop 546 l.nop 547 l.nop 548 l.nop 549 l.nop 550 l.nop 551 l.nop 552 l.nop 553 l.nop 554 l.nop 555 l.nop 556 l.nop 557 l.nop 558 l.nop 559 560 // reset the simulation counters 561 l.nop 5 562 563 /* check fdt header magic word */ 564 l.lwz r3,0(r25) /* load magic from fdt into r3 */ 565 l.movhi r4,hi(OF_DT_HEADER) 566 l.ori r4,r4,lo(OF_DT_HEADER) 567 l.sfeq r3,r4 568 l.bf _fdt_found 569 l.nop 570 /* magic number mismatch, set fdt pointer to null */ 571 l.or r25,r0,r0 572_fdt_found: 573 /* pass fdt pointer to or32_early_setup in r3 */ 574 l.or r3,r0,r25 575 LOAD_SYMBOL_2_GPR(r24, or32_early_setup) 576 l.jalr r24 577 l.nop 578 579clear_regs: 580 /* 581 * clear all GPRS to increase determinism 582 */ 583 CLEAR_GPR(r2) 584 CLEAR_GPR(r3) 585 CLEAR_GPR(r4) 586 CLEAR_GPR(r5) 587 CLEAR_GPR(r6) 588 CLEAR_GPR(r7) 589 CLEAR_GPR(r8) 590 CLEAR_GPR(r9) 591 CLEAR_GPR(r11) 592 CLEAR_GPR(r12) 593 CLEAR_GPR(r13) 594 CLEAR_GPR(r14) 595 CLEAR_GPR(r15) 596 CLEAR_GPR(r16) 597 CLEAR_GPR(r17) 598 CLEAR_GPR(r18) 599 CLEAR_GPR(r19) 600 CLEAR_GPR(r20) 601 CLEAR_GPR(r21) 602 CLEAR_GPR(r22) 603 CLEAR_GPR(r23) 604 CLEAR_GPR(r24) 605 CLEAR_GPR(r25) 606 CLEAR_GPR(r26) 607 CLEAR_GPR(r27) 608 CLEAR_GPR(r28) 609 CLEAR_GPR(r29) 610 CLEAR_GPR(r30) 611 CLEAR_GPR(r31) 612 613jump_start_kernel: 614 /* 615 * jump to kernel entry (start_kernel) 616 */ 617 LOAD_SYMBOL_2_GPR(r30, start_kernel) 618 l.jr r30 619 l.nop 620 621_flush_tlb: 622 /* 623 * I N V A L I D A T E T L B e n t r i e s 624 */ 625 LOAD_SYMBOL_2_GPR(r5,SPR_DTLBMR_BASE(0)) 626 LOAD_SYMBOL_2_GPR(r6,SPR_ITLBMR_BASE(0)) 627 l.addi r7,r0,128 /* Maximum number of sets */ 6281: 629 l.mtspr r5,r0,0x0 630 l.mtspr r6,r0,0x0 631 632 l.addi r5,r5,1 633 l.addi r6,r6,1 634 l.sfeq r7,r0 635 l.bnf 1b 636 l.addi r7,r7,-1 637 638 l.jr r9 639 l.nop 640 641/* ========================================[ cache ]=== */ 642 643 /* alignment here so we don't change memory offsets with 644 * memory controller defined 645 */ 646 .align 0x2000 647 648_ic_enable: 649 /* Check if IC present and skip enabling otherwise */ 650 l.mfspr r24,r0,SPR_UPR 651 l.andi r26,r24,SPR_UPR_ICP 652 l.sfeq r26,r0 653 l.bf 9f 654 l.nop 655 656 /* Disable IC */ 657 l.mfspr r6,r0,SPR_SR 658 l.addi r5,r0,-1 659 l.xori r5,r5,SPR_SR_ICE 660 l.and r5,r6,r5 661 l.mtspr r0,r5,SPR_SR 662 663 /* Establish cache block size 664 If BS=0, 16; 665 If BS=1, 32; 666 r14 contain block size 667 */ 668 l.mfspr r24,r0,SPR_ICCFGR 669 l.andi r26,r24,SPR_ICCFGR_CBS 670 l.srli r28,r26,7 671 l.ori r30,r0,16 672 l.sll r14,r30,r28 673 674 /* Establish number of cache sets 675 r16 contains number of cache sets 676 r28 contains log(# of cache sets) 677 */ 678 l.andi r26,r24,SPR_ICCFGR_NCS 679 l.srli r28,r26,3 680 l.ori r30,r0,1 681 l.sll r16,r30,r28 682 683 /* Invalidate IC */ 684 l.addi r6,r0,0 685 l.sll r5,r14,r28 686// l.mul r5,r14,r16 687// l.trap 1 688// l.addi r5,r0,IC_SIZE 6891: 690 l.mtspr r0,r6,SPR_ICBIR 691 l.sfne r6,r5 692 l.bf 1b 693 l.add r6,r6,r14 694 // l.addi r6,r6,IC_LINE 695 696 /* Enable IC */ 697 l.mfspr r6,r0,SPR_SR 698 l.ori r6,r6,SPR_SR_ICE 699 l.mtspr r0,r6,SPR_SR 700 l.nop 701 l.nop 702 l.nop 703 l.nop 704 l.nop 705 l.nop 706 l.nop 707 l.nop 708 l.nop 709 l.nop 7109: 711 l.jr r9 712 l.nop 713 714_dc_enable: 715 /* Check if DC present and skip enabling otherwise */ 716 l.mfspr r24,r0,SPR_UPR 717 l.andi r26,r24,SPR_UPR_DCP 718 l.sfeq r26,r0 719 l.bf 9f 720 l.nop 721 722 /* Disable DC */ 723 l.mfspr r6,r0,SPR_SR 724 l.addi r5,r0,-1 725 l.xori r5,r5,SPR_SR_DCE 726 l.and r5,r6,r5 727 l.mtspr r0,r5,SPR_SR 728 729 /* Establish cache block size 730 If BS=0, 16; 731 If BS=1, 32; 732 r14 contain block size 733 */ 734 l.mfspr r24,r0,SPR_DCCFGR 735 l.andi r26,r24,SPR_DCCFGR_CBS 736 l.srli r28,r26,7 737 l.ori r30,r0,16 738 l.sll r14,r30,r28 739 740 /* Establish number of cache sets 741 r16 contains number of cache sets 742 r28 contains log(# of cache sets) 743 */ 744 l.andi r26,r24,SPR_DCCFGR_NCS 745 l.srli r28,r26,3 746 l.ori r30,r0,1 747 l.sll r16,r30,r28 748 749 /* Invalidate DC */ 750 l.addi r6,r0,0 751 l.sll r5,r14,r28 7521: 753 l.mtspr r0,r6,SPR_DCBIR 754 l.sfne r6,r5 755 l.bf 1b 756 l.add r6,r6,r14 757 758 /* Enable DC */ 759 l.mfspr r6,r0,SPR_SR 760 l.ori r6,r6,SPR_SR_DCE 761 l.mtspr r0,r6,SPR_SR 7629: 763 l.jr r9 764 l.nop 765 766/* ===============================================[ page table masks ]=== */ 767 768#define DTLB_UP_CONVERT_MASK 0x3fa 769#define ITLB_UP_CONVERT_MASK 0x3a 770 771/* for SMP we'd have (this is a bit subtle, CC must be always set 772 * for SMP, but since we have _PAGE_PRESENT bit always defined 773 * we can just modify the mask) 774 */ 775#define DTLB_SMP_CONVERT_MASK 0x3fb 776#define ITLB_SMP_CONVERT_MASK 0x3b 777 778/* ---[ boot dtlb miss handler ]----------------------------------------- */ 779 780boot_dtlb_miss_handler: 781 782/* mask for DTLB_MR register: - (0) sets V (valid) bit, 783 * - (31-12) sets bits belonging to VPN (31-12) 784 */ 785#define DTLB_MR_MASK 0xfffff001 786 787/* mask for DTLB_TR register: - (2) sets CI (cache inhibit) bit, 788 * - (4) sets A (access) bit, 789 * - (5) sets D (dirty) bit, 790 * - (8) sets SRE (superuser read) bit 791 * - (9) sets SWE (superuser write) bit 792 * - (31-12) sets bits belonging to VPN (31-12) 793 */ 794#define DTLB_TR_MASK 0xfffff332 795 796/* These are for masking out the VPN/PPN value from the MR/TR registers... 797 * it's not the same as the PFN */ 798#define VPN_MASK 0xfffff000 799#define PPN_MASK 0xfffff000 800 801 802 EXCEPTION_STORE_GPR6 803 804#if 0 805 l.mfspr r6,r0,SPR_ESR_BASE // 806 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ? 807 l.sfeqi r6,0 // r6 == 0x1 --> SM 808 l.bf exit_with_no_dtranslation // 809 l.nop 810#endif 811 812 /* this could be optimized by moving storing of 813 * non r6 registers here, and jumping r6 restore 814 * if not in supervisor mode 815 */ 816 817 EXCEPTION_STORE_GPR2 818 EXCEPTION_STORE_GPR3 819 EXCEPTION_STORE_GPR4 820 EXCEPTION_STORE_GPR5 821 822 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA 823 824immediate_translation: 825 CLEAR_GPR(r6) 826 827 l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN size (4Kb) 828 829 l.mfspr r6, r0, SPR_DMMUCFGR 830 l.andi r6, r6, SPR_DMMUCFGR_NTS 831 l.srli r6, r6, SPR_DMMUCFGR_NTS_OFF 832 l.ori r5, r0, 0x1 833 l.sll r5, r5, r6 // r5 = number DMMU sets 834 l.addi r6, r5, -1 // r6 = nsets mask 835 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK 836 837 l.or r6,r6,r4 // r6 <- r4 838 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff 839 l.movhi r5,hi(DTLB_MR_MASK) // r5 <- ffff:0000.x000 840 l.ori r5,r5,lo(DTLB_MR_MASK) // r5 <- ffff:1111.x001 - apply DTLB_MR_MASK 841 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have DTLBMR entry 842 l.mtspr r2,r5,SPR_DTLBMR_BASE(0) // set DTLBMR 843 844 /* set up DTLB with no translation for EA <= 0xbfffffff */ 845 LOAD_SYMBOL_2_GPR(r6,0xbfffffff) 846 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xbfffffff >= EA) 847 l.bf 1f // goto out 848 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1) 849 850 tophys(r3,r4) // r3 <- PA 8511: 852 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff 853 l.movhi r5,hi(DTLB_TR_MASK) // r5 <- ffff:0000.x000 854 l.ori r5,r5,lo(DTLB_TR_MASK) // r5 <- ffff:1111.x330 - apply DTLB_MR_MASK 855 l.and r5,r5,r3 // r5 <- PPN :PPN .x330 - we have DTLBTR entry 856 l.mtspr r2,r5,SPR_DTLBTR_BASE(0) // set DTLBTR 857 858 EXCEPTION_LOAD_GPR6 859 EXCEPTION_LOAD_GPR5 860 EXCEPTION_LOAD_GPR4 861 EXCEPTION_LOAD_GPR3 862 EXCEPTION_LOAD_GPR2 863 864 l.rfe // SR <- ESR, PC <- EPC 865 866exit_with_no_dtranslation: 867 /* EA out of memory or not in supervisor mode */ 868 EXCEPTION_LOAD_GPR6 869 EXCEPTION_LOAD_GPR4 870 l.j _dispatch_bus_fault 871 872/* ---[ boot itlb miss handler ]----------------------------------------- */ 873 874boot_itlb_miss_handler: 875 876/* mask for ITLB_MR register: - sets V (valid) bit, 877 * - sets bits belonging to VPN (15-12) 878 */ 879#define ITLB_MR_MASK 0xfffff001 880 881/* mask for ITLB_TR register: - sets A (access) bit, 882 * - sets SXE (superuser execute) bit 883 * - sets bits belonging to VPN (15-12) 884 */ 885#define ITLB_TR_MASK 0xfffff050 886 887/* 888#define VPN_MASK 0xffffe000 889#define PPN_MASK 0xffffe000 890*/ 891 892 893 894 EXCEPTION_STORE_GPR2 895 EXCEPTION_STORE_GPR3 896 EXCEPTION_STORE_GPR4 897 EXCEPTION_STORE_GPR5 898 EXCEPTION_STORE_GPR6 899 900#if 0 901 l.mfspr r6,r0,SPR_ESR_BASE // 902 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ? 903 l.sfeqi r6,0 // r6 == 0x1 --> SM 904 l.bf exit_with_no_itranslation 905 l.nop 906#endif 907 908 909 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA 910 911earlyearly: 912 CLEAR_GPR(r6) 913 914 l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN size (4Kb) 915 916 l.mfspr r6, r0, SPR_IMMUCFGR 917 l.andi r6, r6, SPR_IMMUCFGR_NTS 918 l.srli r6, r6, SPR_IMMUCFGR_NTS_OFF 919 l.ori r5, r0, 0x1 920 l.sll r5, r5, r6 // r5 = number IMMU sets from IMMUCFGR 921 l.addi r6, r5, -1 // r6 = nsets mask 922 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK 923 924 l.or r6,r6,r4 // r6 <- r4 925 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff 926 l.movhi r5,hi(ITLB_MR_MASK) // r5 <- ffff:0000.x000 927 l.ori r5,r5,lo(ITLB_MR_MASK) // r5 <- ffff:1111.x001 - apply ITLB_MR_MASK 928 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have ITLBMR entry 929 l.mtspr r2,r5,SPR_ITLBMR_BASE(0) // set ITLBMR 930 931 /* 932 * set up ITLB with no translation for EA <= 0x0fffffff 933 * 934 * we need this for head.S mapping (EA = PA). if we move all functions 935 * which run with mmu enabled into entry.S, we might be able to eliminate this. 936 * 937 */ 938 LOAD_SYMBOL_2_GPR(r6,0x0fffffff) 939 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xb0ffffff >= EA) 940 l.bf 1f // goto out 941 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1) 942 943 tophys(r3,r4) // r3 <- PA 9441: 945 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff 946 l.movhi r5,hi(ITLB_TR_MASK) // r5 <- ffff:0000.x000 947 l.ori r5,r5,lo(ITLB_TR_MASK) // r5 <- ffff:1111.x050 - apply ITLB_MR_MASK 948 l.and r5,r5,r3 // r5 <- PPN :PPN .x050 - we have ITLBTR entry 949 l.mtspr r2,r5,SPR_ITLBTR_BASE(0) // set ITLBTR 950 951 EXCEPTION_LOAD_GPR6 952 EXCEPTION_LOAD_GPR5 953 EXCEPTION_LOAD_GPR4 954 EXCEPTION_LOAD_GPR3 955 EXCEPTION_LOAD_GPR2 956 957 l.rfe // SR <- ESR, PC <- EPC 958 959exit_with_no_itranslation: 960 EXCEPTION_LOAD_GPR4 961 EXCEPTION_LOAD_GPR6 962 l.j _dispatch_bus_fault 963 l.nop 964 965/* ====================================================================== */ 966/* 967 * Stuff below here shouldn't go into .head section... maybe this stuff 968 * can be moved to entry.S ??? 969 */ 970 971/* ==============================================[ DTLB miss handler ]=== */ 972 973/* 974 * Comments: 975 * Exception handlers are entered with MMU off so the following handler 976 * needs to use physical addressing 977 * 978 */ 979 980 .text 981ENTRY(dtlb_miss_handler) 982 EXCEPTION_STORE_GPR2 983 EXCEPTION_STORE_GPR3 984 EXCEPTION_STORE_GPR4 985 /* 986 * get EA of the miss 987 */ 988 l.mfspr r2,r0,SPR_EEAR_BASE 989 /* 990 * pmd = (pmd_t *)(current_pgd + pgd_index(daddr)); 991 */ 992 GET_CURRENT_PGD(r3,r4) // r3 is current_pgd, r4 is temp 993 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2) 994 l.slli r4,r4,0x2 // to get address << 2 995 l.add r3,r4,r3 // r4 is pgd_index(daddr) 996 /* 997 * if (pmd_none(*pmd)) 998 * goto pmd_none: 999 */ 1000 tophys (r4,r3) 1001 l.lwz r3,0x0(r4) // get *pmd value 1002 l.sfne r3,r0 1003 l.bnf d_pmd_none 1004 l.addi r3,r0,0xffffe000 // PAGE_MASK 1005 1006d_pmd_good: 1007 /* 1008 * pte = *pte_offset(pmd, daddr); 1009 */ 1010 l.lwz r4,0x0(r4) // get **pmd value 1011 l.and r4,r4,r3 // & PAGE_MASK 1012 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR 1013 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1 1014 l.slli r3,r3,0x2 // to get address << 2 1015 l.add r3,r3,r4 1016 l.lwz r3,0x0(r3) // this is pte at last 1017 /* 1018 * if (!pte_present(pte)) 1019 */ 1020 l.andi r4,r3,0x1 1021 l.sfne r4,r0 // is pte present 1022 l.bnf d_pte_not_present 1023 l.addi r4,r0,0xffffe3fa // PAGE_MASK | DTLB_UP_CONVERT_MASK 1024 /* 1025 * fill DTLB TR register 1026 */ 1027 l.and r4,r3,r4 // apply the mask 1028 // Determine number of DMMU sets 1029 l.mfspr r2, r0, SPR_DMMUCFGR 1030 l.andi r2, r2, SPR_DMMUCFGR_NTS 1031 l.srli r2, r2, SPR_DMMUCFGR_NTS_OFF 1032 l.ori r3, r0, 0x1 1033 l.sll r3, r3, r2 // r3 = number DMMU sets DMMUCFGR 1034 l.addi r2, r3, -1 // r2 = nsets mask 1035 l.mfspr r3, r0, SPR_EEAR_BASE 1036 l.srli r3, r3, 0xd // >> PAGE_SHIFT 1037 l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1) 1038 //NUM_TLB_ENTRIES 1039 l.mtspr r2,r4,SPR_DTLBTR_BASE(0) 1040 /* 1041 * fill DTLB MR register 1042 */ 1043 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */ 1044 l.ori r4,r3,0x1 // set hardware valid bit: DTBL_MR entry 1045 l.mtspr r2,r4,SPR_DTLBMR_BASE(0) 1046 1047 EXCEPTION_LOAD_GPR2 1048 EXCEPTION_LOAD_GPR3 1049 EXCEPTION_LOAD_GPR4 1050 l.rfe 1051d_pmd_none: 1052d_pte_not_present: 1053 EXCEPTION_LOAD_GPR2 1054 EXCEPTION_LOAD_GPR3 1055 EXCEPTION_LOAD_GPR4 1056 EXCEPTION_HANDLE(_dtlb_miss_page_fault_handler) 1057 1058/* ==============================================[ ITLB miss handler ]=== */ 1059ENTRY(itlb_miss_handler) 1060 EXCEPTION_STORE_GPR2 1061 EXCEPTION_STORE_GPR3 1062 EXCEPTION_STORE_GPR4 1063 /* 1064 * get EA of the miss 1065 */ 1066 l.mfspr r2,r0,SPR_EEAR_BASE 1067 1068 /* 1069 * pmd = (pmd_t *)(current_pgd + pgd_index(daddr)); 1070 * 1071 */ 1072 GET_CURRENT_PGD(r3,r4) // r3 is current_pgd, r5 is temp 1073 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2) 1074 l.slli r4,r4,0x2 // to get address << 2 1075 l.add r3,r4,r3 // r4 is pgd_index(daddr) 1076 /* 1077 * if (pmd_none(*pmd)) 1078 * goto pmd_none: 1079 */ 1080 tophys (r4,r3) 1081 l.lwz r3,0x0(r4) // get *pmd value 1082 l.sfne r3,r0 1083 l.bnf i_pmd_none 1084 l.addi r3,r0,0xffffe000 // PAGE_MASK 1085 1086i_pmd_good: 1087 /* 1088 * pte = *pte_offset(pmd, iaddr); 1089 * 1090 */ 1091 l.lwz r4,0x0(r4) // get **pmd value 1092 l.and r4,r4,r3 // & PAGE_MASK 1093 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR 1094 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1 1095 l.slli r3,r3,0x2 // to get address << 2 1096 l.add r3,r3,r4 1097 l.lwz r3,0x0(r3) // this is pte at last 1098 /* 1099 * if (!pte_present(pte)) 1100 * 1101 */ 1102 l.andi r4,r3,0x1 1103 l.sfne r4,r0 // is pte present 1104 l.bnf i_pte_not_present 1105 l.addi r4,r0,0xffffe03a // PAGE_MASK | ITLB_UP_CONVERT_MASK 1106 /* 1107 * fill ITLB TR register 1108 */ 1109 l.and r4,r3,r4 // apply the mask 1110 l.andi r3,r3,0x7c0 // _PAGE_EXEC | _PAGE_SRE | _PAGE_SWE | _PAGE_URE | _PAGE_UWE 1111 l.sfeq r3,r0 1112 l.bf itlb_tr_fill //_workaround 1113 // Determine number of IMMU sets 1114 l.mfspr r2, r0, SPR_IMMUCFGR 1115 l.andi r2, r2, SPR_IMMUCFGR_NTS 1116 l.srli r2, r2, SPR_IMMUCFGR_NTS_OFF 1117 l.ori r3, r0, 0x1 1118 l.sll r3, r3, r2 // r3 = number IMMU sets IMMUCFGR 1119 l.addi r2, r3, -1 // r2 = nsets mask 1120 l.mfspr r3, r0, SPR_EEAR_BASE 1121 l.srli r3, r3, 0xd // >> PAGE_SHIFT 1122 l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1) 1123 1124/* 1125 * __PHX__ :: fixme 1126 * we should not just blindly set executable flags, 1127 * but it does help with ping. the clean way would be to find out 1128 * (and fix it) why stack doesn't have execution permissions 1129 */ 1130 1131itlb_tr_fill_workaround: 1132 l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE) 1133itlb_tr_fill: 1134 l.mtspr r2,r4,SPR_ITLBTR_BASE(0) 1135 /* 1136 * fill DTLB MR register 1137 */ 1138 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */ 1139 l.ori r4,r3,0x1 // set hardware valid bit: ITBL_MR entry 1140 l.mtspr r2,r4,SPR_ITLBMR_BASE(0) 1141 1142 EXCEPTION_LOAD_GPR2 1143 EXCEPTION_LOAD_GPR3 1144 EXCEPTION_LOAD_GPR4 1145 l.rfe 1146 1147i_pmd_none: 1148i_pte_not_present: 1149 EXCEPTION_LOAD_GPR2 1150 EXCEPTION_LOAD_GPR3 1151 EXCEPTION_LOAD_GPR4 1152 EXCEPTION_HANDLE(_itlb_miss_page_fault_handler) 1153 1154/* ==============================================[ boot tlb handlers ]=== */ 1155 1156 1157/* =================================================[ debugging aids ]=== */ 1158 1159 .align 64 1160_immu_trampoline: 1161 .space 64 1162_immu_trampoline_top: 1163 1164#define TRAMP_SLOT_0 (0x0) 1165#define TRAMP_SLOT_1 (0x4) 1166#define TRAMP_SLOT_2 (0x8) 1167#define TRAMP_SLOT_3 (0xc) 1168#define TRAMP_SLOT_4 (0x10) 1169#define TRAMP_SLOT_5 (0x14) 1170#define TRAMP_FRAME_SIZE (0x18) 1171 1172ENTRY(_immu_trampoline_workaround) 1173 // r2 EEA 1174 // r6 is physical EEA 1175 tophys(r6,r2) 1176 1177 LOAD_SYMBOL_2_GPR(r5,_immu_trampoline) 1178 tophys (r3,r5) // r3 is trampoline (physical) 1179 1180 LOAD_SYMBOL_2_GPR(r4,0x15000000) 1181 l.sw TRAMP_SLOT_0(r3),r4 1182 l.sw TRAMP_SLOT_1(r3),r4 1183 l.sw TRAMP_SLOT_4(r3),r4 1184 l.sw TRAMP_SLOT_5(r3),r4 1185 1186 // EPC = EEA - 0x4 1187 l.lwz r4,0x0(r6) // load op @ EEA + 0x0 (fc address) 1188 l.sw TRAMP_SLOT_3(r3),r4 // store it to _immu_trampoline_data 1189 l.lwz r4,-0x4(r6) // load op @ EEA - 0x4 (f8 address) 1190 l.sw TRAMP_SLOT_2(r3),r4 // store it to _immu_trampoline_data 1191 1192 l.srli r5,r4,26 // check opcode for write access 1193 l.sfeqi r5,0 // l.j 1194 l.bf 0f 1195 l.sfeqi r5,0x11 // l.jr 1196 l.bf 1f 1197 l.sfeqi r5,1 // l.jal 1198 l.bf 2f 1199 l.sfeqi r5,0x12 // l.jalr 1200 l.bf 3f 1201 l.sfeqi r5,3 // l.bnf 1202 l.bf 4f 1203 l.sfeqi r5,4 // l.bf 1204 l.bf 5f 120599: 1206 l.nop 1207 l.j 99b // should never happen 1208 l.nop 1 1209 1210 // r2 is EEA 1211 // r3 is trampoline address (physical) 1212 // r4 is instruction 1213 // r6 is physical(EEA) 1214 // 1215 // r5 1216 12172: // l.jal 1218 1219 /* 19 20 aa aa l.movhi r9,0xaaaa 1220 * a9 29 bb bb l.ori r9,0xbbbb 1221 * 1222 * where 0xaaaabbbb is EEA + 0x4 shifted right 2 1223 */ 1224 1225 l.addi r6,r2,0x4 // this is 0xaaaabbbb 1226 1227 // l.movhi r9,0xaaaa 1228 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9 1229 l.sh (TRAMP_SLOT_0+0x0)(r3),r5 1230 l.srli r5,r6,16 1231 l.sh (TRAMP_SLOT_0+0x2)(r3),r5 1232 1233 // l.ori r9,0xbbbb 1234 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9 1235 l.sh (TRAMP_SLOT_1+0x0)(r3),r5 1236 l.andi r5,r6,0xffff 1237 l.sh (TRAMP_SLOT_1+0x2)(r3),r5 1238 1239 /* falthrough, need to set up new jump offset */ 1240 1241 12420: // l.j 1243 l.slli r6,r4,6 // original offset shifted left 6 - 2 1244// l.srli r6,r6,6 // original offset shifted right 2 1245 1246 l.slli r4,r2,4 // old jump position: EEA shifted left 4 1247// l.srli r4,r4,6 // old jump position: shifted right 2 1248 1249 l.addi r5,r3,0xc // new jump position (physical) 1250 l.slli r5,r5,4 // new jump position: shifted left 4 1251 1252 // calculate new jump offset 1253 // new_off = old_off + (old_jump - new_jump) 1254 1255 l.sub r5,r4,r5 // old_jump - new_jump 1256 l.add r5,r6,r5 // orig_off + (old_jump - new_jump) 1257 l.srli r5,r5,6 // new offset shifted right 2 1258 1259 // r5 is new jump offset 1260 // l.j has opcode 0x0... 1261 l.sw TRAMP_SLOT_2(r3),r5 // write it back 1262 1263 l.j trampoline_out 1264 l.nop 1265 1266/* ----------------------------- */ 1267 12683: // l.jalr 1269 1270 /* 19 20 aa aa l.movhi r9,0xaaaa 1271 * a9 29 bb bb l.ori r9,0xbbbb 1272 * 1273 * where 0xaaaabbbb is EEA + 0x4 shifted right 2 1274 */ 1275 1276 l.addi r6,r2,0x4 // this is 0xaaaabbbb 1277 1278 // l.movhi r9,0xaaaa 1279 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9 1280 l.sh (TRAMP_SLOT_0+0x0)(r3),r5 1281 l.srli r5,r6,16 1282 l.sh (TRAMP_SLOT_0+0x2)(r3),r5 1283 1284 // l.ori r9,0xbbbb 1285 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9 1286 l.sh (TRAMP_SLOT_1+0x0)(r3),r5 1287 l.andi r5,r6,0xffff 1288 l.sh (TRAMP_SLOT_1+0x2)(r3),r5 1289 1290 l.lhz r5,(TRAMP_SLOT_2+0x0)(r3) // load hi part of jump instruction 1291 l.andi r5,r5,0x3ff // clear out opcode part 1292 l.ori r5,r5,0x4400 // opcode changed from l.jalr -> l.jr 1293 l.sh (TRAMP_SLOT_2+0x0)(r3),r5 // write it back 1294 1295 /* falthrough */ 1296 12971: // l.jr 1298 l.j trampoline_out 1299 l.nop 1300 1301/* ----------------------------- */ 1302 13034: // l.bnf 13045: // l.bf 1305 l.slli r6,r4,6 // original offset shifted left 6 - 2 1306// l.srli r6,r6,6 // original offset shifted right 2 1307 1308 l.slli r4,r2,4 // old jump position: EEA shifted left 4 1309// l.srli r4,r4,6 // old jump position: shifted right 2 1310 1311 l.addi r5,r3,0xc // new jump position (physical) 1312 l.slli r5,r5,4 // new jump position: shifted left 4 1313 1314 // calculate new jump offset 1315 // new_off = old_off + (old_jump - new_jump) 1316 1317 l.add r6,r6,r4 // (orig_off + old_jump) 1318 l.sub r6,r6,r5 // (orig_off + old_jump) - new_jump 1319 l.srli r6,r6,6 // new offset shifted right 2 1320 1321 // r6 is new jump offset 1322 l.lwz r4,(TRAMP_SLOT_2+0x0)(r3) // load jump instruction 1323 l.srli r4,r4,16 1324 l.andi r4,r4,0xfc00 // get opcode part 1325 l.slli r4,r4,16 1326 l.or r6,r4,r6 // l.b(n)f new offset 1327 l.sw TRAMP_SLOT_2(r3),r6 // write it back 1328 1329 /* we need to add l.j to EEA + 0x8 */ 1330 tophys (r4,r2) // may not be needed (due to shifts down_ 1331 l.addi r4,r4,(0x8 - 0x8) // jump target = r2 + 0x8 (compensate for 0x8) 1332 // jump position = r5 + 0x8 (0x8 compensated) 1333 l.sub r4,r4,r5 // jump offset = target - new_position + 0x8 1334 1335 l.slli r4,r4,4 // the amount of info in imediate of jump 1336 l.srli r4,r4,6 // jump instruction with offset 1337 l.sw TRAMP_SLOT_4(r3),r4 // write it to 4th slot 1338 1339 /* fallthrough */ 1340 1341trampoline_out: 1342 // set up new EPC to point to our trampoline code 1343 LOAD_SYMBOL_2_GPR(r5,_immu_trampoline) 1344 l.mtspr r0,r5,SPR_EPCR_BASE 1345 1346 // immu_trampoline is (4x) CACHE_LINE aligned 1347 // and only 6 instructions long, 1348 // so we need to invalidate only 2 lines 1349 1350 /* Establish cache block size 1351 If BS=0, 16; 1352 If BS=1, 32; 1353 r14 contain block size 1354 */ 1355 l.mfspr r21,r0,SPR_ICCFGR 1356 l.andi r21,r21,SPR_ICCFGR_CBS 1357 l.srli r21,r21,7 1358 l.ori r23,r0,16 1359 l.sll r14,r23,r21 1360 1361 l.mtspr r0,r5,SPR_ICBIR 1362 l.add r5,r5,r14 1363 l.mtspr r0,r5,SPR_ICBIR 1364 1365 l.jr r9 1366 l.nop 1367 1368 1369/* 1370 * DSCR: prints a string referenced by r3. 1371 * 1372 * PRMS: r3 - address of the first character of null 1373 * terminated string to be printed 1374 * 1375 * PREQ: UART at UART_BASE_ADD has to be initialized 1376 * 1377 * POST: caller should be aware that r3, r9 are changed 1378 */ 1379ENTRY(_emergency_print) 1380 EMERGENCY_PRINT_STORE_GPR4 1381 EMERGENCY_PRINT_STORE_GPR5 1382 EMERGENCY_PRINT_STORE_GPR6 1383 EMERGENCY_PRINT_STORE_GPR7 13842: 1385 l.lbz r7,0(r3) 1386 l.sfeq r7,r0 1387 l.bf 9f 1388 l.nop 1389 1390// putc: 1391 l.movhi r4,hi(UART_BASE_ADD) 1392 1393 l.addi r6,r0,0x20 13941: l.lbz r5,5(r4) 1395 l.andi r5,r5,0x20 1396 l.sfeq r5,r6 1397 l.bnf 1b 1398 l.nop 1399 1400 l.sb 0(r4),r7 1401 1402 l.addi r6,r0,0x60 14031: l.lbz r5,5(r4) 1404 l.andi r5,r5,0x60 1405 l.sfeq r5,r6 1406 l.bnf 1b 1407 l.nop 1408 1409 /* next character */ 1410 l.j 2b 1411 l.addi r3,r3,0x1 1412 14139: 1414 EMERGENCY_PRINT_LOAD_GPR7 1415 EMERGENCY_PRINT_LOAD_GPR6 1416 EMERGENCY_PRINT_LOAD_GPR5 1417 EMERGENCY_PRINT_LOAD_GPR4 1418 l.jr r9 1419 l.nop 1420 1421ENTRY(_emergency_print_nr) 1422 EMERGENCY_PRINT_STORE_GPR4 1423 EMERGENCY_PRINT_STORE_GPR5 1424 EMERGENCY_PRINT_STORE_GPR6 1425 EMERGENCY_PRINT_STORE_GPR7 1426 EMERGENCY_PRINT_STORE_GPR8 1427 1428 l.addi r8,r0,32 // shift register 1429 14301: /* remove leading zeros */ 1431 l.addi r8,r8,-0x4 1432 l.srl r7,r3,r8 1433 l.andi r7,r7,0xf 1434 1435 /* don't skip the last zero if number == 0x0 */ 1436 l.sfeqi r8,0x4 1437 l.bf 2f 1438 l.nop 1439 1440 l.sfeq r7,r0 1441 l.bf 1b 1442 l.nop 1443 14442: 1445 l.srl r7,r3,r8 1446 1447 l.andi r7,r7,0xf 1448 l.sflts r8,r0 1449 l.bf 9f 1450 1451 l.sfgtui r7,0x9 1452 l.bnf 8f 1453 l.nop 1454 l.addi r7,r7,0x27 1455 14568: 1457 l.addi r7,r7,0x30 1458// putc: 1459 l.movhi r4,hi(UART_BASE_ADD) 1460 1461 l.addi r6,r0,0x20 14621: l.lbz r5,5(r4) 1463 l.andi r5,r5,0x20 1464 l.sfeq r5,r6 1465 l.bnf 1b 1466 l.nop 1467 1468 l.sb 0(r4),r7 1469 1470 l.addi r6,r0,0x60 14711: l.lbz r5,5(r4) 1472 l.andi r5,r5,0x60 1473 l.sfeq r5,r6 1474 l.bnf 1b 1475 l.nop 1476 1477 /* next character */ 1478 l.j 2b 1479 l.addi r8,r8,-0x4 1480 14819: 1482 EMERGENCY_PRINT_LOAD_GPR8 1483 EMERGENCY_PRINT_LOAD_GPR7 1484 EMERGENCY_PRINT_LOAD_GPR6 1485 EMERGENCY_PRINT_LOAD_GPR5 1486 EMERGENCY_PRINT_LOAD_GPR4 1487 l.jr r9 1488 l.nop 1489 1490 1491/* 1492 * This should be used for debugging only. 1493 * It messes up the Linux early serial output 1494 * somehow, so use it sparingly and essentially 1495 * only if you need to debug something that goes wrong 1496 * before Linux gets the early serial going. 1497 * 1498 * Furthermore, you'll have to make sure you set the 1499 * UART_DEVISOR correctly according to the system 1500 * clock rate. 1501 * 1502 * 1503 */ 1504 1505 1506 1507#define SYS_CLK 20000000 1508//#define SYS_CLK 1843200 1509#define OR32_CONSOLE_BAUD 115200 1510#define UART_DIVISOR SYS_CLK/(16*OR32_CONSOLE_BAUD) 1511 1512ENTRY(_early_uart_init) 1513 l.movhi r3,hi(UART_BASE_ADD) 1514 1515 l.addi r4,r0,0x7 1516 l.sb 0x2(r3),r4 1517 1518 l.addi r4,r0,0x0 1519 l.sb 0x1(r3),r4 1520 1521 l.addi r4,r0,0x3 1522 l.sb 0x3(r3),r4 1523 1524 l.lbz r5,3(r3) 1525 l.ori r4,r5,0x80 1526 l.sb 0x3(r3),r4 1527 l.addi r4,r0,((UART_DIVISOR>>8) & 0x000000ff) 1528 l.sb UART_DLM(r3),r4 1529 l.addi r4,r0,((UART_DIVISOR) & 0x000000ff) 1530 l.sb UART_DLL(r3),r4 1531 l.sb 0x3(r3),r5 1532 1533 l.jr r9 1534 l.nop 1535 1536 .section .rodata 1537_string_unhandled_exception: 1538 .string "\n\rRunarunaround: Unhandled exception 0x\0" 1539 1540_string_epc_prefix: 1541 .string ": EPC=0x\0" 1542 1543_string_nl: 1544 .string "\n\r\0" 1545 1546 1547/* ========================================[ page aligned structures ]=== */ 1548 1549/* 1550 * .data section should be page aligned 1551 * (look into arch/or32/kernel/vmlinux.lds) 1552 */ 1553 .section .data,"aw" 1554 .align 8192 1555 .global empty_zero_page 1556empty_zero_page: 1557 .space 8192 1558 1559 .global swapper_pg_dir 1560swapper_pg_dir: 1561 .space 8192 1562 1563 .global _unhandled_stack 1564_unhandled_stack: 1565 .space 8192 1566_unhandled_stack_top: 1567 1568/* ============================================================[ EOF ]=== */ 1569