1/* 2 * OpenRISC head.S 3 * 4 * Linux architectural port borrowing liberally from similar works of 5 * others. All original copyrights apply as per the original source 6 * declaration. 7 * 8 * Modifications for the OpenRISC architecture: 9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com> 10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License 14 * as published by the Free Software Foundation; either version 15 * 2 of the License, or (at your option) any later version. 16 */ 17 18#include <linux/linkage.h> 19#include <linux/threads.h> 20#include <linux/errno.h> 21#include <linux/init.h> 22#include <linux/serial_reg.h> 23#include <asm/processor.h> 24#include <asm/page.h> 25#include <asm/mmu.h> 26#include <asm/pgtable.h> 27#include <asm/thread_info.h> 28#include <asm/cache.h> 29#include <asm/spr_defs.h> 30#include <asm/asm-offsets.h> 31#include <linux/of_fdt.h> 32 33#define tophys(rd,rs) \ 34 l.movhi rd,hi(-KERNELBASE) ;\ 35 l.add rd,rd,rs 36 37#define CLEAR_GPR(gpr) \ 38 l.movhi gpr,0x0 39 40#define LOAD_SYMBOL_2_GPR(gpr,symbol) \ 41 l.movhi gpr,hi(symbol) ;\ 42 l.ori gpr,gpr,lo(symbol) 43 44 45#define UART_BASE_ADD 0x90000000 46 47#define EXCEPTION_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_SM) 48#define SYSCALL_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_IEE | SPR_SR_TEE | SPR_SR_SM) 49 50/* ============================================[ tmp store locations ]=== */ 51 52#define SPR_SHADOW_GPR(x) ((x) + SPR_GPR_BASE + 32) 53 54/* 55 * emergency_print temporary stores 56 */ 57#ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS 58#define EMERGENCY_PRINT_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(14) 59#define EMERGENCY_PRINT_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(14) 60 61#define EMERGENCY_PRINT_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(15) 62#define EMERGENCY_PRINT_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(15) 63 64#define EMERGENCY_PRINT_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(16) 65#define EMERGENCY_PRINT_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(16) 66 67#define EMERGENCY_PRINT_STORE_GPR7 l.mtspr r0,r7,SPR_SHADOW_GPR(7) 68#define EMERGENCY_PRINT_LOAD_GPR7 l.mfspr r7,r0,SPR_SHADOW_GPR(7) 69 70#define EMERGENCY_PRINT_STORE_GPR8 l.mtspr r0,r8,SPR_SHADOW_GPR(8) 71#define EMERGENCY_PRINT_LOAD_GPR8 l.mfspr r8,r0,SPR_SHADOW_GPR(8) 72 73#define EMERGENCY_PRINT_STORE_GPR9 l.mtspr r0,r9,SPR_SHADOW_GPR(9) 74#define EMERGENCY_PRINT_LOAD_GPR9 l.mfspr r9,r0,SPR_SHADOW_GPR(9) 75 76#else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */ 77#define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4 78#define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0) 79 80#define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5 81#define EMERGENCY_PRINT_LOAD_GPR5 l.lwz r5,0x24(r0) 82 83#define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6 84#define EMERGENCY_PRINT_LOAD_GPR6 l.lwz r6,0x28(r0) 85 86#define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7 87#define EMERGENCY_PRINT_LOAD_GPR7 l.lwz r7,0x2c(r0) 88 89#define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8 90#define EMERGENCY_PRINT_LOAD_GPR8 l.lwz r8,0x30(r0) 91 92#define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9 93#define EMERGENCY_PRINT_LOAD_GPR9 l.lwz r9,0x34(r0) 94 95#endif 96 97/* 98 * TLB miss handlers temorary stores 99 */ 100#ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS 101#define EXCEPTION_STORE_GPR2 l.mtspr r0,r2,SPR_SHADOW_GPR(2) 102#define EXCEPTION_LOAD_GPR2 l.mfspr r2,r0,SPR_SHADOW_GPR(2) 103 104#define EXCEPTION_STORE_GPR3 l.mtspr r0,r3,SPR_SHADOW_GPR(3) 105#define EXCEPTION_LOAD_GPR3 l.mfspr r3,r0,SPR_SHADOW_GPR(3) 106 107#define EXCEPTION_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(4) 108#define EXCEPTION_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(4) 109 110#define EXCEPTION_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(5) 111#define EXCEPTION_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(5) 112 113#define EXCEPTION_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(6) 114#define EXCEPTION_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(6) 115 116#else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */ 117#define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2 118#define EXCEPTION_LOAD_GPR2 l.lwz r2,0x64(r0) 119 120#define EXCEPTION_STORE_GPR3 l.sw 0x68(r0),r3 121#define EXCEPTION_LOAD_GPR3 l.lwz r3,0x68(r0) 122 123#define EXCEPTION_STORE_GPR4 l.sw 0x6c(r0),r4 124#define EXCEPTION_LOAD_GPR4 l.lwz r4,0x6c(r0) 125 126#define EXCEPTION_STORE_GPR5 l.sw 0x70(r0),r5 127#define EXCEPTION_LOAD_GPR5 l.lwz r5,0x70(r0) 128 129#define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6 130#define EXCEPTION_LOAD_GPR6 l.lwz r6,0x74(r0) 131 132#endif 133 134/* 135 * EXCEPTION_HANDLE temporary stores 136 */ 137 138#ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS 139#define EXCEPTION_T_STORE_GPR30 l.mtspr r0,r30,SPR_SHADOW_GPR(30) 140#define EXCEPTION_T_LOAD_GPR30(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(30) 141 142#define EXCEPTION_T_STORE_GPR10 l.mtspr r0,r10,SPR_SHADOW_GPR(10) 143#define EXCEPTION_T_LOAD_GPR10(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(10) 144 145#define EXCEPTION_T_STORE_SP l.mtspr r0,r1,SPR_SHADOW_GPR(1) 146#define EXCEPTION_T_LOAD_SP(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(1) 147 148#else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */ 149#define EXCEPTION_T_STORE_GPR30 l.sw 0x78(r0),r30 150#define EXCEPTION_T_LOAD_GPR30(reg) l.lwz reg,0x78(r0) 151 152#define EXCEPTION_T_STORE_GPR10 l.sw 0x7c(r0),r10 153#define EXCEPTION_T_LOAD_GPR10(reg) l.lwz reg,0x7c(r0) 154 155#define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1 156#define EXCEPTION_T_LOAD_SP(reg) l.lwz reg,0x80(r0) 157#endif 158 159/* =========================================================[ macros ]=== */ 160 161#ifdef CONFIG_SMP 162#define GET_CURRENT_PGD(reg,t1) \ 163 LOAD_SYMBOL_2_GPR(reg,current_pgd) ;\ 164 l.mfspr t1,r0,SPR_COREID ;\ 165 l.slli t1,t1,2 ;\ 166 l.add reg,reg,t1 ;\ 167 tophys (t1,reg) ;\ 168 l.lwz reg,0(t1) 169#else 170#define GET_CURRENT_PGD(reg,t1) \ 171 LOAD_SYMBOL_2_GPR(reg,current_pgd) ;\ 172 tophys (t1,reg) ;\ 173 l.lwz reg,0(t1) 174#endif 175 176/* Load r10 from current_thread_info_set - clobbers r1 and r30 */ 177#ifdef CONFIG_SMP 178#define GET_CURRENT_THREAD_INFO \ 179 LOAD_SYMBOL_2_GPR(r1,current_thread_info_set) ;\ 180 tophys (r30,r1) ;\ 181 l.mfspr r10,r0,SPR_COREID ;\ 182 l.slli r10,r10,2 ;\ 183 l.add r30,r30,r10 ;\ 184 /* r10: current_thread_info */ ;\ 185 l.lwz r10,0(r30) 186#else 187#define GET_CURRENT_THREAD_INFO \ 188 LOAD_SYMBOL_2_GPR(r1,current_thread_info_set) ;\ 189 tophys (r30,r1) ;\ 190 /* r10: current_thread_info */ ;\ 191 l.lwz r10,0(r30) 192#endif 193 194/* 195 * DSCR: this is a common hook for handling exceptions. it will save 196 * the needed registers, set up stack and pointer to current 197 * then jump to the handler while enabling MMU 198 * 199 * PRMS: handler - a function to jump to. it has to save the 200 * remaining registers to kernel stack, call 201 * appropriate arch-independant exception handler 202 * and finaly jump to ret_from_except 203 * 204 * PREQ: unchanged state from the time exception happened 205 * 206 * POST: SAVED the following registers original value 207 * to the new created exception frame pointed to by r1 208 * 209 * r1 - ksp pointing to the new (exception) frame 210 * r4 - EEAR exception EA 211 * r10 - current pointing to current_thread_info struct 212 * r12 - syscall 0, since we didn't come from syscall 213 * r13 - temp it actually contains new SR, not needed anymore 214 * r31 - handler address of the handler we'll jump to 215 * 216 * handler has to save remaining registers to the exception 217 * ksp frame *before* tainting them! 218 * 219 * NOTE: this function is not reentrant per se. reentrancy is guaranteed 220 * by processor disabling all exceptions/interrupts when exception 221 * accours. 222 * 223 * OPTM: no need to make it so wasteful to extract ksp when in user mode 224 */ 225 226#define EXCEPTION_HANDLE(handler) \ 227 EXCEPTION_T_STORE_GPR30 ;\ 228 l.mfspr r30,r0,SPR_ESR_BASE ;\ 229 l.andi r30,r30,SPR_SR_SM ;\ 230 l.sfeqi r30,0 ;\ 231 EXCEPTION_T_STORE_GPR10 ;\ 232 l.bnf 2f /* kernel_mode */ ;\ 233 EXCEPTION_T_STORE_SP /* delay slot */ ;\ 2341: /* user_mode: */ ;\ 235 GET_CURRENT_THREAD_INFO ;\ 236 tophys (r30,r10) ;\ 237 l.lwz r1,(TI_KSP)(r30) ;\ 238 /* fall through */ ;\ 2392: /* kernel_mode: */ ;\ 240 /* create new stack frame, save only needed gprs */ ;\ 241 /* r1: KSP, r10: current, r4: EEAR, r31: __pa(KSP) */ ;\ 242 /* r12: temp, syscall indicator */ ;\ 243 l.addi r1,r1,-(INT_FRAME_SIZE) ;\ 244 /* r1 is KSP, r30 is __pa(KSP) */ ;\ 245 tophys (r30,r1) ;\ 246 l.sw PT_GPR12(r30),r12 ;\ 247 l.mfspr r12,r0,SPR_EPCR_BASE ;\ 248 l.sw PT_PC(r30),r12 ;\ 249 l.mfspr r12,r0,SPR_ESR_BASE ;\ 250 l.sw PT_SR(r30),r12 ;\ 251 /* save r30 */ ;\ 252 EXCEPTION_T_LOAD_GPR30(r12) ;\ 253 l.sw PT_GPR30(r30),r12 ;\ 254 /* save r10 as was prior to exception */ ;\ 255 EXCEPTION_T_LOAD_GPR10(r12) ;\ 256 l.sw PT_GPR10(r30),r12 ;\ 257 /* save PT_SP as was prior to exception */ ;\ 258 EXCEPTION_T_LOAD_SP(r12) ;\ 259 l.sw PT_SP(r30),r12 ;\ 260 /* save exception r4, set r4 = EA */ ;\ 261 l.sw PT_GPR4(r30),r4 ;\ 262 l.mfspr r4,r0,SPR_EEAR_BASE ;\ 263 /* r12 == 1 if we come from syscall */ ;\ 264 CLEAR_GPR(r12) ;\ 265 /* ----- turn on MMU ----- */ ;\ 266 l.ori r30,r0,(EXCEPTION_SR) ;\ 267 l.mtspr r0,r30,SPR_ESR_BASE ;\ 268 /* r30: EA address of handler */ ;\ 269 LOAD_SYMBOL_2_GPR(r30,handler) ;\ 270 l.mtspr r0,r30,SPR_EPCR_BASE ;\ 271 l.rfe 272 273/* 274 * this doesn't work 275 * 276 * 277 * #ifdef CONFIG_JUMP_UPON_UNHANDLED_EXCEPTION 278 * #define UNHANDLED_EXCEPTION(handler) \ 279 * l.ori r3,r0,0x1 ;\ 280 * l.mtspr r0,r3,SPR_SR ;\ 281 * l.movhi r3,hi(0xf0000100) ;\ 282 * l.ori r3,r3,lo(0xf0000100) ;\ 283 * l.jr r3 ;\ 284 * l.nop 1 285 * 286 * #endif 287 */ 288 289/* DSCR: this is the same as EXCEPTION_HANDLE(), we are just 290 * a bit more carefull (if we have a PT_SP or current pointer 291 * corruption) and set them up from 'current_set' 292 * 293 */ 294#define UNHANDLED_EXCEPTION(handler) \ 295 EXCEPTION_T_STORE_GPR30 ;\ 296 EXCEPTION_T_STORE_GPR10 ;\ 297 EXCEPTION_T_STORE_SP ;\ 298 /* temporary store r3, r9 into r1, r10 */ ;\ 299 l.addi r1,r3,0x0 ;\ 300 l.addi r10,r9,0x0 ;\ 301 /* the string referenced by r3 must be low enough */ ;\ 302 l.jal _emergency_print ;\ 303 l.ori r3,r0,lo(_string_unhandled_exception) ;\ 304 l.mfspr r3,r0,SPR_NPC ;\ 305 l.jal _emergency_print_nr ;\ 306 l.andi r3,r3,0x1f00 ;\ 307 /* the string referenced by r3 must be low enough */ ;\ 308 l.jal _emergency_print ;\ 309 l.ori r3,r0,lo(_string_epc_prefix) ;\ 310 l.jal _emergency_print_nr ;\ 311 l.mfspr r3,r0,SPR_EPCR_BASE ;\ 312 l.jal _emergency_print ;\ 313 l.ori r3,r0,lo(_string_nl) ;\ 314 /* end of printing */ ;\ 315 l.addi r3,r1,0x0 ;\ 316 l.addi r9,r10,0x0 ;\ 317 /* extract current, ksp from current_set */ ;\ 318 LOAD_SYMBOL_2_GPR(r1,_unhandled_stack_top) ;\ 319 LOAD_SYMBOL_2_GPR(r10,init_thread_union) ;\ 320 /* create new stack frame, save only needed gprs */ ;\ 321 /* r1: KSP, r10: current, r31: __pa(KSP) */ ;\ 322 /* r12: temp, syscall indicator, r13 temp */ ;\ 323 l.addi r1,r1,-(INT_FRAME_SIZE) ;\ 324 /* r1 is KSP, r30 is __pa(KSP) */ ;\ 325 tophys (r30,r1) ;\ 326 l.sw PT_GPR12(r30),r12 ;\ 327 l.mfspr r12,r0,SPR_EPCR_BASE ;\ 328 l.sw PT_PC(r30),r12 ;\ 329 l.mfspr r12,r0,SPR_ESR_BASE ;\ 330 l.sw PT_SR(r30),r12 ;\ 331 /* save r31 */ ;\ 332 EXCEPTION_T_LOAD_GPR30(r12) ;\ 333 l.sw PT_GPR30(r30),r12 ;\ 334 /* save r10 as was prior to exception */ ;\ 335 EXCEPTION_T_LOAD_GPR10(r12) ;\ 336 l.sw PT_GPR10(r30),r12 ;\ 337 /* save PT_SP as was prior to exception */ ;\ 338 EXCEPTION_T_LOAD_SP(r12) ;\ 339 l.sw PT_SP(r30),r12 ;\ 340 l.sw PT_GPR13(r30),r13 ;\ 341 /* --> */ ;\ 342 /* save exception r4, set r4 = EA */ ;\ 343 l.sw PT_GPR4(r30),r4 ;\ 344 l.mfspr r4,r0,SPR_EEAR_BASE ;\ 345 /* r12 == 1 if we come from syscall */ ;\ 346 CLEAR_GPR(r12) ;\ 347 /* ----- play a MMU trick ----- */ ;\ 348 l.ori r30,r0,(EXCEPTION_SR) ;\ 349 l.mtspr r0,r30,SPR_ESR_BASE ;\ 350 /* r31: EA address of handler */ ;\ 351 LOAD_SYMBOL_2_GPR(r30,handler) ;\ 352 l.mtspr r0,r30,SPR_EPCR_BASE ;\ 353 l.rfe 354 355/* =====================================================[ exceptions] === */ 356 357/* ---[ 0x100: RESET exception ]----------------------------------------- */ 358 .org 0x100 359 /* Jump to .init code at _start which lives in the .head section 360 * and will be discarded after boot. 361 */ 362 LOAD_SYMBOL_2_GPR(r15, _start) 363 tophys (r13,r15) /* MMU disabled */ 364 l.jr r13 365 l.nop 366 367/* ---[ 0x200: BUS exception ]------------------------------------------- */ 368 .org 0x200 369_dispatch_bus_fault: 370 EXCEPTION_HANDLE(_bus_fault_handler) 371 372/* ---[ 0x300: Data Page Fault exception ]------------------------------- */ 373 .org 0x300 374_dispatch_do_dpage_fault: 375// totaly disable timer interrupt 376// l.mtspr r0,r0,SPR_TTMR 377// DEBUG_TLB_PROBE(0x300) 378// EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x300) 379 EXCEPTION_HANDLE(_data_page_fault_handler) 380 381/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */ 382 .org 0x400 383_dispatch_do_ipage_fault: 384// totaly disable timer interrupt 385// l.mtspr r0,r0,SPR_TTMR 386// DEBUG_TLB_PROBE(0x400) 387// EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x400) 388 EXCEPTION_HANDLE(_insn_page_fault_handler) 389 390/* ---[ 0x500: Timer exception ]----------------------------------------- */ 391 .org 0x500 392 EXCEPTION_HANDLE(_timer_handler) 393 394/* ---[ 0x600: Alignment exception ]-------------------------------------- */ 395 .org 0x600 396 EXCEPTION_HANDLE(_alignment_handler) 397 398/* ---[ 0x700: Illegal insn exception ]---------------------------------- */ 399 .org 0x700 400 EXCEPTION_HANDLE(_illegal_instruction_handler) 401 402/* ---[ 0x800: External interrupt exception ]---------------------------- */ 403 .org 0x800 404 EXCEPTION_HANDLE(_external_irq_handler) 405 406/* ---[ 0x900: DTLB miss exception ]------------------------------------- */ 407 .org 0x900 408 l.j boot_dtlb_miss_handler 409 l.nop 410 411/* ---[ 0xa00: ITLB miss exception ]------------------------------------- */ 412 .org 0xa00 413 l.j boot_itlb_miss_handler 414 l.nop 415 416/* ---[ 0xb00: Range exception ]----------------------------------------- */ 417 .org 0xb00 418 UNHANDLED_EXCEPTION(_vector_0xb00) 419 420/* ---[ 0xc00: Syscall exception ]--------------------------------------- */ 421 .org 0xc00 422 EXCEPTION_HANDLE(_sys_call_handler) 423 424/* ---[ 0xd00: Trap exception ]------------------------------------------ */ 425 .org 0xd00 426 UNHANDLED_EXCEPTION(_vector_0xd00) 427 428/* ---[ 0xe00: Trap exception ]------------------------------------------ */ 429 .org 0xe00 430// UNHANDLED_EXCEPTION(_vector_0xe00) 431 EXCEPTION_HANDLE(_trap_handler) 432 433/* ---[ 0xf00: Reserved exception ]-------------------------------------- */ 434 .org 0xf00 435 UNHANDLED_EXCEPTION(_vector_0xf00) 436 437/* ---[ 0x1000: Reserved exception ]------------------------------------- */ 438 .org 0x1000 439 UNHANDLED_EXCEPTION(_vector_0x1000) 440 441/* ---[ 0x1100: Reserved exception ]------------------------------------- */ 442 .org 0x1100 443 UNHANDLED_EXCEPTION(_vector_0x1100) 444 445/* ---[ 0x1200: Reserved exception ]------------------------------------- */ 446 .org 0x1200 447 UNHANDLED_EXCEPTION(_vector_0x1200) 448 449/* ---[ 0x1300: Reserved exception ]------------------------------------- */ 450 .org 0x1300 451 UNHANDLED_EXCEPTION(_vector_0x1300) 452 453/* ---[ 0x1400: Reserved exception ]------------------------------------- */ 454 .org 0x1400 455 UNHANDLED_EXCEPTION(_vector_0x1400) 456 457/* ---[ 0x1500: Reserved exception ]------------------------------------- */ 458 .org 0x1500 459 UNHANDLED_EXCEPTION(_vector_0x1500) 460 461/* ---[ 0x1600: Reserved exception ]------------------------------------- */ 462 .org 0x1600 463 UNHANDLED_EXCEPTION(_vector_0x1600) 464 465/* ---[ 0x1700: Reserved exception ]------------------------------------- */ 466 .org 0x1700 467 UNHANDLED_EXCEPTION(_vector_0x1700) 468 469/* ---[ 0x1800: Reserved exception ]------------------------------------- */ 470 .org 0x1800 471 UNHANDLED_EXCEPTION(_vector_0x1800) 472 473/* ---[ 0x1900: Reserved exception ]------------------------------------- */ 474 .org 0x1900 475 UNHANDLED_EXCEPTION(_vector_0x1900) 476 477/* ---[ 0x1a00: Reserved exception ]------------------------------------- */ 478 .org 0x1a00 479 UNHANDLED_EXCEPTION(_vector_0x1a00) 480 481/* ---[ 0x1b00: Reserved exception ]------------------------------------- */ 482 .org 0x1b00 483 UNHANDLED_EXCEPTION(_vector_0x1b00) 484 485/* ---[ 0x1c00: Reserved exception ]------------------------------------- */ 486 .org 0x1c00 487 UNHANDLED_EXCEPTION(_vector_0x1c00) 488 489/* ---[ 0x1d00: Reserved exception ]------------------------------------- */ 490 .org 0x1d00 491 UNHANDLED_EXCEPTION(_vector_0x1d00) 492 493/* ---[ 0x1e00: Reserved exception ]------------------------------------- */ 494 .org 0x1e00 495 UNHANDLED_EXCEPTION(_vector_0x1e00) 496 497/* ---[ 0x1f00: Reserved exception ]------------------------------------- */ 498 .org 0x1f00 499 UNHANDLED_EXCEPTION(_vector_0x1f00) 500 501 .org 0x2000 502/* ===================================================[ kernel start ]=== */ 503 504/* .text*/ 505 506/* This early stuff belongs in HEAD, but some of the functions below definitely 507 * don't... */ 508 509 __HEAD 510 .global _start 511_start: 512 /* Init r0 to zero as per spec */ 513 CLEAR_GPR(r0) 514 515 /* save kernel parameters */ 516 l.or r25,r0,r3 /* pointer to fdt */ 517 518 /* 519 * ensure a deterministic start 520 */ 521 522 l.ori r3,r0,0x1 523 l.mtspr r0,r3,SPR_SR 524 525 CLEAR_GPR(r1) 526 CLEAR_GPR(r2) 527 CLEAR_GPR(r3) 528 CLEAR_GPR(r4) 529 CLEAR_GPR(r5) 530 CLEAR_GPR(r6) 531 CLEAR_GPR(r7) 532 CLEAR_GPR(r8) 533 CLEAR_GPR(r9) 534 CLEAR_GPR(r10) 535 CLEAR_GPR(r11) 536 CLEAR_GPR(r12) 537 CLEAR_GPR(r13) 538 CLEAR_GPR(r14) 539 CLEAR_GPR(r15) 540 CLEAR_GPR(r16) 541 CLEAR_GPR(r17) 542 CLEAR_GPR(r18) 543 CLEAR_GPR(r19) 544 CLEAR_GPR(r20) 545 CLEAR_GPR(r21) 546 CLEAR_GPR(r22) 547 CLEAR_GPR(r23) 548 CLEAR_GPR(r24) 549 CLEAR_GPR(r26) 550 CLEAR_GPR(r27) 551 CLEAR_GPR(r28) 552 CLEAR_GPR(r29) 553 CLEAR_GPR(r30) 554 CLEAR_GPR(r31) 555 556#ifdef CONFIG_SMP 557 l.mfspr r26,r0,SPR_COREID 558 l.sfeq r26,r0 559 l.bnf secondary_wait 560 l.nop 561#endif 562 /* 563 * set up initial ksp and current 564 */ 565 /* setup kernel stack */ 566 LOAD_SYMBOL_2_GPR(r1,init_thread_union + THREAD_SIZE) 567 LOAD_SYMBOL_2_GPR(r10,init_thread_union) // setup current 568 tophys (r31,r10) 569 l.sw TI_KSP(r31), r1 570 571 l.ori r4,r0,0x0 572 573 574 /* 575 * .data contains initialized data, 576 * .bss contains uninitialized data - clear it up 577 */ 578clear_bss: 579 LOAD_SYMBOL_2_GPR(r24, __bss_start) 580 LOAD_SYMBOL_2_GPR(r26, _end) 581 tophys(r28,r24) 582 tophys(r30,r26) 583 CLEAR_GPR(r24) 584 CLEAR_GPR(r26) 5851: 586 l.sw (0)(r28),r0 587 l.sfltu r28,r30 588 l.bf 1b 589 l.addi r28,r28,4 590 591enable_ic: 592 l.jal _ic_enable 593 l.nop 594 595enable_dc: 596 l.jal _dc_enable 597 l.nop 598 599flush_tlb: 600 l.jal _flush_tlb 601 l.nop 602 603/* The MMU needs to be enabled before or32_early_setup is called */ 604 605enable_mmu: 606 /* 607 * enable dmmu & immu 608 * SR[5] = 0, SR[6] = 0, 6th and 7th bit of SR set to 0 609 */ 610 l.mfspr r30,r0,SPR_SR 611 l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME) 612 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME) 613 l.or r30,r30,r28 614 l.mtspr r0,r30,SPR_SR 615 l.nop 616 l.nop 617 l.nop 618 l.nop 619 l.nop 620 l.nop 621 l.nop 622 l.nop 623 l.nop 624 l.nop 625 l.nop 626 l.nop 627 l.nop 628 l.nop 629 l.nop 630 l.nop 631 632 // reset the simulation counters 633 l.nop 5 634 635 /* check fdt header magic word */ 636 l.lwz r3,0(r25) /* load magic from fdt into r3 */ 637 l.movhi r4,hi(OF_DT_HEADER) 638 l.ori r4,r4,lo(OF_DT_HEADER) 639 l.sfeq r3,r4 640 l.bf _fdt_found 641 l.nop 642 /* magic number mismatch, set fdt pointer to null */ 643 l.or r25,r0,r0 644_fdt_found: 645 /* pass fdt pointer to or32_early_setup in r3 */ 646 l.or r3,r0,r25 647 LOAD_SYMBOL_2_GPR(r24, or32_early_setup) 648 l.jalr r24 649 l.nop 650 651clear_regs: 652 /* 653 * clear all GPRS to increase determinism 654 */ 655 CLEAR_GPR(r2) 656 CLEAR_GPR(r3) 657 CLEAR_GPR(r4) 658 CLEAR_GPR(r5) 659 CLEAR_GPR(r6) 660 CLEAR_GPR(r7) 661 CLEAR_GPR(r8) 662 CLEAR_GPR(r9) 663 CLEAR_GPR(r11) 664 CLEAR_GPR(r12) 665 CLEAR_GPR(r13) 666 CLEAR_GPR(r14) 667 CLEAR_GPR(r15) 668 CLEAR_GPR(r16) 669 CLEAR_GPR(r17) 670 CLEAR_GPR(r18) 671 CLEAR_GPR(r19) 672 CLEAR_GPR(r20) 673 CLEAR_GPR(r21) 674 CLEAR_GPR(r22) 675 CLEAR_GPR(r23) 676 CLEAR_GPR(r24) 677 CLEAR_GPR(r25) 678 CLEAR_GPR(r26) 679 CLEAR_GPR(r27) 680 CLEAR_GPR(r28) 681 CLEAR_GPR(r29) 682 CLEAR_GPR(r30) 683 CLEAR_GPR(r31) 684 685jump_start_kernel: 686 /* 687 * jump to kernel entry (start_kernel) 688 */ 689 LOAD_SYMBOL_2_GPR(r30, start_kernel) 690 l.jr r30 691 l.nop 692 693_flush_tlb: 694 /* 695 * I N V A L I D A T E T L B e n t r i e s 696 */ 697 LOAD_SYMBOL_2_GPR(r5,SPR_DTLBMR_BASE(0)) 698 LOAD_SYMBOL_2_GPR(r6,SPR_ITLBMR_BASE(0)) 699 l.addi r7,r0,128 /* Maximum number of sets */ 7001: 701 l.mtspr r5,r0,0x0 702 l.mtspr r6,r0,0x0 703 704 l.addi r5,r5,1 705 l.addi r6,r6,1 706 l.sfeq r7,r0 707 l.bnf 1b 708 l.addi r7,r7,-1 709 710 l.jr r9 711 l.nop 712 713#ifdef CONFIG_SMP 714secondary_wait: 715 /* Doze the cpu until we are asked to run */ 716 /* If we dont have power management skip doze */ 717 l.mfspr r25,r0,SPR_UPR 718 l.andi r25,r25,SPR_UPR_PMP 719 l.sfeq r25,r0 720 l.bf secondary_check_release 721 l.nop 722 723 /* Setup special secondary exception handler */ 724 LOAD_SYMBOL_2_GPR(r3, _secondary_evbar) 725 tophys(r25,r3) 726 l.mtspr r0,r25,SPR_EVBAR 727 728 /* Enable Interrupts */ 729 l.mfspr r25,r0,SPR_SR 730 l.ori r25,r25,SPR_SR_IEE 731 l.mtspr r0,r25,SPR_SR 732 733 /* Unmask interrupts interrupts */ 734 l.mfspr r25,r0,SPR_PICMR 735 l.ori r25,r25,0xffff 736 l.mtspr r0,r25,SPR_PICMR 737 738 /* Doze */ 739 l.mfspr r25,r0,SPR_PMR 740 LOAD_SYMBOL_2_GPR(r3, SPR_PMR_DME) 741 l.or r25,r25,r3 742 l.mtspr r0,r25,SPR_PMR 743 744 /* Wakeup - Restore exception handler */ 745 l.mtspr r0,r0,SPR_EVBAR 746 747secondary_check_release: 748 /* 749 * Check if we actually got the release signal, if not go-back to 750 * sleep. 751 */ 752 l.mfspr r25,r0,SPR_COREID 753 LOAD_SYMBOL_2_GPR(r3, secondary_release) 754 tophys(r4, r3) 755 l.lwz r3,0(r4) 756 l.sfeq r25,r3 757 l.bnf secondary_wait 758 l.nop 759 /* fall through to secondary_init */ 760 761secondary_init: 762 /* 763 * set up initial ksp and current 764 */ 765 LOAD_SYMBOL_2_GPR(r10, secondary_thread_info) 766 tophys (r30,r10) 767 l.lwz r10,0(r30) 768 l.addi r1,r10,THREAD_SIZE 769 tophys (r30,r10) 770 l.sw TI_KSP(r30),r1 771 772 l.jal _ic_enable 773 l.nop 774 775 l.jal _dc_enable 776 l.nop 777 778 l.jal _flush_tlb 779 l.nop 780 781 /* 782 * enable dmmu & immu 783 */ 784 l.mfspr r30,r0,SPR_SR 785 l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME) 786 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME) 787 l.or r30,r30,r28 788 /* 789 * This is a bit tricky, we need to switch over from physical addresses 790 * to virtual addresses on the fly. 791 * To do that, we first set up ESR with the IME and DME bits set. 792 * Then EPCR is set to secondary_start and then a l.rfe is issued to 793 * "jump" to that. 794 */ 795 l.mtspr r0,r30,SPR_ESR_BASE 796 LOAD_SYMBOL_2_GPR(r30, secondary_start) 797 l.mtspr r0,r30,SPR_EPCR_BASE 798 l.rfe 799 800secondary_start: 801 LOAD_SYMBOL_2_GPR(r30, secondary_start_kernel) 802 l.jr r30 803 l.nop 804 805#endif 806 807/* ========================================[ cache ]=== */ 808 809 /* alignment here so we don't change memory offsets with 810 * memory controller defined 811 */ 812 .align 0x2000 813 814_ic_enable: 815 /* Check if IC present and skip enabling otherwise */ 816 l.mfspr r24,r0,SPR_UPR 817 l.andi r26,r24,SPR_UPR_ICP 818 l.sfeq r26,r0 819 l.bf 9f 820 l.nop 821 822 /* Disable IC */ 823 l.mfspr r6,r0,SPR_SR 824 l.addi r5,r0,-1 825 l.xori r5,r5,SPR_SR_ICE 826 l.and r5,r6,r5 827 l.mtspr r0,r5,SPR_SR 828 829 /* Establish cache block size 830 If BS=0, 16; 831 If BS=1, 32; 832 r14 contain block size 833 */ 834 l.mfspr r24,r0,SPR_ICCFGR 835 l.andi r26,r24,SPR_ICCFGR_CBS 836 l.srli r28,r26,7 837 l.ori r30,r0,16 838 l.sll r14,r30,r28 839 840 /* Establish number of cache sets 841 r16 contains number of cache sets 842 r28 contains log(# of cache sets) 843 */ 844 l.andi r26,r24,SPR_ICCFGR_NCS 845 l.srli r28,r26,3 846 l.ori r30,r0,1 847 l.sll r16,r30,r28 848 849 /* Invalidate IC */ 850 l.addi r6,r0,0 851 l.sll r5,r14,r28 852// l.mul r5,r14,r16 853// l.trap 1 854// l.addi r5,r0,IC_SIZE 8551: 856 l.mtspr r0,r6,SPR_ICBIR 857 l.sfne r6,r5 858 l.bf 1b 859 l.add r6,r6,r14 860 // l.addi r6,r6,IC_LINE 861 862 /* Enable IC */ 863 l.mfspr r6,r0,SPR_SR 864 l.ori r6,r6,SPR_SR_ICE 865 l.mtspr r0,r6,SPR_SR 866 l.nop 867 l.nop 868 l.nop 869 l.nop 870 l.nop 871 l.nop 872 l.nop 873 l.nop 874 l.nop 875 l.nop 8769: 877 l.jr r9 878 l.nop 879 880_dc_enable: 881 /* Check if DC present and skip enabling otherwise */ 882 l.mfspr r24,r0,SPR_UPR 883 l.andi r26,r24,SPR_UPR_DCP 884 l.sfeq r26,r0 885 l.bf 9f 886 l.nop 887 888 /* Disable DC */ 889 l.mfspr r6,r0,SPR_SR 890 l.addi r5,r0,-1 891 l.xori r5,r5,SPR_SR_DCE 892 l.and r5,r6,r5 893 l.mtspr r0,r5,SPR_SR 894 895 /* Establish cache block size 896 If BS=0, 16; 897 If BS=1, 32; 898 r14 contain block size 899 */ 900 l.mfspr r24,r0,SPR_DCCFGR 901 l.andi r26,r24,SPR_DCCFGR_CBS 902 l.srli r28,r26,7 903 l.ori r30,r0,16 904 l.sll r14,r30,r28 905 906 /* Establish number of cache sets 907 r16 contains number of cache sets 908 r28 contains log(# of cache sets) 909 */ 910 l.andi r26,r24,SPR_DCCFGR_NCS 911 l.srli r28,r26,3 912 l.ori r30,r0,1 913 l.sll r16,r30,r28 914 915 /* Invalidate DC */ 916 l.addi r6,r0,0 917 l.sll r5,r14,r28 9181: 919 l.mtspr r0,r6,SPR_DCBIR 920 l.sfne r6,r5 921 l.bf 1b 922 l.add r6,r6,r14 923 924 /* Enable DC */ 925 l.mfspr r6,r0,SPR_SR 926 l.ori r6,r6,SPR_SR_DCE 927 l.mtspr r0,r6,SPR_SR 9289: 929 l.jr r9 930 l.nop 931 932/* ===============================================[ page table masks ]=== */ 933 934#define DTLB_UP_CONVERT_MASK 0x3fa 935#define ITLB_UP_CONVERT_MASK 0x3a 936 937/* for SMP we'd have (this is a bit subtle, CC must be always set 938 * for SMP, but since we have _PAGE_PRESENT bit always defined 939 * we can just modify the mask) 940 */ 941#define DTLB_SMP_CONVERT_MASK 0x3fb 942#define ITLB_SMP_CONVERT_MASK 0x3b 943 944/* ---[ boot dtlb miss handler ]----------------------------------------- */ 945 946boot_dtlb_miss_handler: 947 948/* mask for DTLB_MR register: - (0) sets V (valid) bit, 949 * - (31-12) sets bits belonging to VPN (31-12) 950 */ 951#define DTLB_MR_MASK 0xfffff001 952 953/* mask for DTLB_TR register: - (2) sets CI (cache inhibit) bit, 954 * - (4) sets A (access) bit, 955 * - (5) sets D (dirty) bit, 956 * - (8) sets SRE (superuser read) bit 957 * - (9) sets SWE (superuser write) bit 958 * - (31-12) sets bits belonging to VPN (31-12) 959 */ 960#define DTLB_TR_MASK 0xfffff332 961 962/* These are for masking out the VPN/PPN value from the MR/TR registers... 963 * it's not the same as the PFN */ 964#define VPN_MASK 0xfffff000 965#define PPN_MASK 0xfffff000 966 967 968 EXCEPTION_STORE_GPR6 969 970#if 0 971 l.mfspr r6,r0,SPR_ESR_BASE // 972 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ? 973 l.sfeqi r6,0 // r6 == 0x1 --> SM 974 l.bf exit_with_no_dtranslation // 975 l.nop 976#endif 977 978 /* this could be optimized by moving storing of 979 * non r6 registers here, and jumping r6 restore 980 * if not in supervisor mode 981 */ 982 983 EXCEPTION_STORE_GPR2 984 EXCEPTION_STORE_GPR3 985 EXCEPTION_STORE_GPR4 986 EXCEPTION_STORE_GPR5 987 988 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA 989 990immediate_translation: 991 CLEAR_GPR(r6) 992 993 l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN size (4Kb) 994 995 l.mfspr r6, r0, SPR_DMMUCFGR 996 l.andi r6, r6, SPR_DMMUCFGR_NTS 997 l.srli r6, r6, SPR_DMMUCFGR_NTS_OFF 998 l.ori r5, r0, 0x1 999 l.sll r5, r5, r6 // r5 = number DMMU sets 1000 l.addi r6, r5, -1 // r6 = nsets mask 1001 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK 1002 1003 l.or r6,r6,r4 // r6 <- r4 1004 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff 1005 l.movhi r5,hi(DTLB_MR_MASK) // r5 <- ffff:0000.x000 1006 l.ori r5,r5,lo(DTLB_MR_MASK) // r5 <- ffff:1111.x001 - apply DTLB_MR_MASK 1007 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have DTLBMR entry 1008 l.mtspr r2,r5,SPR_DTLBMR_BASE(0) // set DTLBMR 1009 1010 /* set up DTLB with no translation for EA <= 0xbfffffff */ 1011 LOAD_SYMBOL_2_GPR(r6,0xbfffffff) 1012 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xbfffffff >= EA) 1013 l.bf 1f // goto out 1014 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1) 1015 1016 tophys(r3,r4) // r3 <- PA 10171: 1018 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff 1019 l.movhi r5,hi(DTLB_TR_MASK) // r5 <- ffff:0000.x000 1020 l.ori r5,r5,lo(DTLB_TR_MASK) // r5 <- ffff:1111.x330 - apply DTLB_MR_MASK 1021 l.and r5,r5,r3 // r5 <- PPN :PPN .x330 - we have DTLBTR entry 1022 l.mtspr r2,r5,SPR_DTLBTR_BASE(0) // set DTLBTR 1023 1024 EXCEPTION_LOAD_GPR6 1025 EXCEPTION_LOAD_GPR5 1026 EXCEPTION_LOAD_GPR4 1027 EXCEPTION_LOAD_GPR3 1028 EXCEPTION_LOAD_GPR2 1029 1030 l.rfe // SR <- ESR, PC <- EPC 1031 1032exit_with_no_dtranslation: 1033 /* EA out of memory or not in supervisor mode */ 1034 EXCEPTION_LOAD_GPR6 1035 EXCEPTION_LOAD_GPR4 1036 l.j _dispatch_bus_fault 1037 1038/* ---[ boot itlb miss handler ]----------------------------------------- */ 1039 1040boot_itlb_miss_handler: 1041 1042/* mask for ITLB_MR register: - sets V (valid) bit, 1043 * - sets bits belonging to VPN (15-12) 1044 */ 1045#define ITLB_MR_MASK 0xfffff001 1046 1047/* mask for ITLB_TR register: - sets A (access) bit, 1048 * - sets SXE (superuser execute) bit 1049 * - sets bits belonging to VPN (15-12) 1050 */ 1051#define ITLB_TR_MASK 0xfffff050 1052 1053/* 1054#define VPN_MASK 0xffffe000 1055#define PPN_MASK 0xffffe000 1056*/ 1057 1058 1059 1060 EXCEPTION_STORE_GPR2 1061 EXCEPTION_STORE_GPR3 1062 EXCEPTION_STORE_GPR4 1063 EXCEPTION_STORE_GPR5 1064 EXCEPTION_STORE_GPR6 1065 1066#if 0 1067 l.mfspr r6,r0,SPR_ESR_BASE // 1068 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ? 1069 l.sfeqi r6,0 // r6 == 0x1 --> SM 1070 l.bf exit_with_no_itranslation 1071 l.nop 1072#endif 1073 1074 1075 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA 1076 1077earlyearly: 1078 CLEAR_GPR(r6) 1079 1080 l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN size (4Kb) 1081 1082 l.mfspr r6, r0, SPR_IMMUCFGR 1083 l.andi r6, r6, SPR_IMMUCFGR_NTS 1084 l.srli r6, r6, SPR_IMMUCFGR_NTS_OFF 1085 l.ori r5, r0, 0x1 1086 l.sll r5, r5, r6 // r5 = number IMMU sets from IMMUCFGR 1087 l.addi r6, r5, -1 // r6 = nsets mask 1088 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK 1089 1090 l.or r6,r6,r4 // r6 <- r4 1091 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff 1092 l.movhi r5,hi(ITLB_MR_MASK) // r5 <- ffff:0000.x000 1093 l.ori r5,r5,lo(ITLB_MR_MASK) // r5 <- ffff:1111.x001 - apply ITLB_MR_MASK 1094 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have ITLBMR entry 1095 l.mtspr r2,r5,SPR_ITLBMR_BASE(0) // set ITLBMR 1096 1097 /* 1098 * set up ITLB with no translation for EA <= 0x0fffffff 1099 * 1100 * we need this for head.S mapping (EA = PA). if we move all functions 1101 * which run with mmu enabled into entry.S, we might be able to eliminate this. 1102 * 1103 */ 1104 LOAD_SYMBOL_2_GPR(r6,0x0fffffff) 1105 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xb0ffffff >= EA) 1106 l.bf 1f // goto out 1107 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1) 1108 1109 tophys(r3,r4) // r3 <- PA 11101: 1111 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff 1112 l.movhi r5,hi(ITLB_TR_MASK) // r5 <- ffff:0000.x000 1113 l.ori r5,r5,lo(ITLB_TR_MASK) // r5 <- ffff:1111.x050 - apply ITLB_MR_MASK 1114 l.and r5,r5,r3 // r5 <- PPN :PPN .x050 - we have ITLBTR entry 1115 l.mtspr r2,r5,SPR_ITLBTR_BASE(0) // set ITLBTR 1116 1117 EXCEPTION_LOAD_GPR6 1118 EXCEPTION_LOAD_GPR5 1119 EXCEPTION_LOAD_GPR4 1120 EXCEPTION_LOAD_GPR3 1121 EXCEPTION_LOAD_GPR2 1122 1123 l.rfe // SR <- ESR, PC <- EPC 1124 1125exit_with_no_itranslation: 1126 EXCEPTION_LOAD_GPR4 1127 EXCEPTION_LOAD_GPR6 1128 l.j _dispatch_bus_fault 1129 l.nop 1130 1131/* ====================================================================== */ 1132/* 1133 * Stuff below here shouldn't go into .head section... maybe this stuff 1134 * can be moved to entry.S ??? 1135 */ 1136 1137/* ==============================================[ DTLB miss handler ]=== */ 1138 1139/* 1140 * Comments: 1141 * Exception handlers are entered with MMU off so the following handler 1142 * needs to use physical addressing 1143 * 1144 */ 1145 1146 .text 1147ENTRY(dtlb_miss_handler) 1148 EXCEPTION_STORE_GPR2 1149 EXCEPTION_STORE_GPR3 1150 EXCEPTION_STORE_GPR4 1151 /* 1152 * get EA of the miss 1153 */ 1154 l.mfspr r2,r0,SPR_EEAR_BASE 1155 /* 1156 * pmd = (pmd_t *)(current_pgd + pgd_index(daddr)); 1157 */ 1158 GET_CURRENT_PGD(r3,r4) // r3 is current_pgd, r4 is temp 1159 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2) 1160 l.slli r4,r4,0x2 // to get address << 2 1161 l.add r3,r4,r3 // r4 is pgd_index(daddr) 1162 /* 1163 * if (pmd_none(*pmd)) 1164 * goto pmd_none: 1165 */ 1166 tophys (r4,r3) 1167 l.lwz r3,0x0(r4) // get *pmd value 1168 l.sfne r3,r0 1169 l.bnf d_pmd_none 1170 l.addi r3,r0,0xffffe000 // PAGE_MASK 1171 1172d_pmd_good: 1173 /* 1174 * pte = *pte_offset(pmd, daddr); 1175 */ 1176 l.lwz r4,0x0(r4) // get **pmd value 1177 l.and r4,r4,r3 // & PAGE_MASK 1178 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR 1179 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1 1180 l.slli r3,r3,0x2 // to get address << 2 1181 l.add r3,r3,r4 1182 l.lwz r3,0x0(r3) // this is pte at last 1183 /* 1184 * if (!pte_present(pte)) 1185 */ 1186 l.andi r4,r3,0x1 1187 l.sfne r4,r0 // is pte present 1188 l.bnf d_pte_not_present 1189 l.addi r4,r0,0xffffe3fa // PAGE_MASK | DTLB_UP_CONVERT_MASK 1190 /* 1191 * fill DTLB TR register 1192 */ 1193 l.and r4,r3,r4 // apply the mask 1194 // Determine number of DMMU sets 1195 l.mfspr r2, r0, SPR_DMMUCFGR 1196 l.andi r2, r2, SPR_DMMUCFGR_NTS 1197 l.srli r2, r2, SPR_DMMUCFGR_NTS_OFF 1198 l.ori r3, r0, 0x1 1199 l.sll r3, r3, r2 // r3 = number DMMU sets DMMUCFGR 1200 l.addi r2, r3, -1 // r2 = nsets mask 1201 l.mfspr r3, r0, SPR_EEAR_BASE 1202 l.srli r3, r3, 0xd // >> PAGE_SHIFT 1203 l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1) 1204 //NUM_TLB_ENTRIES 1205 l.mtspr r2,r4,SPR_DTLBTR_BASE(0) 1206 /* 1207 * fill DTLB MR register 1208 */ 1209 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */ 1210 l.ori r4,r3,0x1 // set hardware valid bit: DTBL_MR entry 1211 l.mtspr r2,r4,SPR_DTLBMR_BASE(0) 1212 1213 EXCEPTION_LOAD_GPR2 1214 EXCEPTION_LOAD_GPR3 1215 EXCEPTION_LOAD_GPR4 1216 l.rfe 1217d_pmd_none: 1218d_pte_not_present: 1219 EXCEPTION_LOAD_GPR2 1220 EXCEPTION_LOAD_GPR3 1221 EXCEPTION_LOAD_GPR4 1222 EXCEPTION_HANDLE(_dtlb_miss_page_fault_handler) 1223 1224/* ==============================================[ ITLB miss handler ]=== */ 1225ENTRY(itlb_miss_handler) 1226 EXCEPTION_STORE_GPR2 1227 EXCEPTION_STORE_GPR3 1228 EXCEPTION_STORE_GPR4 1229 /* 1230 * get EA of the miss 1231 */ 1232 l.mfspr r2,r0,SPR_EEAR_BASE 1233 1234 /* 1235 * pmd = (pmd_t *)(current_pgd + pgd_index(daddr)); 1236 * 1237 */ 1238 GET_CURRENT_PGD(r3,r4) // r3 is current_pgd, r5 is temp 1239 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2) 1240 l.slli r4,r4,0x2 // to get address << 2 1241 l.add r3,r4,r3 // r4 is pgd_index(daddr) 1242 /* 1243 * if (pmd_none(*pmd)) 1244 * goto pmd_none: 1245 */ 1246 tophys (r4,r3) 1247 l.lwz r3,0x0(r4) // get *pmd value 1248 l.sfne r3,r0 1249 l.bnf i_pmd_none 1250 l.addi r3,r0,0xffffe000 // PAGE_MASK 1251 1252i_pmd_good: 1253 /* 1254 * pte = *pte_offset(pmd, iaddr); 1255 * 1256 */ 1257 l.lwz r4,0x0(r4) // get **pmd value 1258 l.and r4,r4,r3 // & PAGE_MASK 1259 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR 1260 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1 1261 l.slli r3,r3,0x2 // to get address << 2 1262 l.add r3,r3,r4 1263 l.lwz r3,0x0(r3) // this is pte at last 1264 /* 1265 * if (!pte_present(pte)) 1266 * 1267 */ 1268 l.andi r4,r3,0x1 1269 l.sfne r4,r0 // is pte present 1270 l.bnf i_pte_not_present 1271 l.addi r4,r0,0xffffe03a // PAGE_MASK | ITLB_UP_CONVERT_MASK 1272 /* 1273 * fill ITLB TR register 1274 */ 1275 l.and r4,r3,r4 // apply the mask 1276 l.andi r3,r3,0x7c0 // _PAGE_EXEC | _PAGE_SRE | _PAGE_SWE | _PAGE_URE | _PAGE_UWE 1277 l.sfeq r3,r0 1278 l.bf itlb_tr_fill //_workaround 1279 // Determine number of IMMU sets 1280 l.mfspr r2, r0, SPR_IMMUCFGR 1281 l.andi r2, r2, SPR_IMMUCFGR_NTS 1282 l.srli r2, r2, SPR_IMMUCFGR_NTS_OFF 1283 l.ori r3, r0, 0x1 1284 l.sll r3, r3, r2 // r3 = number IMMU sets IMMUCFGR 1285 l.addi r2, r3, -1 // r2 = nsets mask 1286 l.mfspr r3, r0, SPR_EEAR_BASE 1287 l.srli r3, r3, 0xd // >> PAGE_SHIFT 1288 l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1) 1289 1290/* 1291 * __PHX__ :: fixme 1292 * we should not just blindly set executable flags, 1293 * but it does help with ping. the clean way would be to find out 1294 * (and fix it) why stack doesn't have execution permissions 1295 */ 1296 1297itlb_tr_fill_workaround: 1298 l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE) 1299itlb_tr_fill: 1300 l.mtspr r2,r4,SPR_ITLBTR_BASE(0) 1301 /* 1302 * fill DTLB MR register 1303 */ 1304 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */ 1305 l.ori r4,r3,0x1 // set hardware valid bit: ITBL_MR entry 1306 l.mtspr r2,r4,SPR_ITLBMR_BASE(0) 1307 1308 EXCEPTION_LOAD_GPR2 1309 EXCEPTION_LOAD_GPR3 1310 EXCEPTION_LOAD_GPR4 1311 l.rfe 1312 1313i_pmd_none: 1314i_pte_not_present: 1315 EXCEPTION_LOAD_GPR2 1316 EXCEPTION_LOAD_GPR3 1317 EXCEPTION_LOAD_GPR4 1318 EXCEPTION_HANDLE(_itlb_miss_page_fault_handler) 1319 1320/* ==============================================[ boot tlb handlers ]=== */ 1321 1322 1323/* =================================================[ debugging aids ]=== */ 1324 1325 .align 64 1326_immu_trampoline: 1327 .space 64 1328_immu_trampoline_top: 1329 1330#define TRAMP_SLOT_0 (0x0) 1331#define TRAMP_SLOT_1 (0x4) 1332#define TRAMP_SLOT_2 (0x8) 1333#define TRAMP_SLOT_3 (0xc) 1334#define TRAMP_SLOT_4 (0x10) 1335#define TRAMP_SLOT_5 (0x14) 1336#define TRAMP_FRAME_SIZE (0x18) 1337 1338ENTRY(_immu_trampoline_workaround) 1339 // r2 EEA 1340 // r6 is physical EEA 1341 tophys(r6,r2) 1342 1343 LOAD_SYMBOL_2_GPR(r5,_immu_trampoline) 1344 tophys (r3,r5) // r3 is trampoline (physical) 1345 1346 LOAD_SYMBOL_2_GPR(r4,0x15000000) 1347 l.sw TRAMP_SLOT_0(r3),r4 1348 l.sw TRAMP_SLOT_1(r3),r4 1349 l.sw TRAMP_SLOT_4(r3),r4 1350 l.sw TRAMP_SLOT_5(r3),r4 1351 1352 // EPC = EEA - 0x4 1353 l.lwz r4,0x0(r6) // load op @ EEA + 0x0 (fc address) 1354 l.sw TRAMP_SLOT_3(r3),r4 // store it to _immu_trampoline_data 1355 l.lwz r4,-0x4(r6) // load op @ EEA - 0x4 (f8 address) 1356 l.sw TRAMP_SLOT_2(r3),r4 // store it to _immu_trampoline_data 1357 1358 l.srli r5,r4,26 // check opcode for write access 1359 l.sfeqi r5,0 // l.j 1360 l.bf 0f 1361 l.sfeqi r5,0x11 // l.jr 1362 l.bf 1f 1363 l.sfeqi r5,1 // l.jal 1364 l.bf 2f 1365 l.sfeqi r5,0x12 // l.jalr 1366 l.bf 3f 1367 l.sfeqi r5,3 // l.bnf 1368 l.bf 4f 1369 l.sfeqi r5,4 // l.bf 1370 l.bf 5f 137199: 1372 l.nop 1373 l.j 99b // should never happen 1374 l.nop 1 1375 1376 // r2 is EEA 1377 // r3 is trampoline address (physical) 1378 // r4 is instruction 1379 // r6 is physical(EEA) 1380 // 1381 // r5 1382 13832: // l.jal 1384 1385 /* 19 20 aa aa l.movhi r9,0xaaaa 1386 * a9 29 bb bb l.ori r9,0xbbbb 1387 * 1388 * where 0xaaaabbbb is EEA + 0x4 shifted right 2 1389 */ 1390 1391 l.addi r6,r2,0x4 // this is 0xaaaabbbb 1392 1393 // l.movhi r9,0xaaaa 1394 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9 1395 l.sh (TRAMP_SLOT_0+0x0)(r3),r5 1396 l.srli r5,r6,16 1397 l.sh (TRAMP_SLOT_0+0x2)(r3),r5 1398 1399 // l.ori r9,0xbbbb 1400 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9 1401 l.sh (TRAMP_SLOT_1+0x0)(r3),r5 1402 l.andi r5,r6,0xffff 1403 l.sh (TRAMP_SLOT_1+0x2)(r3),r5 1404 1405 /* falthrough, need to set up new jump offset */ 1406 1407 14080: // l.j 1409 l.slli r6,r4,6 // original offset shifted left 6 - 2 1410// l.srli r6,r6,6 // original offset shifted right 2 1411 1412 l.slli r4,r2,4 // old jump position: EEA shifted left 4 1413// l.srli r4,r4,6 // old jump position: shifted right 2 1414 1415 l.addi r5,r3,0xc // new jump position (physical) 1416 l.slli r5,r5,4 // new jump position: shifted left 4 1417 1418 // calculate new jump offset 1419 // new_off = old_off + (old_jump - new_jump) 1420 1421 l.sub r5,r4,r5 // old_jump - new_jump 1422 l.add r5,r6,r5 // orig_off + (old_jump - new_jump) 1423 l.srli r5,r5,6 // new offset shifted right 2 1424 1425 // r5 is new jump offset 1426 // l.j has opcode 0x0... 1427 l.sw TRAMP_SLOT_2(r3),r5 // write it back 1428 1429 l.j trampoline_out 1430 l.nop 1431 1432/* ----------------------------- */ 1433 14343: // l.jalr 1435 1436 /* 19 20 aa aa l.movhi r9,0xaaaa 1437 * a9 29 bb bb l.ori r9,0xbbbb 1438 * 1439 * where 0xaaaabbbb is EEA + 0x4 shifted right 2 1440 */ 1441 1442 l.addi r6,r2,0x4 // this is 0xaaaabbbb 1443 1444 // l.movhi r9,0xaaaa 1445 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9 1446 l.sh (TRAMP_SLOT_0+0x0)(r3),r5 1447 l.srli r5,r6,16 1448 l.sh (TRAMP_SLOT_0+0x2)(r3),r5 1449 1450 // l.ori r9,0xbbbb 1451 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9 1452 l.sh (TRAMP_SLOT_1+0x0)(r3),r5 1453 l.andi r5,r6,0xffff 1454 l.sh (TRAMP_SLOT_1+0x2)(r3),r5 1455 1456 l.lhz r5,(TRAMP_SLOT_2+0x0)(r3) // load hi part of jump instruction 1457 l.andi r5,r5,0x3ff // clear out opcode part 1458 l.ori r5,r5,0x4400 // opcode changed from l.jalr -> l.jr 1459 l.sh (TRAMP_SLOT_2+0x0)(r3),r5 // write it back 1460 1461 /* falthrough */ 1462 14631: // l.jr 1464 l.j trampoline_out 1465 l.nop 1466 1467/* ----------------------------- */ 1468 14694: // l.bnf 14705: // l.bf 1471 l.slli r6,r4,6 // original offset shifted left 6 - 2 1472// l.srli r6,r6,6 // original offset shifted right 2 1473 1474 l.slli r4,r2,4 // old jump position: EEA shifted left 4 1475// l.srli r4,r4,6 // old jump position: shifted right 2 1476 1477 l.addi r5,r3,0xc // new jump position (physical) 1478 l.slli r5,r5,4 // new jump position: shifted left 4 1479 1480 // calculate new jump offset 1481 // new_off = old_off + (old_jump - new_jump) 1482 1483 l.add r6,r6,r4 // (orig_off + old_jump) 1484 l.sub r6,r6,r5 // (orig_off + old_jump) - new_jump 1485 l.srli r6,r6,6 // new offset shifted right 2 1486 1487 // r6 is new jump offset 1488 l.lwz r4,(TRAMP_SLOT_2+0x0)(r3) // load jump instruction 1489 l.srli r4,r4,16 1490 l.andi r4,r4,0xfc00 // get opcode part 1491 l.slli r4,r4,16 1492 l.or r6,r4,r6 // l.b(n)f new offset 1493 l.sw TRAMP_SLOT_2(r3),r6 // write it back 1494 1495 /* we need to add l.j to EEA + 0x8 */ 1496 tophys (r4,r2) // may not be needed (due to shifts down_ 1497 l.addi r4,r4,(0x8 - 0x8) // jump target = r2 + 0x8 (compensate for 0x8) 1498 // jump position = r5 + 0x8 (0x8 compensated) 1499 l.sub r4,r4,r5 // jump offset = target - new_position + 0x8 1500 1501 l.slli r4,r4,4 // the amount of info in imediate of jump 1502 l.srli r4,r4,6 // jump instruction with offset 1503 l.sw TRAMP_SLOT_4(r3),r4 // write it to 4th slot 1504 1505 /* fallthrough */ 1506 1507trampoline_out: 1508 // set up new EPC to point to our trampoline code 1509 LOAD_SYMBOL_2_GPR(r5,_immu_trampoline) 1510 l.mtspr r0,r5,SPR_EPCR_BASE 1511 1512 // immu_trampoline is (4x) CACHE_LINE aligned 1513 // and only 6 instructions long, 1514 // so we need to invalidate only 2 lines 1515 1516 /* Establish cache block size 1517 If BS=0, 16; 1518 If BS=1, 32; 1519 r14 contain block size 1520 */ 1521 l.mfspr r21,r0,SPR_ICCFGR 1522 l.andi r21,r21,SPR_ICCFGR_CBS 1523 l.srli r21,r21,7 1524 l.ori r23,r0,16 1525 l.sll r14,r23,r21 1526 1527 l.mtspr r0,r5,SPR_ICBIR 1528 l.add r5,r5,r14 1529 l.mtspr r0,r5,SPR_ICBIR 1530 1531 l.jr r9 1532 l.nop 1533 1534 1535/* 1536 * DSCR: prints a string referenced by r3. 1537 * 1538 * PRMS: r3 - address of the first character of null 1539 * terminated string to be printed 1540 * 1541 * PREQ: UART at UART_BASE_ADD has to be initialized 1542 * 1543 * POST: caller should be aware that r3, r9 are changed 1544 */ 1545ENTRY(_emergency_print) 1546 EMERGENCY_PRINT_STORE_GPR4 1547 EMERGENCY_PRINT_STORE_GPR5 1548 EMERGENCY_PRINT_STORE_GPR6 1549 EMERGENCY_PRINT_STORE_GPR7 15502: 1551 l.lbz r7,0(r3) 1552 l.sfeq r7,r0 1553 l.bf 9f 1554 l.nop 1555 1556// putc: 1557 l.movhi r4,hi(UART_BASE_ADD) 1558 1559 l.addi r6,r0,0x20 15601: l.lbz r5,5(r4) 1561 l.andi r5,r5,0x20 1562 l.sfeq r5,r6 1563 l.bnf 1b 1564 l.nop 1565 1566 l.sb 0(r4),r7 1567 1568 l.addi r6,r0,0x60 15691: l.lbz r5,5(r4) 1570 l.andi r5,r5,0x60 1571 l.sfeq r5,r6 1572 l.bnf 1b 1573 l.nop 1574 1575 /* next character */ 1576 l.j 2b 1577 l.addi r3,r3,0x1 1578 15799: 1580 EMERGENCY_PRINT_LOAD_GPR7 1581 EMERGENCY_PRINT_LOAD_GPR6 1582 EMERGENCY_PRINT_LOAD_GPR5 1583 EMERGENCY_PRINT_LOAD_GPR4 1584 l.jr r9 1585 l.nop 1586 1587ENTRY(_emergency_print_nr) 1588 EMERGENCY_PRINT_STORE_GPR4 1589 EMERGENCY_PRINT_STORE_GPR5 1590 EMERGENCY_PRINT_STORE_GPR6 1591 EMERGENCY_PRINT_STORE_GPR7 1592 EMERGENCY_PRINT_STORE_GPR8 1593 1594 l.addi r8,r0,32 // shift register 1595 15961: /* remove leading zeros */ 1597 l.addi r8,r8,-0x4 1598 l.srl r7,r3,r8 1599 l.andi r7,r7,0xf 1600 1601 /* don't skip the last zero if number == 0x0 */ 1602 l.sfeqi r8,0x4 1603 l.bf 2f 1604 l.nop 1605 1606 l.sfeq r7,r0 1607 l.bf 1b 1608 l.nop 1609 16102: 1611 l.srl r7,r3,r8 1612 1613 l.andi r7,r7,0xf 1614 l.sflts r8,r0 1615 l.bf 9f 1616 1617 l.sfgtui r7,0x9 1618 l.bnf 8f 1619 l.nop 1620 l.addi r7,r7,0x27 1621 16228: 1623 l.addi r7,r7,0x30 1624// putc: 1625 l.movhi r4,hi(UART_BASE_ADD) 1626 1627 l.addi r6,r0,0x20 16281: l.lbz r5,5(r4) 1629 l.andi r5,r5,0x20 1630 l.sfeq r5,r6 1631 l.bnf 1b 1632 l.nop 1633 1634 l.sb 0(r4),r7 1635 1636 l.addi r6,r0,0x60 16371: l.lbz r5,5(r4) 1638 l.andi r5,r5,0x60 1639 l.sfeq r5,r6 1640 l.bnf 1b 1641 l.nop 1642 1643 /* next character */ 1644 l.j 2b 1645 l.addi r8,r8,-0x4 1646 16479: 1648 EMERGENCY_PRINT_LOAD_GPR8 1649 EMERGENCY_PRINT_LOAD_GPR7 1650 EMERGENCY_PRINT_LOAD_GPR6 1651 EMERGENCY_PRINT_LOAD_GPR5 1652 EMERGENCY_PRINT_LOAD_GPR4 1653 l.jr r9 1654 l.nop 1655 1656 1657/* 1658 * This should be used for debugging only. 1659 * It messes up the Linux early serial output 1660 * somehow, so use it sparingly and essentially 1661 * only if you need to debug something that goes wrong 1662 * before Linux gets the early serial going. 1663 * 1664 * Furthermore, you'll have to make sure you set the 1665 * UART_DEVISOR correctly according to the system 1666 * clock rate. 1667 * 1668 * 1669 */ 1670 1671 1672 1673#define SYS_CLK 20000000 1674//#define SYS_CLK 1843200 1675#define OR32_CONSOLE_BAUD 115200 1676#define UART_DIVISOR SYS_CLK/(16*OR32_CONSOLE_BAUD) 1677 1678ENTRY(_early_uart_init) 1679 l.movhi r3,hi(UART_BASE_ADD) 1680 1681 l.addi r4,r0,0x7 1682 l.sb 0x2(r3),r4 1683 1684 l.addi r4,r0,0x0 1685 l.sb 0x1(r3),r4 1686 1687 l.addi r4,r0,0x3 1688 l.sb 0x3(r3),r4 1689 1690 l.lbz r5,3(r3) 1691 l.ori r4,r5,0x80 1692 l.sb 0x3(r3),r4 1693 l.addi r4,r0,((UART_DIVISOR>>8) & 0x000000ff) 1694 l.sb UART_DLM(r3),r4 1695 l.addi r4,r0,((UART_DIVISOR) & 0x000000ff) 1696 l.sb UART_DLL(r3),r4 1697 l.sb 0x3(r3),r5 1698 1699 l.jr r9 1700 l.nop 1701 1702 .align 0x1000 1703 .global _secondary_evbar 1704_secondary_evbar: 1705 1706 .space 0x800 1707 /* Just disable interrupts and Return */ 1708 l.ori r3,r0,SPR_SR_SM 1709 l.mtspr r0,r3,SPR_ESR_BASE 1710 l.rfe 1711 1712 1713 .section .rodata 1714_string_unhandled_exception: 1715 .string "\n\rRunarunaround: Unhandled exception 0x\0" 1716 1717_string_epc_prefix: 1718 .string ": EPC=0x\0" 1719 1720_string_nl: 1721 .string "\n\r\0" 1722 1723 1724/* ========================================[ page aligned structures ]=== */ 1725 1726/* 1727 * .data section should be page aligned 1728 * (look into arch/or32/kernel/vmlinux.lds) 1729 */ 1730 .section .data,"aw" 1731 .align 8192 1732 .global empty_zero_page 1733empty_zero_page: 1734 .space 8192 1735 1736 .global swapper_pg_dir 1737swapper_pg_dir: 1738 .space 8192 1739 1740 .global _unhandled_stack 1741_unhandled_stack: 1742 .space 8192 1743_unhandled_stack_top: 1744 1745/* ============================================================[ EOF ]=== */ 1746