1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * OpenRISC entry.S 4 * 5 * Linux architectural port borrowing liberally from similar works of 6 * others. All original copyrights apply as per the original source 7 * declaration. 8 * 9 * Modifications for the OpenRISC architecture: 10 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com> 11 * Copyright (C) 2005 Gyorgy Jeney <nog@bsemi.com> 12 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se> 13 */ 14 15#include <linux/linkage.h> 16#include <linux/pgtable.h> 17 18#include <asm/processor.h> 19#include <asm/unistd.h> 20#include <asm/thread_info.h> 21#include <asm/errno.h> 22#include <asm/spr_defs.h> 23#include <asm/page.h> 24#include <asm/mmu.h> 25#include <asm/asm-offsets.h> 26 27#define DISABLE_INTERRUPTS(t1,t2) \ 28 l.mfspr t2,r0,SPR_SR ;\ 29 l.movhi t1,hi(~(SPR_SR_IEE|SPR_SR_TEE)) ;\ 30 l.ori t1,t1,lo(~(SPR_SR_IEE|SPR_SR_TEE)) ;\ 31 l.and t2,t2,t1 ;\ 32 l.mtspr r0,t2,SPR_SR 33 34#define ENABLE_INTERRUPTS(t1) \ 35 l.mfspr t1,r0,SPR_SR ;\ 36 l.ori t1,t1,lo(SPR_SR_IEE|SPR_SR_TEE) ;\ 37 l.mtspr r0,t1,SPR_SR 38 39/* =========================================================[ macros ]=== */ 40 41#ifdef CONFIG_TRACE_IRQFLAGS 42/* 43 * Trace irq on/off creating a stack frame. 44 */ 45#define TRACE_IRQS_OP(trace_op) \ 46 l.sw -8(r1),r2 /* store frame pointer */ ;\ 47 l.sw -4(r1),r9 /* store return address */ ;\ 48 l.addi r2,r1,0 /* move sp to fp */ ;\ 49 l.jal trace_op ;\ 50 l.addi r1,r1,-8 ;\ 51 l.ori r1,r2,0 /* restore sp */ ;\ 52 l.lwz r9,-4(r1) /* restore return address */ ;\ 53 l.lwz r2,-8(r1) /* restore fp */ ;\ 54/* 55 * Trace irq on/off and save registers we need that would otherwise be 56 * clobbered. 57 */ 58#define TRACE_IRQS_SAVE(t1,trace_op) \ 59 l.sw -12(r1),t1 /* save extra reg */ ;\ 60 l.sw -8(r1),r2 /* store frame pointer */ ;\ 61 l.sw -4(r1),r9 /* store return address */ ;\ 62 l.addi r2,r1,0 /* move sp to fp */ ;\ 63 l.jal trace_op ;\ 64 l.addi r1,r1,-12 ;\ 65 l.ori r1,r2,0 /* restore sp */ ;\ 66 l.lwz r9,-4(r1) /* restore return address */ ;\ 67 l.lwz r2,-8(r1) /* restore fp */ ;\ 68 l.lwz t1,-12(r1) /* restore extra reg */ 69 70#define TRACE_IRQS_OFF TRACE_IRQS_OP(trace_hardirqs_off) 71#define TRACE_IRQS_ON TRACE_IRQS_OP(trace_hardirqs_on) 72#define TRACE_IRQS_ON_SYSCALL \ 73 TRACE_IRQS_SAVE(r10,trace_hardirqs_on) ;\ 74 l.lwz r3,PT_GPR3(r1) ;\ 75 l.lwz r4,PT_GPR4(r1) ;\ 76 l.lwz r5,PT_GPR5(r1) ;\ 77 l.lwz r6,PT_GPR6(r1) ;\ 78 l.lwz r7,PT_GPR7(r1) ;\ 79 l.lwz r8,PT_GPR8(r1) ;\ 80 l.lwz r11,PT_GPR11(r1) 81#define TRACE_IRQS_OFF_ENTRY \ 82 l.lwz r5,PT_SR(r1) ;\ 83 l.andi r3,r5,(SPR_SR_IEE|SPR_SR_TEE) ;\ 84 l.sfeq r5,r0 /* skip trace if irqs were already off */;\ 85 l.bf 1f ;\ 86 l.nop ;\ 87 TRACE_IRQS_SAVE(r4,trace_hardirqs_off) ;\ 881: 89#else 90#define TRACE_IRQS_OFF 91#define TRACE_IRQS_ON 92#define TRACE_IRQS_OFF_ENTRY 93#define TRACE_IRQS_ON_SYSCALL 94#endif 95 96/* 97 * We need to disable interrupts at beginning of RESTORE_ALL 98 * since interrupt might come in after we've loaded EPC return address 99 * and overwrite EPC with address somewhere in RESTORE_ALL 100 * which is of course wrong! 101 */ 102 103#define RESTORE_ALL \ 104 DISABLE_INTERRUPTS(r3,r4) ;\ 105 l.lwz r3,PT_PC(r1) ;\ 106 l.mtspr r0,r3,SPR_EPCR_BASE ;\ 107 l.lwz r3,PT_SR(r1) ;\ 108 l.mtspr r0,r3,SPR_ESR_BASE ;\ 109 l.lwz r3,PT_FPCSR(r1) ;\ 110 l.mtspr r0,r3,SPR_FPCSR ;\ 111 l.lwz r2,PT_GPR2(r1) ;\ 112 l.lwz r3,PT_GPR3(r1) ;\ 113 l.lwz r4,PT_GPR4(r1) ;\ 114 l.lwz r5,PT_GPR5(r1) ;\ 115 l.lwz r6,PT_GPR6(r1) ;\ 116 l.lwz r7,PT_GPR7(r1) ;\ 117 l.lwz r8,PT_GPR8(r1) ;\ 118 l.lwz r9,PT_GPR9(r1) ;\ 119 l.lwz r10,PT_GPR10(r1) ;\ 120 l.lwz r11,PT_GPR11(r1) ;\ 121 l.lwz r12,PT_GPR12(r1) ;\ 122 l.lwz r13,PT_GPR13(r1) ;\ 123 l.lwz r14,PT_GPR14(r1) ;\ 124 l.lwz r15,PT_GPR15(r1) ;\ 125 l.lwz r16,PT_GPR16(r1) ;\ 126 l.lwz r17,PT_GPR17(r1) ;\ 127 l.lwz r18,PT_GPR18(r1) ;\ 128 l.lwz r19,PT_GPR19(r1) ;\ 129 l.lwz r20,PT_GPR20(r1) ;\ 130 l.lwz r21,PT_GPR21(r1) ;\ 131 l.lwz r22,PT_GPR22(r1) ;\ 132 l.lwz r23,PT_GPR23(r1) ;\ 133 l.lwz r24,PT_GPR24(r1) ;\ 134 l.lwz r25,PT_GPR25(r1) ;\ 135 l.lwz r26,PT_GPR26(r1) ;\ 136 l.lwz r27,PT_GPR27(r1) ;\ 137 l.lwz r28,PT_GPR28(r1) ;\ 138 l.lwz r29,PT_GPR29(r1) ;\ 139 l.lwz r30,PT_GPR30(r1) ;\ 140 l.lwz r31,PT_GPR31(r1) ;\ 141 l.lwz r1,PT_SP(r1) ;\ 142 l.rfe 143 144 145#define EXCEPTION_ENTRY(handler) \ 146 .global handler ;\ 147handler: ;\ 148 /* r1, EPCR, ESR a already saved */ ;\ 149 l.sw PT_GPR2(r1),r2 ;\ 150 l.sw PT_GPR3(r1),r3 ;\ 151 /* r4 already save */ ;\ 152 l.sw PT_GPR5(r1),r5 ;\ 153 l.sw PT_GPR6(r1),r6 ;\ 154 l.sw PT_GPR7(r1),r7 ;\ 155 l.sw PT_GPR8(r1),r8 ;\ 156 l.sw PT_GPR9(r1),r9 ;\ 157 /* r10 already saved */ ;\ 158 l.sw PT_GPR11(r1),r11 ;\ 159 /* r12 already saved */ ;\ 160 l.sw PT_GPR13(r1),r13 ;\ 161 l.sw PT_GPR14(r1),r14 ;\ 162 l.sw PT_GPR15(r1),r15 ;\ 163 l.sw PT_GPR16(r1),r16 ;\ 164 l.sw PT_GPR17(r1),r17 ;\ 165 l.sw PT_GPR18(r1),r18 ;\ 166 l.sw PT_GPR19(r1),r19 ;\ 167 l.sw PT_GPR20(r1),r20 ;\ 168 l.sw PT_GPR21(r1),r21 ;\ 169 l.sw PT_GPR22(r1),r22 ;\ 170 l.sw PT_GPR23(r1),r23 ;\ 171 l.sw PT_GPR24(r1),r24 ;\ 172 l.sw PT_GPR25(r1),r25 ;\ 173 l.sw PT_GPR26(r1),r26 ;\ 174 l.sw PT_GPR27(r1),r27 ;\ 175 l.sw PT_GPR28(r1),r28 ;\ 176 l.sw PT_GPR29(r1),r29 ;\ 177 /* r30 already save */ ;\ 178 l.sw PT_GPR31(r1),r31 ;\ 179 TRACE_IRQS_OFF_ENTRY ;\ 180 l.mfspr r30,r0,SPR_FPCSR ;\ 181 l.sw PT_FPCSR(r1),r30 ;\ 182 /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\ 183 l.addi r30,r0,-1 ;\ 184 l.sw PT_ORIG_GPR11(r1),r30 185 186#define UNHANDLED_EXCEPTION(handler,vector) \ 187 .global handler ;\ 188handler: ;\ 189 /* r1, EPCR, ESR already saved */ ;\ 190 l.sw PT_GPR2(r1),r2 ;\ 191 l.sw PT_GPR3(r1),r3 ;\ 192 l.sw PT_GPR5(r1),r5 ;\ 193 l.sw PT_GPR6(r1),r6 ;\ 194 l.sw PT_GPR7(r1),r7 ;\ 195 l.sw PT_GPR8(r1),r8 ;\ 196 l.sw PT_GPR9(r1),r9 ;\ 197 /* r10 already saved */ ;\ 198 l.sw PT_GPR11(r1),r11 ;\ 199 /* r12 already saved */ ;\ 200 l.sw PT_GPR13(r1),r13 ;\ 201 l.sw PT_GPR14(r1),r14 ;\ 202 l.sw PT_GPR15(r1),r15 ;\ 203 l.sw PT_GPR16(r1),r16 ;\ 204 l.sw PT_GPR17(r1),r17 ;\ 205 l.sw PT_GPR18(r1),r18 ;\ 206 l.sw PT_GPR19(r1),r19 ;\ 207 l.sw PT_GPR20(r1),r20 ;\ 208 l.sw PT_GPR21(r1),r21 ;\ 209 l.sw PT_GPR22(r1),r22 ;\ 210 l.sw PT_GPR23(r1),r23 ;\ 211 l.sw PT_GPR24(r1),r24 ;\ 212 l.sw PT_GPR25(r1),r25 ;\ 213 l.sw PT_GPR26(r1),r26 ;\ 214 l.sw PT_GPR27(r1),r27 ;\ 215 l.sw PT_GPR28(r1),r28 ;\ 216 l.sw PT_GPR29(r1),r29 ;\ 217 /* r30 already saved */ ;\ 218 l.sw PT_GPR31(r1),r31 ;\ 219 /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\ 220 l.addi r30,r0,-1 ;\ 221 l.sw PT_ORIG_GPR11(r1),r30 ;\ 222 l.mfspr r30,r0,SPR_FPCSR ;\ 223 l.sw PT_FPCSR(r1),r30 ;\ 224 l.addi r3,r1,0 ;\ 225 /* r4 is exception EA */ ;\ 226 l.addi r5,r0,vector ;\ 227 l.jal unhandled_exception ;\ 228 l.nop ;\ 229 l.j _ret_from_exception ;\ 230 l.nop 231 232/* clobbers 'reg' */ 233#define CLEAR_LWA_FLAG(reg) \ 234 l.movhi reg,hi(lwa_flag) ;\ 235 l.ori reg,reg,lo(lwa_flag) ;\ 236 l.sw 0(reg),r0 237/* 238 * NOTE: one should never assume that SPR_EPC, SPR_ESR, SPR_EEAR 239 * contain the same values as when exception we're handling 240 * occured. in fact they never do. if you need them use 241 * values saved on stack (for SPR_EPC, SPR_ESR) or content 242 * of r4 (for SPR_EEAR). for details look at EXCEPTION_HANDLE() 243 * in 'arch/openrisc/kernel/head.S' 244 */ 245 246/* =====================================================[ exceptions] === */ 247 248/* ---[ 0x100: RESET exception ]----------------------------------------- */ 249 250EXCEPTION_ENTRY(_tng_kernel_start) 251 l.jal _start 252 l.andi r0,r0,0 253 254/* ---[ 0x200: BUS exception ]------------------------------------------- */ 255 256EXCEPTION_ENTRY(_bus_fault_handler) 257 CLEAR_LWA_FLAG(r3) 258 /* r4: EA of fault (set by EXCEPTION_HANDLE) */ 259 l.jal do_bus_fault 260 l.addi r3,r1,0 /* pt_regs */ 261 262 l.j _ret_from_exception 263 l.nop 264 265/* ---[ 0x300: Data Page Fault exception ]------------------------------- */ 266EXCEPTION_ENTRY(_dtlb_miss_page_fault_handler) 267 CLEAR_LWA_FLAG(r3) 268 l.and r5,r5,r0 269 l.j 1f 270 l.nop 271 272EXCEPTION_ENTRY(_data_page_fault_handler) 273 CLEAR_LWA_FLAG(r3) 274 /* set up parameters for do_page_fault */ 275 l.ori r5,r0,0x300 // exception vector 2761: 277 l.addi r3,r1,0 // pt_regs 278 /* r4 set be EXCEPTION_HANDLE */ // effective address of fault 279 280#ifdef CONFIG_OPENRISC_NO_SPR_SR_DSX 281 l.lwz r6,PT_PC(r3) // address of an offending insn 282 l.lwz r6,0(r6) // instruction that caused pf 283 284 l.srli r6,r6,26 // check opcode for jump insn 285 l.sfeqi r6,0 // l.j 286 l.bf 8f 287 l.sfeqi r6,1 // l.jal 288 l.bf 8f 289 l.sfeqi r6,3 // l.bnf 290 l.bf 8f 291 l.sfeqi r6,4 // l.bf 292 l.bf 8f 293 l.sfeqi r6,0x11 // l.jr 294 l.bf 8f 295 l.sfeqi r6,0x12 // l.jalr 296 l.bf 8f 297 l.nop 298 299 l.j 9f 300 l.nop 301 3028: // offending insn is in delay slot 303 l.lwz r6,PT_PC(r3) // address of an offending insn 304 l.addi r6,r6,4 305 l.lwz r6,0(r6) // instruction that caused pf 306 l.srli r6,r6,26 // get opcode 3079: // offending instruction opcode loaded in r6 308 309#else 310 311 l.mfspr r6,r0,SPR_SR // SR 312 l.andi r6,r6,SPR_SR_DSX // check for delay slot exception 313 l.sfne r6,r0 // exception happened in delay slot 314 l.bnf 7f 315 l.lwz r6,PT_PC(r3) // address of an offending insn 316 317 l.addi r6,r6,4 // offending insn is in delay slot 3187: 319 l.lwz r6,0(r6) // instruction that caused pf 320 l.srli r6,r6,26 // check opcode for write access 321#endif 322 323 l.sfgeui r6,0x33 // check opcode for write access 324 l.bnf 1f 325 l.sfleui r6,0x37 326 l.bnf 1f 327 l.ori r6,r0,0x1 // write access 328 l.j 2f 329 l.nop 3301: l.ori r6,r0,0x0 // !write access 3312: 332 333 /* call fault.c handler in openrisc/mm/fault.c */ 334 l.jal do_page_fault 335 l.nop 336 l.j _ret_from_exception 337 l.nop 338 339/* ---[ 0x400: Insn Page Fault exception ]------------------------------- */ 340EXCEPTION_ENTRY(_itlb_miss_page_fault_handler) 341 CLEAR_LWA_FLAG(r3) 342 l.and r5,r5,r0 343 l.j 1f 344 l.nop 345 346EXCEPTION_ENTRY(_insn_page_fault_handler) 347 CLEAR_LWA_FLAG(r3) 348 /* set up parameters for do_page_fault */ 349 l.ori r5,r0,0x400 // exception vector 3501: 351 l.addi r3,r1,0 // pt_regs 352 /* r4 set be EXCEPTION_HANDLE */ // effective address of fault 353 l.ori r6,r0,0x0 // !write access 354 355 /* call fault.c handler in openrisc/mm/fault.c */ 356 l.jal do_page_fault 357 l.nop 358 l.j _ret_from_exception 359 l.nop 360 361 362/* ---[ 0x500: Timer exception ]----------------------------------------- */ 363 364EXCEPTION_ENTRY(_timer_handler) 365 CLEAR_LWA_FLAG(r3) 366 l.jal timer_interrupt 367 l.addi r3,r1,0 /* pt_regs */ 368 369 l.j _ret_from_intr 370 l.nop 371 372/* ---[ 0x600: Alignment exception ]-------------------------------------- */ 373 374EXCEPTION_ENTRY(_alignment_handler) 375 CLEAR_LWA_FLAG(r3) 376 /* r4: EA of fault (set by EXCEPTION_HANDLE) */ 377 l.jal do_unaligned_access 378 l.addi r3,r1,0 /* pt_regs */ 379 380 l.j _ret_from_exception 381 l.nop 382 383#if 0 384EXCEPTION_ENTRY(_alignment_handler) 385// l.mfspr r2,r0,SPR_EEAR_BASE /* Load the effective address */ 386 l.addi r2,r4,0 387// l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */ 388 l.lwz r5,PT_PC(r1) 389 390 l.lwz r3,0(r5) /* Load insn */ 391 l.srli r4,r3,26 /* Shift left to get the insn opcode */ 392 393 l.sfeqi r4,0x00 /* Check if the load/store insn is in delay slot */ 394 l.bf jmp 395 l.sfeqi r4,0x01 396 l.bf jmp 397 l.sfeqi r4,0x03 398 l.bf jmp 399 l.sfeqi r4,0x04 400 l.bf jmp 401 l.sfeqi r4,0x11 402 l.bf jr 403 l.sfeqi r4,0x12 404 l.bf jr 405 l.nop 406 l.j 1f 407 l.addi r5,r5,4 /* Increment PC to get return insn address */ 408 409jmp: 410 l.slli r4,r3,6 /* Get the signed extended jump length */ 411 l.srai r4,r4,4 412 413 l.lwz r3,4(r5) /* Load the real load/store insn */ 414 415 l.add r5,r5,r4 /* Calculate jump target address */ 416 417 l.j 1f 418 l.srli r4,r3,26 /* Shift left to get the insn opcode */ 419 420jr: 421 l.slli r4,r3,9 /* Shift to get the reg nb */ 422 l.andi r4,r4,0x7c 423 424 l.lwz r3,4(r5) /* Load the real load/store insn */ 425 426 l.add r4,r4,r1 /* Load the jump register value from the stack */ 427 l.lwz r5,0(r4) 428 429 l.srli r4,r3,26 /* Shift left to get the insn opcode */ 430 431 4321: 433// l.mtspr r0,r5,SPR_EPCR_BASE 434 l.sw PT_PC(r1),r5 435 436 l.sfeqi r4,0x26 437 l.bf lhs 438 l.sfeqi r4,0x25 439 l.bf lhz 440 l.sfeqi r4,0x22 441 l.bf lws 442 l.sfeqi r4,0x21 443 l.bf lwz 444 l.sfeqi r4,0x37 445 l.bf sh 446 l.sfeqi r4,0x35 447 l.bf sw 448 l.nop 449 4501: l.j 1b /* I don't know what to do */ 451 l.nop 452 453lhs: l.lbs r5,0(r2) 454 l.slli r5,r5,8 455 l.lbz r6,1(r2) 456 l.or r5,r5,r6 457 l.srli r4,r3,19 458 l.andi r4,r4,0x7c 459 l.add r4,r4,r1 460 l.j align_end 461 l.sw 0(r4),r5 462 463lhz: l.lbz r5,0(r2) 464 l.slli r5,r5,8 465 l.lbz r6,1(r2) 466 l.or r5,r5,r6 467 l.srli r4,r3,19 468 l.andi r4,r4,0x7c 469 l.add r4,r4,r1 470 l.j align_end 471 l.sw 0(r4),r5 472 473lws: l.lbs r5,0(r2) 474 l.slli r5,r5,24 475 l.lbz r6,1(r2) 476 l.slli r6,r6,16 477 l.or r5,r5,r6 478 l.lbz r6,2(r2) 479 l.slli r6,r6,8 480 l.or r5,r5,r6 481 l.lbz r6,3(r2) 482 l.or r5,r5,r6 483 l.srli r4,r3,19 484 l.andi r4,r4,0x7c 485 l.add r4,r4,r1 486 l.j align_end 487 l.sw 0(r4),r5 488 489lwz: l.lbz r5,0(r2) 490 l.slli r5,r5,24 491 l.lbz r6,1(r2) 492 l.slli r6,r6,16 493 l.or r5,r5,r6 494 l.lbz r6,2(r2) 495 l.slli r6,r6,8 496 l.or r5,r5,r6 497 l.lbz r6,3(r2) 498 l.or r5,r5,r6 499 l.srli r4,r3,19 500 l.andi r4,r4,0x7c 501 l.add r4,r4,r1 502 l.j align_end 503 l.sw 0(r4),r5 504 505sh: 506 l.srli r4,r3,9 507 l.andi r4,r4,0x7c 508 l.add r4,r4,r1 509 l.lwz r5,0(r4) 510 l.sb 1(r2),r5 511 l.srli r5,r5,8 512 l.j align_end 513 l.sb 0(r2),r5 514 515sw: 516 l.srli r4,r3,9 517 l.andi r4,r4,0x7c 518 l.add r4,r4,r1 519 l.lwz r5,0(r4) 520 l.sb 3(r2),r5 521 l.srli r5,r5,8 522 l.sb 2(r2),r5 523 l.srli r5,r5,8 524 l.sb 1(r2),r5 525 l.srli r5,r5,8 526 l.j align_end 527 l.sb 0(r2),r5 528 529align_end: 530 l.j _ret_from_intr 531 l.nop 532#endif 533 534/* ---[ 0x700: Illegal insn exception ]---------------------------------- */ 535 536EXCEPTION_ENTRY(_illegal_instruction_handler) 537 /* r4: EA of fault (set by EXCEPTION_HANDLE) */ 538 l.jal do_illegal_instruction 539 l.addi r3,r1,0 /* pt_regs */ 540 541 l.j _ret_from_exception 542 l.nop 543 544/* ---[ 0x800: External interrupt exception ]---------------------------- */ 545 546EXCEPTION_ENTRY(_external_irq_handler) 547#ifdef CONFIG_OPENRISC_ESR_EXCEPTION_BUG_CHECK 548 l.lwz r4,PT_SR(r1) // were interrupts enabled ? 549 l.andi r4,r4,SPR_SR_IEE 550 l.sfeqi r4,0 551 l.bnf 1f // ext irq enabled, all ok. 552 l.nop 553 554#ifdef CONFIG_PRINTK 555 l.addi r1,r1,-0x8 556 l.movhi r3,hi(42f) 557 l.ori r3,r3,lo(42f) 558 l.sw 0x0(r1),r3 559 l.jal _printk 560 l.sw 0x4(r1),r4 561 l.addi r1,r1,0x8 562 563 .section .rodata, "a" 56442: 565 .string "\n\rESR interrupt bug: in _external_irq_handler (ESR %x)\n\r" 566 .align 4 567 .previous 568#endif 569 570 l.ori r4,r4,SPR_SR_IEE // fix the bug 571// l.sw PT_SR(r1),r4 5721: 573#endif 574 CLEAR_LWA_FLAG(r3) 575 l.addi r3,r1,0 576 l.movhi r8,hi(generic_handle_arch_irq) 577 l.ori r8,r8,lo(generic_handle_arch_irq) 578 l.jalr r8 579 l.nop 580 l.j _ret_from_intr 581 l.nop 582 583/* ---[ 0x900: DTLB miss exception ]------------------------------------- */ 584 585 586/* ---[ 0xa00: ITLB miss exception ]------------------------------------- */ 587 588 589/* ---[ 0xb00: Range exception ]----------------------------------------- */ 590 591UNHANDLED_EXCEPTION(_vector_0xb00,0xb00) 592 593/* ---[ 0xc00: Syscall exception ]--------------------------------------- */ 594 595/* 596 * Syscalls are a special type of exception in that they are 597 * _explicitly_ invoked by userspace and can therefore be 598 * held to conform to the same ABI as normal functions with 599 * respect to whether registers are preserved across the call 600 * or not. 601 */ 602 603/* Upon syscall entry we just save the callee-saved registers 604 * and not the call-clobbered ones. 605 */ 606 607_string_syscall_return: 608 .string "syscall r9:0x%08x -> syscall(%ld) return %ld\0" 609 .align 4 610 611ENTRY(_sys_call_handler) 612 /* r1, EPCR, ESR a already saved */ 613 l.sw PT_GPR2(r1),r2 614 /* r3-r8 must be saved because syscall restart relies 615 * on us being able to restart the syscall args... technically 616 * they should be clobbered, otherwise 617 */ 618 l.sw PT_GPR3(r1),r3 619 /* 620 * r4 already saved 621 * r4 holds the EEAR address of the fault, use it as screatch reg and 622 * then load the original r4 623 */ 624 CLEAR_LWA_FLAG(r4) 625 l.lwz r4,PT_GPR4(r1) 626 l.sw PT_GPR5(r1),r5 627 l.sw PT_GPR6(r1),r6 628 l.sw PT_GPR7(r1),r7 629 l.sw PT_GPR8(r1),r8 630 l.sw PT_GPR9(r1),r9 631 /* r10 already saved */ 632 l.sw PT_GPR11(r1),r11 633 /* orig_gpr11 must be set for syscalls */ 634 l.sw PT_ORIG_GPR11(r1),r11 635 /* r12,r13 already saved */ 636 637 /* r14-r28 (even) aren't touched by the syscall fast path below 638 * so we don't need to save them. However, the functions that return 639 * to userspace via a call to switch() DO need to save these because 640 * switch() effectively clobbers them... saving these registers for 641 * such functions is handled in their syscall wrappers (see fork, vfork, 642 * and clone, below). 643 644 /* r30 is the only register we clobber in the fast path */ 645 /* r30 already saved */ 646/* l.sw PT_GPR30(r1),r30 */ 647 648_syscall_check_trace_enter: 649 /* syscalls run with interrupts enabled */ 650 TRACE_IRQS_ON_SYSCALL 651 ENABLE_INTERRUPTS(r29) // enable interrupts, r29 is temp 652 653 /* If TIF_SYSCALL_TRACE is set, then we want to do syscall tracing */ 654 l.lwz r30,TI_FLAGS(r10) 655 l.andi r30,r30,_TIF_SYSCALL_TRACE 656 l.sfne r30,r0 657 l.bf _syscall_trace_enter 658 l.nop 659 660_syscall_check: 661 /* Ensure that the syscall number is reasonable */ 662 l.sfgeui r11,__NR_syscalls 663 l.bf _syscall_badsys 664 l.nop 665 666_syscall_call: 667 l.movhi r29,hi(sys_call_table) 668 l.ori r29,r29,lo(sys_call_table) 669 l.slli r11,r11,2 670 l.add r29,r29,r11 671 l.lwz r29,0(r29) 672 673 l.jalr r29 674 l.nop 675 676_syscall_return: 677 /* All syscalls return here... just pay attention to ret_from_fork 678 * which does it in a round-about way. 679 */ 680 l.sw PT_GPR11(r1),r11 // save return value 681 682#if 0 683_syscall_debug: 684 l.movhi r3,hi(_string_syscall_return) 685 l.ori r3,r3,lo(_string_syscall_return) 686 l.ori r27,r0,2 687 l.sw -4(r1),r27 688 l.sw -8(r1),r11 689 l.lwz r29,PT_ORIG_GPR11(r1) 690 l.sw -12(r1),r29 691 l.lwz r29,PT_GPR9(r1) 692 l.sw -16(r1),r29 693 l.movhi r27,hi(_printk) 694 l.ori r27,r27,lo(_printk) 695 l.jalr r27 696 l.addi r1,r1,-16 697 l.addi r1,r1,16 698#endif 699#if 0 700_syscall_show_regs: 701 l.movhi r27,hi(show_registers) 702 l.ori r27,r27,lo(show_registers) 703 l.jalr r27 704 l.or r3,r1,r1 705#endif 706 707_syscall_check_trace_leave: 708 /* r30 is a callee-saved register so this should still hold the 709 * _TIF_SYSCALL_TRACE flag from _syscall_check_trace_enter above... 710 * _syscall_trace_leave expects syscall result to be in pt_regs->r11. 711 */ 712 l.sfne r30,r0 713 l.bf _syscall_trace_leave 714 l.nop 715 716/* This is where the exception-return code begins... interrupts need to be 717 * disabled the rest of the way here because we can't afford to miss any 718 * interrupts that set NEED_RESCHED or SIGNALPENDING... really true? */ 719 720_syscall_check_work: 721 /* Here we need to disable interrupts */ 722 DISABLE_INTERRUPTS(r27,r29) 723 TRACE_IRQS_OFF 724 l.lwz r30,TI_FLAGS(r10) 725 l.andi r30,r30,_TIF_WORK_MASK 726 l.sfne r30,r0 727 728 l.bnf _syscall_resume_userspace 729 l.nop 730 731 /* Work pending follows a different return path, so we need to 732 * make sure that all the call-saved registers get into pt_regs 733 * before branching... 734 */ 735 l.sw PT_GPR14(r1),r14 736 l.sw PT_GPR16(r1),r16 737 l.sw PT_GPR18(r1),r18 738 l.sw PT_GPR20(r1),r20 739 l.sw PT_GPR22(r1),r22 740 l.sw PT_GPR24(r1),r24 741 l.sw PT_GPR26(r1),r26 742 l.sw PT_GPR28(r1),r28 743 744 /* _work_pending needs to be called with interrupts disabled */ 745 l.j _work_pending 746 l.nop 747 748_syscall_resume_userspace: 749// ENABLE_INTERRUPTS(r29) 750 751 752/* This is the hot path for returning to userspace from a syscall. If there's 753 * work to be done and the branch to _work_pending was taken above, then the 754 * return to userspace will be done via the normal exception return path... 755 * that path restores _all_ registers and will overwrite the "clobbered" 756 * registers with whatever garbage is in pt_regs -- that's OK because those 757 * registers are clobbered anyway and because the extra work is insignificant 758 * in the context of the extra work that _work_pending is doing. 759 760/* Once again, syscalls are special and only guarantee to preserve the 761 * same registers as a normal function call */ 762 763/* The assumption here is that the registers r14-r28 (even) are untouched and 764 * don't need to be restored... be sure that that's really the case! 765 */ 766 767/* This is still too much... we should only be restoring what we actually 768 * clobbered... we should even be using 'scratch' (odd) regs above so that 769 * we don't need to restore anything, hardly... 770 */ 771 772 l.lwz r2,PT_GPR2(r1) 773 774 /* Restore args */ 775 /* r3-r8 are technically clobbered, but syscall restart needs these 776 * to be restored... 777 */ 778 l.lwz r3,PT_GPR3(r1) 779 l.lwz r4,PT_GPR4(r1) 780 l.lwz r5,PT_GPR5(r1) 781 l.lwz r6,PT_GPR6(r1) 782 l.lwz r7,PT_GPR7(r1) 783 l.lwz r8,PT_GPR8(r1) 784 785 l.lwz r9,PT_GPR9(r1) 786 l.lwz r10,PT_GPR10(r1) 787 l.lwz r11,PT_GPR11(r1) 788 789 /* r30 is the only register we clobber in the fast path */ 790 l.lwz r30,PT_GPR30(r1) 791 792 /* Here we use r13-r19 (odd) as scratch regs */ 793 l.lwz r13,PT_PC(r1) 794 l.lwz r15,PT_SR(r1) 795 l.lwz r1,PT_SP(r1) 796 /* Interrupts need to be disabled for setting EPCR and ESR 797 * so that another interrupt doesn't come in here and clobber 798 * them before we can use them for our l.rfe */ 799 DISABLE_INTERRUPTS(r17,r19) 800 l.mtspr r0,r13,SPR_EPCR_BASE 801 l.mtspr r0,r15,SPR_ESR_BASE 802 l.rfe 803 804/* End of hot path! 805 * Keep the below tracing and error handling out of the hot path... 806*/ 807 808_syscall_trace_enter: 809 /* Here we pass pt_regs to do_syscall_trace_enter. Make sure 810 * that function is really getting all the info it needs as 811 * pt_regs isn't a complete set of userspace regs, just the 812 * ones relevant to the syscall... 813 * 814 * Note use of delay slot for setting argument. 815 */ 816 l.jal do_syscall_trace_enter 817 l.addi r3,r1,0 818 819 /* Restore arguments (not preserved across do_syscall_trace_enter) 820 * so that we can do the syscall for real and return to the syscall 821 * hot path. 822 */ 823 l.lwz r11,PT_GPR11(r1) 824 l.lwz r3,PT_GPR3(r1) 825 l.lwz r4,PT_GPR4(r1) 826 l.lwz r5,PT_GPR5(r1) 827 l.lwz r6,PT_GPR6(r1) 828 l.lwz r7,PT_GPR7(r1) 829 830 l.j _syscall_check 831 l.lwz r8,PT_GPR8(r1) 832 833_syscall_trace_leave: 834 l.jal do_syscall_trace_leave 835 l.addi r3,r1,0 836 837 l.j _syscall_check_work 838 l.nop 839 840_syscall_badsys: 841 /* Here we effectively pretend to have executed an imaginary 842 * syscall that returns -ENOSYS and then return to the regular 843 * syscall hot path. 844 * Note that "return value" is set in the delay slot... 845 */ 846 l.j _syscall_return 847 l.addi r11,r0,-ENOSYS 848 849/******* END SYSCALL HANDLING *******/ 850 851/* ---[ 0xd00: Floating Point exception ]-------------------------------- */ 852 853EXCEPTION_ENTRY(_fpe_trap_handler) 854 CLEAR_LWA_FLAG(r3) 855 /* r4: EA of fault (set by EXCEPTION_HANDLE) */ 856 l.jal do_fpe_trap 857 l.addi r3,r1,0 /* pt_regs */ 858 859 l.j _ret_from_exception 860 l.nop 861 862/* ---[ 0xe00: Trap exception ]------------------------------------------ */ 863 864EXCEPTION_ENTRY(_trap_handler) 865 CLEAR_LWA_FLAG(r3) 866 /* r4: EA of fault (set by EXCEPTION_HANDLE) */ 867 l.jal do_trap 868 l.addi r3,r1,0 /* pt_regs */ 869 870 l.j _ret_from_exception 871 l.nop 872 873/* ---[ 0xf00: Reserved exception ]-------------------------------------- */ 874 875UNHANDLED_EXCEPTION(_vector_0xf00,0xf00) 876 877/* ---[ 0x1000: Reserved exception ]------------------------------------- */ 878 879UNHANDLED_EXCEPTION(_vector_0x1000,0x1000) 880 881/* ---[ 0x1100: Reserved exception ]------------------------------------- */ 882 883UNHANDLED_EXCEPTION(_vector_0x1100,0x1100) 884 885/* ---[ 0x1200: Reserved exception ]------------------------------------- */ 886 887UNHANDLED_EXCEPTION(_vector_0x1200,0x1200) 888 889/* ---[ 0x1300: Reserved exception ]------------------------------------- */ 890 891UNHANDLED_EXCEPTION(_vector_0x1300,0x1300) 892 893/* ---[ 0x1400: Reserved exception ]------------------------------------- */ 894 895UNHANDLED_EXCEPTION(_vector_0x1400,0x1400) 896 897/* ---[ 0x1500: Reserved exception ]------------------------------------- */ 898 899UNHANDLED_EXCEPTION(_vector_0x1500,0x1500) 900 901/* ---[ 0x1600: Reserved exception ]------------------------------------- */ 902 903UNHANDLED_EXCEPTION(_vector_0x1600,0x1600) 904 905/* ---[ 0x1700: Reserved exception ]------------------------------------- */ 906 907UNHANDLED_EXCEPTION(_vector_0x1700,0x1700) 908 909/* ---[ 0x1800: Reserved exception ]------------------------------------- */ 910 911UNHANDLED_EXCEPTION(_vector_0x1800,0x1800) 912 913/* ---[ 0x1900: Reserved exception ]------------------------------------- */ 914 915UNHANDLED_EXCEPTION(_vector_0x1900,0x1900) 916 917/* ---[ 0x1a00: Reserved exception ]------------------------------------- */ 918 919UNHANDLED_EXCEPTION(_vector_0x1a00,0x1a00) 920 921/* ---[ 0x1b00: Reserved exception ]------------------------------------- */ 922 923UNHANDLED_EXCEPTION(_vector_0x1b00,0x1b00) 924 925/* ---[ 0x1c00: Reserved exception ]------------------------------------- */ 926 927UNHANDLED_EXCEPTION(_vector_0x1c00,0x1c00) 928 929/* ---[ 0x1d00: Reserved exception ]------------------------------------- */ 930 931UNHANDLED_EXCEPTION(_vector_0x1d00,0x1d00) 932 933/* ---[ 0x1e00: Reserved exception ]------------------------------------- */ 934 935UNHANDLED_EXCEPTION(_vector_0x1e00,0x1e00) 936 937/* ---[ 0x1f00: Reserved exception ]------------------------------------- */ 938 939UNHANDLED_EXCEPTION(_vector_0x1f00,0x1f00) 940 941/* ========================================================[ return ] === */ 942 943_resume_userspace: 944 DISABLE_INTERRUPTS(r3,r4) 945 TRACE_IRQS_OFF 946 l.lwz r4,TI_FLAGS(r10) 947 l.andi r13,r4,_TIF_WORK_MASK 948 l.sfeqi r13,0 949 l.bf _restore_all 950 l.nop 951 952_work_pending: 953 l.lwz r5,PT_ORIG_GPR11(r1) 954 l.sfltsi r5,0 955 l.bnf 1f 956 l.nop 957 l.andi r5,r5,0 9581: 959 l.jal do_work_pending 960 l.ori r3,r1,0 /* pt_regs */ 961 962 l.sfeqi r11,0 963 l.bf _restore_all 964 l.nop 965 l.sfltsi r11,0 966 l.bnf 1f 967 l.nop 968 l.and r11,r11,r0 969 l.ori r11,r11,__NR_restart_syscall 970 l.j _syscall_check_trace_enter 971 l.nop 9721: 973 l.lwz r11,PT_ORIG_GPR11(r1) 974 /* Restore arg registers */ 975 l.lwz r3,PT_GPR3(r1) 976 l.lwz r4,PT_GPR4(r1) 977 l.lwz r5,PT_GPR5(r1) 978 l.lwz r6,PT_GPR6(r1) 979 l.lwz r7,PT_GPR7(r1) 980 l.j _syscall_check_trace_enter 981 l.lwz r8,PT_GPR8(r1) 982 983_restore_all: 984#ifdef CONFIG_TRACE_IRQFLAGS 985 l.lwz r4,PT_SR(r1) 986 l.andi r3,r4,(SPR_SR_IEE|SPR_SR_TEE) 987 l.sfeq r3,r0 /* skip trace if irqs were off */ 988 l.bf skip_hardirqs_on 989 l.nop 990 TRACE_IRQS_ON 991skip_hardirqs_on: 992#endif 993 RESTORE_ALL 994 /* This returns to userspace code */ 995 996 997ENTRY(_ret_from_intr) 998ENTRY(_ret_from_exception) 999 l.lwz r4,PT_SR(r1) 1000 l.andi r3,r4,SPR_SR_SM 1001 l.sfeqi r3,0 1002 l.bnf _restore_all 1003 l.nop 1004 l.j _resume_userspace 1005 l.nop 1006 1007ENTRY(ret_from_fork) 1008 l.jal schedule_tail 1009 l.nop 1010 1011 /* Check if we are a kernel thread */ 1012 l.sfeqi r20,0 1013 l.bf 1f 1014 l.nop 1015 1016 /* ...we are a kernel thread so invoke the requested callback */ 1017 l.jalr r20 1018 l.or r3,r22,r0 1019 10201: 1021 /* _syscall_returns expect r11 to contain return value */ 1022 l.lwz r11,PT_GPR11(r1) 1023 1024 /* The syscall fast path return expects call-saved registers 1025 * r14-r28 to be untouched, so we restore them here as they 1026 * will have been effectively clobbered when arriving here 1027 * via the call to switch() 1028 */ 1029 l.lwz r14,PT_GPR14(r1) 1030 l.lwz r16,PT_GPR16(r1) 1031 l.lwz r18,PT_GPR18(r1) 1032 l.lwz r20,PT_GPR20(r1) 1033 l.lwz r22,PT_GPR22(r1) 1034 l.lwz r24,PT_GPR24(r1) 1035 l.lwz r26,PT_GPR26(r1) 1036 l.lwz r28,PT_GPR28(r1) 1037 1038 l.j _syscall_return 1039 l.nop 1040 1041/* ========================================================[ switch ] === */ 1042 1043/* 1044 * This routine switches between two different tasks. The process 1045 * state of one is saved on its kernel stack. Then the state 1046 * of the other is restored from its kernel stack. The memory 1047 * management hardware is updated to the second process's state. 1048 * Finally, we can return to the second process, via the 'return'. 1049 * 1050 * Note: there are two ways to get to the "going out" portion 1051 * of this code; either by coming in via the entry (_switch) 1052 * or via "fork" which must set up an environment equivalent 1053 * to the "_switch" path. If you change this (or in particular, the 1054 * SAVE_REGS macro), you'll have to change the fork code also. 1055 */ 1056 1057 1058/* _switch MUST never lay on page boundry, cause it runs from 1059 * effective addresses and beeing interrupted by iTLB miss would kill it. 1060 * dTLB miss seems to never accour in the bad place since data accesses 1061 * are from task structures which are always page aligned. 1062 * 1063 * The problem happens in RESTORE_ALL where we first set the EPCR 1064 * register, then load the previous register values and only at the end call 1065 * the l.rfe instruction. If get TLB miss in beetwen the EPCR register gets 1066 * garbled and we end up calling l.rfe with the wrong EPCR. (same probably 1067 * holds for ESR) 1068 * 1069 * To avoid this problems it is sufficient to align _switch to 1070 * some nice round number smaller than it's size... 1071 */ 1072 1073/* ABI rules apply here... we either enter _switch via schedule() or via 1074 * an imaginary call to which we shall return at return_from_fork. Either 1075 * way, we are a function call and only need to preserve the callee-saved 1076 * registers when we return. As such, we don't need to save the registers 1077 * on the stack that we won't be returning as they were... 1078 */ 1079 1080 .align 0x400 1081ENTRY(_switch) 1082 /* We don't store SR as _switch only gets called in a context where 1083 * the SR will be the same going in and coming out... */ 1084 1085 /* Set up new pt_regs struct for saving task state */ 1086 l.addi r1,r1,-(INT_FRAME_SIZE) 1087 1088 /* No need to store r1/PT_SP as it goes into KSP below */ 1089 l.sw PT_GPR2(r1),r2 1090 l.sw PT_GPR9(r1),r9 1091 1092 /* Save callee-saved registers to the new pt_regs */ 1093 l.sw PT_GPR14(r1),r14 1094 l.sw PT_GPR16(r1),r16 1095 l.sw PT_GPR18(r1),r18 1096 l.sw PT_GPR20(r1),r20 1097 l.sw PT_GPR22(r1),r22 1098 l.sw PT_GPR24(r1),r24 1099 l.sw PT_GPR26(r1),r26 1100 l.sw PT_GPR28(r1),r28 1101 l.sw PT_GPR30(r1),r30 1102 1103 /* Store the old FPU state to new pt_regs */ 1104 l.mfspr r29,r0,SPR_FPCSR 1105 l.sw PT_FPCSR(r1),r29 1106 1107 l.addi r11,r10,0 /* Save old 'current' to 'last' return value*/ 1108 1109 /* We use thread_info->ksp for storing the address of the above 1110 * structure so that we can get back to it later... we don't want 1111 * to lose the value of thread_info->ksp, though, so store it as 1112 * pt_regs->sp so that we can easily restore it when we are made 1113 * live again... 1114 */ 1115 1116 /* Save the old value of thread_info->ksp as pt_regs->sp */ 1117 l.lwz r29,TI_KSP(r10) 1118 l.sw PT_SP(r1),r29 1119 1120 /* Swap kernel stack pointers */ 1121 l.sw TI_KSP(r10),r1 /* Save old stack pointer */ 1122 l.or r10,r4,r0 /* Set up new current_thread_info */ 1123 l.lwz r1,TI_KSP(r10) /* Load new stack pointer */ 1124 1125 /* Restore the old value of thread_info->ksp */ 1126 l.lwz r29,PT_SP(r1) 1127 l.sw TI_KSP(r10),r29 1128 1129 /* Restore the old value of FPCSR */ 1130 l.lwz r29,PT_FPCSR(r1) 1131 l.mtspr r0,r29,SPR_FPCSR 1132 1133 /* ...and restore the registers, except r11 because the return value 1134 * has already been set above. 1135 */ 1136 l.lwz r2,PT_GPR2(r1) 1137 l.lwz r9,PT_GPR9(r1) 1138 /* No need to restore r10 */ 1139 /* ...and do not restore r11 */ 1140 1141 /* Restore callee-saved registers */ 1142 l.lwz r14,PT_GPR14(r1) 1143 l.lwz r16,PT_GPR16(r1) 1144 l.lwz r18,PT_GPR18(r1) 1145 l.lwz r20,PT_GPR20(r1) 1146 l.lwz r22,PT_GPR22(r1) 1147 l.lwz r24,PT_GPR24(r1) 1148 l.lwz r26,PT_GPR26(r1) 1149 l.lwz r28,PT_GPR28(r1) 1150 l.lwz r30,PT_GPR30(r1) 1151 1152 /* Unwind stack to pre-switch state */ 1153 l.addi r1,r1,(INT_FRAME_SIZE) 1154 1155 /* Return via the link-register back to where we 'came from', where 1156 * that may be either schedule(), ret_from_fork(), or 1157 * ret_from_kernel_thread(). If we are returning to a new thread, 1158 * we are expected to have set up the arg to schedule_tail already, 1159 * hence we do so here unconditionally: 1160 */ 1161 l.lwz r3,TI_TASK(r3) /* Load 'prev' as schedule_tail arg */ 1162 l.jr r9 1163 l.nop 1164 1165/* ==================================================================== */ 1166 1167/* These all use the delay slot for setting the argument register, so the 1168 * jump is always happening after the l.addi instruction. 1169 * 1170 * These are all just wrappers that don't touch the link-register r9, so the 1171 * return from the "real" syscall function will return back to the syscall 1172 * code that did the l.jal that brought us here. 1173 */ 1174 1175/* fork requires that we save all the callee-saved registers because they 1176 * are all effectively clobbered by the call to _switch. Here we store 1177 * all the registers that aren't touched by the syscall fast path and thus 1178 * weren't saved there. 1179 */ 1180 1181_fork_save_extra_regs_and_call: 1182 l.sw PT_GPR14(r1),r14 1183 l.sw PT_GPR16(r1),r16 1184 l.sw PT_GPR18(r1),r18 1185 l.sw PT_GPR20(r1),r20 1186 l.sw PT_GPR22(r1),r22 1187 l.sw PT_GPR24(r1),r24 1188 l.sw PT_GPR26(r1),r26 1189 l.jr r29 1190 l.sw PT_GPR28(r1),r28 1191 1192ENTRY(__sys_clone) 1193 l.movhi r29,hi(sys_clone) 1194 l.j _fork_save_extra_regs_and_call 1195 l.ori r29,r29,lo(sys_clone) 1196 1197ENTRY(__sys_clone3) 1198 l.movhi r29,hi(sys_clone3) 1199 l.j _fork_save_extra_regs_and_call 1200 l.ori r29,r29,lo(sys_clone3) 1201 1202ENTRY(__sys_fork) 1203 l.movhi r29,hi(sys_fork) 1204 l.j _fork_save_extra_regs_and_call 1205 l.ori r29,r29,lo(sys_fork) 1206 1207ENTRY(sys_rt_sigreturn) 1208 l.jal _sys_rt_sigreturn 1209 l.addi r3,r1,0 1210 l.sfne r30,r0 1211 l.bnf _no_syscall_trace 1212 l.nop 1213 l.jal do_syscall_trace_leave 1214 l.addi r3,r1,0 1215_no_syscall_trace: 1216 l.j _resume_userspace 1217 l.nop 1218 1219/* This is a catch-all syscall for atomic instructions for the OpenRISC 1000. 1220 * The functions takes a variable number of parameters depending on which 1221 * particular flavour of atomic you want... parameter 1 is a flag identifying 1222 * the atomic in question. Currently, this function implements the 1223 * following variants: 1224 * 1225 * XCHG: 1226 * @flag: 1 1227 * @ptr1: 1228 * @ptr2: 1229 * Atomically exchange the values in pointers 1 and 2. 1230 * 1231 */ 1232 1233ENTRY(sys_or1k_atomic) 1234 /* FIXME: This ignores r3 and always does an XCHG */ 1235 DISABLE_INTERRUPTS(r17,r19) 1236 l.lwz r29,0(r4) 1237 l.lwz r27,0(r5) 1238 l.sw 0(r4),r27 1239 l.sw 0(r5),r29 1240 ENABLE_INTERRUPTS(r17) 1241 l.jr r9 1242 l.or r11,r0,r0 1243 1244/* ============================================================[ EOF ]=== */ 1245