1 /*
2  * OpenRISC Linux
3  *
4  * SPR Definitions
5  *
6  * Copyright (C) 2000 Damjan Lampret
7  * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
8  * Copyright (C) 2008, 2010 Embecosm Limited
9  * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
10  * et al.
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License as published by
14  * the Free Software Foundation; either version 2 of the License, or
15  * (at your option) any later version.
16  *
17  * This file is part of OpenRISC 1000 Architectural Simulator.
18  */
19 
20 #ifndef SPR_DEFS__H
21 #define SPR_DEFS__H
22 
23 /* Definition of special-purpose registers (SPRs). */
24 
25 #define MAX_GRPS (32)
26 #define MAX_SPRS_PER_GRP_BITS (11)
27 #define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
28 #define MAX_SPRS (0x10000)
29 
30 /* Base addresses for the groups */
31 #define SPRGROUP_SYS	(0 << MAX_SPRS_PER_GRP_BITS)
32 #define SPRGROUP_DMMU	(1 << MAX_SPRS_PER_GRP_BITS)
33 #define SPRGROUP_IMMU	(2 << MAX_SPRS_PER_GRP_BITS)
34 #define SPRGROUP_DC	(3 << MAX_SPRS_PER_GRP_BITS)
35 #define SPRGROUP_IC	(4 << MAX_SPRS_PER_GRP_BITS)
36 #define SPRGROUP_MAC	(5 << MAX_SPRS_PER_GRP_BITS)
37 #define SPRGROUP_D	(6 << MAX_SPRS_PER_GRP_BITS)
38 #define SPRGROUP_PC	(7 << MAX_SPRS_PER_GRP_BITS)
39 #define SPRGROUP_PM	(8 << MAX_SPRS_PER_GRP_BITS)
40 #define SPRGROUP_PIC	(9 << MAX_SPRS_PER_GRP_BITS)
41 #define SPRGROUP_TT	(10 << MAX_SPRS_PER_GRP_BITS)
42 #define SPRGROUP_FP	(11 << MAX_SPRS_PER_GRP_BITS)
43 
44 /* System control and status group */
45 #define SPR_VR		(SPRGROUP_SYS + 0)
46 #define SPR_UPR		(SPRGROUP_SYS + 1)
47 #define SPR_CPUCFGR	(SPRGROUP_SYS + 2)
48 #define SPR_DMMUCFGR	(SPRGROUP_SYS + 3)
49 #define SPR_IMMUCFGR	(SPRGROUP_SYS + 4)
50 #define SPR_DCCFGR	(SPRGROUP_SYS + 5)
51 #define SPR_ICCFGR	(SPRGROUP_SYS + 6)
52 #define SPR_DCFGR	(SPRGROUP_SYS + 7)
53 #define SPR_PCCFGR	(SPRGROUP_SYS + 8)
54 #define SPR_VR2		(SPRGROUP_SYS + 9)
55 #define SPR_AVR		(SPRGROUP_SYS + 10)
56 #define SPR_EVBAR	(SPRGROUP_SYS + 11)
57 #define SPR_AECR	(SPRGROUP_SYS + 12)
58 #define SPR_AESR	(SPRGROUP_SYS + 13)
59 #define SPR_NPC         (SPRGROUP_SYS + 16)  /* CZ 21/06/01 */
60 #define SPR_SR		(SPRGROUP_SYS + 17)  /* CZ 21/06/01 */
61 #define SPR_PPC         (SPRGROUP_SYS + 18)  /* CZ 21/06/01 */
62 #define SPR_FPCSR       (SPRGROUP_SYS + 20)  /* CZ 21/06/01 */
63 #define SPR_EPCR_BASE	(SPRGROUP_SYS + 32)  /* CZ 21/06/01 */
64 #define SPR_EPCR_LAST	(SPRGROUP_SYS + 47)  /* CZ 21/06/01 */
65 #define SPR_EEAR_BASE	(SPRGROUP_SYS + 48)
66 #define SPR_EEAR_LAST	(SPRGROUP_SYS + 63)
67 #define SPR_ESR_BASE	(SPRGROUP_SYS + 64)
68 #define SPR_ESR_LAST	(SPRGROUP_SYS + 79)
69 #define SPR_COREID	(SPRGROUP_SYS + 128)
70 #define SPR_NUMCORES	(SPRGROUP_SYS + 129)
71 #define SPR_GPR_BASE	(SPRGROUP_SYS + 1024)
72 
73 /* Data MMU group */
74 #define SPR_DMMUCR	(SPRGROUP_DMMU + 0)
75 #define SPR_DTLBEIR	(SPRGROUP_DMMU + 2)
76 #define SPR_DTLBMR_BASE(WAY)	(SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
77 #define SPR_DTLBMR_LAST(WAY)	(SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
78 #define SPR_DTLBTR_BASE(WAY)	(SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
79 #define SPR_DTLBTR_LAST(WAY)	(SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
80 
81 /* Instruction MMU group */
82 #define SPR_IMMUCR	(SPRGROUP_IMMU + 0)
83 #define SPR_ITLBEIR	(SPRGROUP_IMMU + 2)
84 #define SPR_ITLBMR_BASE(WAY)	(SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
85 #define SPR_ITLBMR_LAST(WAY)	(SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
86 #define SPR_ITLBTR_BASE(WAY)	(SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
87 #define SPR_ITLBTR_LAST(WAY)	(SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
88 
89 /* Data cache group */
90 #define SPR_DCCR	(SPRGROUP_DC + 0)
91 #define SPR_DCBPR	(SPRGROUP_DC + 1)
92 #define SPR_DCBFR	(SPRGROUP_DC + 2)
93 #define SPR_DCBIR	(SPRGROUP_DC + 3)
94 #define SPR_DCBWR	(SPRGROUP_DC + 4)
95 #define SPR_DCBLR	(SPRGROUP_DC + 5)
96 #define SPR_DCR_BASE(WAY)	(SPRGROUP_DC + 0x200 + (WAY) * 0x200)
97 #define SPR_DCR_LAST(WAY)	(SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
98 
99 /* Instruction cache group */
100 #define SPR_ICCR	(SPRGROUP_IC + 0)
101 #define SPR_ICBPR	(SPRGROUP_IC + 1)
102 #define SPR_ICBIR	(SPRGROUP_IC + 2)
103 #define SPR_ICBLR	(SPRGROUP_IC + 3)
104 #define SPR_ICR_BASE(WAY)	(SPRGROUP_IC + 0x200 + (WAY) * 0x200)
105 #define SPR_ICR_LAST(WAY)	(SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
106 
107 /* MAC group */
108 #define SPR_MACLO	(SPRGROUP_MAC + 1)
109 #define SPR_MACHI	(SPRGROUP_MAC + 2)
110 
111 /* Debug group */
112 #define SPR_DVR(N)	(SPRGROUP_D + (N))
113 #define SPR_DCR(N)	(SPRGROUP_D + 8 + (N))
114 #define SPR_DMR1	(SPRGROUP_D + 16)
115 #define SPR_DMR2	(SPRGROUP_D + 17)
116 #define SPR_DWCR0	(SPRGROUP_D + 18)
117 #define SPR_DWCR1	(SPRGROUP_D + 19)
118 #define SPR_DSR		(SPRGROUP_D + 20)
119 #define SPR_DRR		(SPRGROUP_D + 21)
120 
121 /* Performance counters group */
122 #define SPR_PCCR(N)	(SPRGROUP_PC + (N))
123 #define SPR_PCMR(N)	(SPRGROUP_PC + 8 + (N))
124 
125 /* Power management group */
126 #define SPR_PMR (SPRGROUP_PM + 0)
127 
128 /* PIC group */
129 #define SPR_PICMR (SPRGROUP_PIC + 0)
130 #define SPR_PICPR (SPRGROUP_PIC + 1)
131 #define SPR_PICSR (SPRGROUP_PIC + 2)
132 
133 /* Tick Timer group */
134 #define SPR_TTMR (SPRGROUP_TT + 0)
135 #define SPR_TTCR (SPRGROUP_TT + 1)
136 
137 /*
138  * Bit definitions for the Version Register
139  *
140  */
141 #define SPR_VR_VER	0xff000000  /* Processor version */
142 #define SPR_VR_CFG	0x00ff0000  /* Processor configuration */
143 #define SPR_VR_RES	0x0000ffc0  /* Reserved */
144 #define SPR_VR_REV	0x0000003f  /* Processor revision */
145 #define SPR_VR_UVRP	0x00000040  /* Updated Version Registers Present */
146 
147 #define SPR_VR_VER_OFF	24
148 #define SPR_VR_CFG_OFF	16
149 #define SPR_VR_REV_OFF	0
150 
151 /*
152  * Bit definitions for the Version Register 2
153  */
154 #define SPR_VR2_CPUID	0xff000000  /* Processor ID */
155 #define SPR_VR2_VER	0x00ffffff  /* Processor version */
156 
157 /*
158  * Bit definitions for the Unit Present Register
159  *
160  */
161 #define SPR_UPR_UP	   0x00000001  /* UPR present */
162 #define SPR_UPR_DCP	   0x00000002  /* Data cache present */
163 #define SPR_UPR_ICP	   0x00000004  /* Instruction cache present */
164 #define SPR_UPR_DMP	   0x00000008  /* Data MMU present */
165 #define SPR_UPR_IMP	   0x00000010  /* Instruction MMU present */
166 #define SPR_UPR_MP	   0x00000020  /* MAC present */
167 #define SPR_UPR_DUP	   0x00000040  /* Debug unit present */
168 #define SPR_UPR_PCUP	   0x00000080  /* Performance counters unit present */
169 #define SPR_UPR_PICP	   0x00000100  /* PIC present */
170 #define SPR_UPR_PMP	   0x00000200  /* Power management present */
171 #define SPR_UPR_TTP	   0x00000400  /* Tick timer present */
172 #define SPR_UPR_RES	   0x00fe0000  /* Reserved */
173 #define SPR_UPR_CUP	   0xff000000  /* Context units present */
174 
175 /*
176  * JPB: Bit definitions for the CPU configuration register
177  *
178  */
179 #define SPR_CPUCFGR_NSGF   0x0000000f  /* Number of shadow GPR files */
180 #define SPR_CPUCFGR_CGF	   0x00000010  /* Custom GPR file */
181 #define SPR_CPUCFGR_OB32S  0x00000020  /* ORBIS32 supported */
182 #define SPR_CPUCFGR_OB64S  0x00000040  /* ORBIS64 supported */
183 #define SPR_CPUCFGR_OF32S  0x00000080  /* ORFPX32 supported */
184 #define SPR_CPUCFGR_OF64S  0x00000100  /* ORFPX64 supported */
185 #define SPR_CPUCFGR_OV64S  0x00000200  /* ORVDX64 supported */
186 #define SPR_CPUCFGR_RES	   0xfffffc00  /* Reserved */
187 
188 /*
189  * JPB: Bit definitions for the Debug configuration register and other
190  * constants.
191  *
192  */
193 
194 #define SPR_DCFGR_NDP      0x00000007  /* Number of matchpoints mask */
195 #define SPR_DCFGR_NDP1     0x00000000  /* One matchpoint supported */
196 #define SPR_DCFGR_NDP2     0x00000001  /* Two matchpoints supported */
197 #define SPR_DCFGR_NDP3     0x00000002  /* Three matchpoints supported */
198 #define SPR_DCFGR_NDP4     0x00000003  /* Four matchpoints supported */
199 #define SPR_DCFGR_NDP5     0x00000004  /* Five matchpoints supported */
200 #define SPR_DCFGR_NDP6     0x00000005  /* Six matchpoints supported */
201 #define SPR_DCFGR_NDP7     0x00000006  /* Seven matchpoints supported */
202 #define SPR_DCFGR_NDP8     0x00000007  /* Eight matchpoints supported */
203 #define SPR_DCFGR_WPCI     0x00000008  /* Watchpoint counters implemented */
204 
205 #define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \
206                                2 == n ? SPR_DCFGR_NDP2 : \
207                                3 == n ? SPR_DCFGR_NDP3 : \
208                                4 == n ? SPR_DCFGR_NDP4 : \
209                                5 == n ? SPR_DCFGR_NDP5 : \
210                                6 == n ? SPR_DCFGR_NDP6 : \
211                                7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8)
212 #define MAX_MATCHPOINTS  8
213 #define MAX_WATCHPOINTS  (MAX_MATCHPOINTS + 2)
214 
215 /*
216  * Bit definitions for the Supervision Register
217  *
218  */
219 #define SPR_SR_SM          0x00000001  /* Supervisor Mode */
220 #define SPR_SR_TEE         0x00000002  /* Tick timer Exception Enable */
221 #define SPR_SR_IEE         0x00000004  /* Interrupt Exception Enable */
222 #define SPR_SR_DCE         0x00000008  /* Data Cache Enable */
223 #define SPR_SR_ICE         0x00000010  /* Instruction Cache Enable */
224 #define SPR_SR_DME         0x00000020  /* Data MMU Enable */
225 #define SPR_SR_IME         0x00000040  /* Instruction MMU Enable */
226 #define SPR_SR_LEE         0x00000080  /* Little Endian Enable */
227 #define SPR_SR_CE          0x00000100  /* CID Enable */
228 #define SPR_SR_F           0x00000200  /* Condition Flag */
229 #define SPR_SR_CY          0x00000400  /* Carry flag */
230 #define SPR_SR_OV          0x00000800  /* Overflow flag */
231 #define SPR_SR_OVE         0x00001000  /* Overflow flag Exception */
232 #define SPR_SR_DSX         0x00002000  /* Delay Slot Exception */
233 #define SPR_SR_EPH         0x00004000  /* Exception Prefix High */
234 #define SPR_SR_FO          0x00008000  /* Fixed one */
235 #define SPR_SR_SUMRA       0x00010000  /* Supervisor SPR read access */
236 #define SPR_SR_RES         0x0ffe0000  /* Reserved */
237 #define SPR_SR_CID         0xf0000000  /* Context ID */
238 
239 /*
240  * Bit definitions for the Data MMU Control Register
241  *
242  */
243 #define SPR_DMMUCR_P2S	   0x0000003e  /* Level 2 Page Size */
244 #define SPR_DMMUCR_P1S	   0x000007c0  /* Level 1 Page Size */
245 #define SPR_DMMUCR_VADDR_WIDTH	0x0000f800  /* Virtual ADDR Width */
246 #define SPR_DMMUCR_PADDR_WIDTH	0x000f0000  /* Physical ADDR Width */
247 
248 /*
249  * Bit definitions for the Instruction MMU Control Register
250  *
251  */
252 #define SPR_IMMUCR_P2S	   0x0000003e  /* Level 2 Page Size */
253 #define SPR_IMMUCR_P1S	   0x000007c0  /* Level 1 Page Size */
254 #define SPR_IMMUCR_VADDR_WIDTH	0x0000f800  /* Virtual ADDR Width */
255 #define SPR_IMMUCR_PADDR_WIDTH	0x000f0000  /* Physical ADDR Width */
256 
257 /*
258  * Bit definitions for the Data TLB Match Register
259  *
260  */
261 #define SPR_DTLBMR_V	   0x00000001  /* Valid */
262 #define SPR_DTLBMR_PL1	   0x00000002  /* Page Level 1 (if 0 then PL2) */
263 #define SPR_DTLBMR_CID	   0x0000003c  /* Context ID */
264 #define SPR_DTLBMR_LRU	   0x000000c0  /* Least Recently Used */
265 #define SPR_DTLBMR_VPN	   0xfffff000  /* Virtual Page Number */
266 
267 /*
268  * Bit definitions for the Data TLB Translate Register
269  *
270  */
271 #define SPR_DTLBTR_CC	   0x00000001  /* Cache Coherency */
272 #define SPR_DTLBTR_CI	   0x00000002  /* Cache Inhibit */
273 #define SPR_DTLBTR_WBC	   0x00000004  /* Write-Back Cache */
274 #define SPR_DTLBTR_WOM	   0x00000008  /* Weakly-Ordered Memory */
275 #define SPR_DTLBTR_A	   0x00000010  /* Accessed */
276 #define SPR_DTLBTR_D	   0x00000020  /* Dirty */
277 #define SPR_DTLBTR_URE	   0x00000040  /* User Read Enable */
278 #define SPR_DTLBTR_UWE	   0x00000080  /* User Write Enable */
279 #define SPR_DTLBTR_SRE	   0x00000100  /* Supervisor Read Enable */
280 #define SPR_DTLBTR_SWE	   0x00000200  /* Supervisor Write Enable */
281 #define SPR_DTLBTR_PPN	   0xfffff000  /* Physical Page Number */
282 
283 /*
284  * Bit definitions for the Instruction TLB Match Register
285  *
286  */
287 #define SPR_ITLBMR_V	   0x00000001  /* Valid */
288 #define SPR_ITLBMR_PL1	   0x00000002  /* Page Level 1 (if 0 then PL2) */
289 #define SPR_ITLBMR_CID	   0x0000003c  /* Context ID */
290 #define SPR_ITLBMR_LRU	   0x000000c0  /* Least Recently Used */
291 #define SPR_ITLBMR_VPN	   0xfffff000  /* Virtual Page Number */
292 
293 /*
294  * Bit definitions for the Instruction TLB Translate Register
295  *
296  */
297 #define SPR_ITLBTR_CC	   0x00000001  /* Cache Coherency */
298 #define SPR_ITLBTR_CI	   0x00000002  /* Cache Inhibit */
299 #define SPR_ITLBTR_WBC	   0x00000004  /* Write-Back Cache */
300 #define SPR_ITLBTR_WOM	   0x00000008  /* Weakly-Ordered Memory */
301 #define SPR_ITLBTR_A	   0x00000010  /* Accessed */
302 #define SPR_ITLBTR_D	   0x00000020  /* Dirty */
303 #define SPR_ITLBTR_SXE	   0x00000040  /* User Read Enable */
304 #define SPR_ITLBTR_UXE	   0x00000080  /* User Write Enable */
305 #define SPR_ITLBTR_PPN	   0xfffff000  /* Physical Page Number */
306 
307 /*
308  * Bit definitions for Data Cache Control register
309  *
310  */
311 #define SPR_DCCR_EW	   0x000000ff  /* Enable ways */
312 
313 /*
314  * Bit definitions for Insn Cache Control register
315  *
316  */
317 #define SPR_ICCR_EW	   0x000000ff  /* Enable ways */
318 
319 /*
320  * Bit definitions for Data Cache Configuration Register
321  *
322  */
323 
324 #define SPR_DCCFGR_NCW		0x00000007
325 #define SPR_DCCFGR_NCS		0x00000078
326 #define SPR_DCCFGR_CBS		0x00000080
327 #define SPR_DCCFGR_CWS		0x00000100
328 #define SPR_DCCFGR_CCRI		0x00000200
329 #define SPR_DCCFGR_CBIRI	0x00000400
330 #define SPR_DCCFGR_CBPRI	0x00000800
331 #define SPR_DCCFGR_CBLRI	0x00001000
332 #define SPR_DCCFGR_CBFRI	0x00002000
333 #define SPR_DCCFGR_CBWBRI	0x00004000
334 
335 #define SPR_DCCFGR_NCW_OFF      0
336 #define SPR_DCCFGR_NCS_OFF      3
337 #define SPR_DCCFGR_CBS_OFF	7
338 
339 /*
340  * Bit definitions for Instruction Cache Configuration Register
341  *
342  */
343 #define SPR_ICCFGR_NCW		0x00000007
344 #define SPR_ICCFGR_NCS		0x00000078
345 #define SPR_ICCFGR_CBS		0x00000080
346 #define SPR_ICCFGR_CCRI		0x00000200
347 #define SPR_ICCFGR_CBIRI	0x00000400
348 #define SPR_ICCFGR_CBPRI	0x00000800
349 #define SPR_ICCFGR_CBLRI	0x00001000
350 
351 #define SPR_ICCFGR_NCW_OFF      0
352 #define SPR_ICCFGR_NCS_OFF      3
353 #define SPR_ICCFGR_CBS_OFF	7
354 
355 /*
356  * Bit definitions for Data MMU Configuration Register
357  *
358  */
359 
360 #define SPR_DMMUCFGR_NTW	0x00000003
361 #define SPR_DMMUCFGR_NTS	0x0000001C
362 #define SPR_DMMUCFGR_NAE	0x000000E0
363 #define SPR_DMMUCFGR_CRI	0x00000100
364 #define SPR_DMMUCFGR_PRI        0x00000200
365 #define SPR_DMMUCFGR_TEIRI	0x00000400
366 #define SPR_DMMUCFGR_HTR	0x00000800
367 
368 #define SPR_DMMUCFGR_NTW_OFF	0
369 #define SPR_DMMUCFGR_NTS_OFF	2
370 
371 /*
372  * Bit definitions for Instruction MMU Configuration Register
373  *
374  */
375 
376 #define SPR_IMMUCFGR_NTW	0x00000003
377 #define SPR_IMMUCFGR_NTS	0x0000001C
378 #define SPR_IMMUCFGR_NAE	0x000000E0
379 #define SPR_IMMUCFGR_CRI	0x00000100
380 #define SPR_IMMUCFGR_PRI	0x00000200
381 #define SPR_IMMUCFGR_TEIRI	0x00000400
382 #define SPR_IMMUCFGR_HTR	0x00000800
383 
384 #define SPR_IMMUCFGR_NTW_OFF	0
385 #define SPR_IMMUCFGR_NTS_OFF	2
386 
387 /*
388  * Bit definitions for Debug Control registers
389  *
390  */
391 #define SPR_DCR_DP	0x00000001  /* DVR/DCR present */
392 #define SPR_DCR_CC	0x0000000e  /* Compare condition */
393 #define SPR_DCR_SC	0x00000010  /* Signed compare */
394 #define SPR_DCR_CT	0x000000e0  /* Compare to */
395 
396 /* Bit results with SPR_DCR_CC mask */
397 #define SPR_DCR_CC_MASKED 0x00000000
398 #define SPR_DCR_CC_EQUAL  0x00000002
399 #define SPR_DCR_CC_LESS   0x00000004
400 #define SPR_DCR_CC_LESSE  0x00000006
401 #define SPR_DCR_CC_GREAT  0x00000008
402 #define SPR_DCR_CC_GREATE 0x0000000a
403 #define SPR_DCR_CC_NEQUAL 0x0000000c
404 
405 /* Bit results with SPR_DCR_CT mask */
406 #define SPR_DCR_CT_DISABLED 0x00000000
407 #define SPR_DCR_CT_IFEA     0x00000020
408 #define SPR_DCR_CT_LEA      0x00000040
409 #define SPR_DCR_CT_SEA      0x00000060
410 #define SPR_DCR_CT_LD       0x00000080
411 #define SPR_DCR_CT_SD       0x000000a0
412 #define SPR_DCR_CT_LSEA     0x000000c0
413 #define SPR_DCR_CT_LSD	    0x000000e0
414 /* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */
415 
416 /*
417  * Bit definitions for Debug Mode 1 register
418  *
419  */
420 #define SPR_DMR1_CW       0x000fffff  /* Chain register pair data */
421 #define SPR_DMR1_CW0_AND  0x00000001
422 #define SPR_DMR1_CW0_OR   0x00000002
423 #define SPR_DMR1_CW0      (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR)
424 #define SPR_DMR1_CW1_AND  0x00000004
425 #define SPR_DMR1_CW1_OR   0x00000008
426 #define SPR_DMR1_CW1      (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR)
427 #define SPR_DMR1_CW2_AND  0x00000010
428 #define SPR_DMR1_CW2_OR   0x00000020
429 #define SPR_DMR1_CW2      (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR)
430 #define SPR_DMR1_CW3_AND  0x00000040
431 #define SPR_DMR1_CW3_OR   0x00000080
432 #define SPR_DMR1_CW3      (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR)
433 #define SPR_DMR1_CW4_AND  0x00000100
434 #define SPR_DMR1_CW4_OR   0x00000200
435 #define SPR_DMR1_CW4      (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR)
436 #define SPR_DMR1_CW5_AND  0x00000400
437 #define SPR_DMR1_CW5_OR   0x00000800
438 #define SPR_DMR1_CW5      (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR)
439 #define SPR_DMR1_CW6_AND  0x00001000
440 #define SPR_DMR1_CW6_OR   0x00002000
441 #define SPR_DMR1_CW6      (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR)
442 #define SPR_DMR1_CW7_AND  0x00004000
443 #define SPR_DMR1_CW7_OR   0x00008000
444 #define SPR_DMR1_CW7      (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR)
445 #define SPR_DMR1_CW8_AND  0x00010000
446 #define SPR_DMR1_CW8_OR   0x00020000
447 #define SPR_DMR1_CW8      (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR)
448 #define SPR_DMR1_CW9_AND  0x00040000
449 #define SPR_DMR1_CW9_OR   0x00080000
450 #define SPR_DMR1_CW9      (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR)
451 #define SPR_DMR1_RES1      0x00300000  /* Reserved */
452 #define SPR_DMR1_ST	  0x00400000  /* Single-step trace*/
453 #define SPR_DMR1_BT	  0x00800000  /* Branch trace */
454 #define SPR_DMR1_RES2	  0xff000000  /* Reserved */
455 
456 /*
457  * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB
458  *
459  */
460 #define SPR_DMR2_WCE0	   0x00000001  /* Watchpoint counter 0 enable */
461 #define SPR_DMR2_WCE1	   0x00000002  /* Watchpoint counter 0 enable */
462 #define SPR_DMR2_AWTC	   0x00000ffc  /* Assign watchpoints to counters */
463 #define SPR_DMR2_AWTC_OFF           2  /* Bit offset to AWTC field */
464 #define SPR_DMR2_WGB	   0x003ff000  /* Watchpoints generating breakpoint */
465 #define SPR_DMR2_WGB_OFF           12  /* Bit offset to WGB field */
466 #define SPR_DMR2_WBS	   0xffc00000  /* JPB: Watchpoint status */
467 #define SPR_DMR2_WBS_OFF           22  /* Bit offset to WBS field */
468 
469 /*
470  * Bit definitions for Debug watchpoint counter registers
471  *
472  */
473 #define SPR_DWCR_COUNT	    0x0000ffff  /* Count */
474 #define SPR_DWCR_MATCH	    0xffff0000  /* Match */
475 #define SPR_DWCR_MATCH_OFF          16  /* Match bit offset */
476 
477 /*
478  * Bit definitions for Debug stop register
479  *
480  */
481 #define SPR_DSR_RSTE	0x00000001  /* Reset exception */
482 #define SPR_DSR_BUSEE	0x00000002  /* Bus error exception */
483 #define SPR_DSR_DPFE	0x00000004  /* Data Page Fault exception */
484 #define SPR_DSR_IPFE	0x00000008  /* Insn Page Fault exception */
485 #define SPR_DSR_TTE	0x00000010  /* Tick Timer exception */
486 #define SPR_DSR_AE	0x00000020  /* Alignment exception */
487 #define SPR_DSR_IIE	0x00000040  /* Illegal Instruction exception */
488 #define SPR_DSR_IE	0x00000080  /* Interrupt exception */
489 #define SPR_DSR_DME	0x00000100  /* DTLB miss exception */
490 #define SPR_DSR_IME	0x00000200  /* ITLB miss exception */
491 #define SPR_DSR_RE	0x00000400  /* Range exception */
492 #define SPR_DSR_SCE	0x00000800  /* System call exception */
493 #define SPR_DSR_FPE     0x00001000  /* Floating Point Exception */
494 #define SPR_DSR_TE	0x00002000  /* Trap exception */
495 
496 /*
497  * Bit definitions for Debug reason register
498  *
499  */
500 #define SPR_DRR_RSTE	0x00000001  /* Reset exception */
501 #define SPR_DRR_BUSEE	0x00000002  /* Bus error exception */
502 #define SPR_DRR_DPFE	0x00000004  /* Data Page Fault exception */
503 #define SPR_DRR_IPFE	0x00000008  /* Insn Page Fault exception */
504 #define SPR_DRR_TTE	0x00000010  /* Tick Timer exception */
505 #define SPR_DRR_AE	0x00000020  /* Alignment exception */
506 #define SPR_DRR_IIE	0x00000040  /* Illegal Instruction exception */
507 #define SPR_DRR_IE	0x00000080  /* Interrupt exception */
508 #define SPR_DRR_DME	0x00000100  /* DTLB miss exception */
509 #define SPR_DRR_IME	0x00000200  /* ITLB miss exception */
510 #define SPR_DRR_RE	0x00000400  /* Range exception */
511 #define SPR_DRR_SCE	0x00000800  /* System call exception */
512 #define SPR_DRR_FPE     0x00001000  /* Floating Point Exception */
513 #define SPR_DRR_TE	0x00002000  /* Trap exception */
514 
515 /*
516  * Bit definitions for Performance counters mode registers
517  *
518  */
519 #define SPR_PCMR_CP	0x00000001  /* Counter present */
520 #define SPR_PCMR_UMRA	0x00000002  /* User mode read access */
521 #define SPR_PCMR_CISM	0x00000004  /* Count in supervisor mode */
522 #define SPR_PCMR_CIUM	0x00000008  /* Count in user mode */
523 #define SPR_PCMR_LA	0x00000010  /* Load access event */
524 #define SPR_PCMR_SA	0x00000020  /* Store access event */
525 #define SPR_PCMR_IF	0x00000040  /* Instruction fetch event*/
526 #define SPR_PCMR_DCM	0x00000080  /* Data cache miss event */
527 #define SPR_PCMR_ICM	0x00000100  /* Insn cache miss event */
528 #define SPR_PCMR_IFS	0x00000200  /* Insn fetch stall event */
529 #define SPR_PCMR_LSUS	0x00000400  /* LSU stall event */
530 #define SPR_PCMR_BS	0x00000800  /* Branch stall event */
531 #define SPR_PCMR_DTLBM	0x00001000  /* DTLB miss event */
532 #define SPR_PCMR_ITLBM	0x00002000  /* ITLB miss event */
533 #define SPR_PCMR_DDS	0x00004000  /* Data dependency stall event */
534 #define SPR_PCMR_WPE	0x03ff8000  /* Watchpoint events */
535 
536 /*
537  * Bit definitions for the Power management register
538  *
539  */
540 #define SPR_PMR_SDF	0x0000000f  /* Slow down factor */
541 #define SPR_PMR_DME	0x00000010  /* Doze mode enable */
542 #define SPR_PMR_SME	0x00000020  /* Sleep mode enable */
543 #define SPR_PMR_DCGE	0x00000040  /* Dynamic clock gating enable */
544 #define SPR_PMR_SUME	0x00000080  /* Suspend mode enable */
545 
546 /*
547  * Bit definitions for PICMR
548  *
549  */
550 #define SPR_PICMR_IUM	0xfffffffc  /* Interrupt unmask */
551 
552 /*
553  * Bit definitions for PICPR
554  *
555  */
556 #define SPR_PICPR_IPRIO	0xfffffffc  /* Interrupt priority */
557 
558 /*
559  * Bit definitions for PICSR
560  *
561  */
562 #define SPR_PICSR_IS	0xffffffff  /* Interrupt status */
563 
564 /*
565  * Bit definitions for Tick Timer Control Register
566  *
567  */
568 
569 #define SPR_TTCR_CNT	0xffffffff  /* Count, time period */
570 #define SPR_TTMR_TP	0x0fffffff  /* Time period */
571 #define SPR_TTMR_IP	0x10000000  /* Interrupt Pending */
572 #define SPR_TTMR_IE	0x20000000  /* Interrupt Enable */
573 #define SPR_TTMR_DI	0x00000000  /* Disabled */
574 #define SPR_TTMR_RT	0x40000000  /* Restart tick */
575 #define SPR_TTMR_SR     0x80000000  /* Single run */
576 #define SPR_TTMR_CR     0xc0000000  /* Continuous run */
577 #define SPR_TTMR_M      0xc0000000  /* Tick mode */
578 
579 /*
580  * Bit definitions for the FP Control Status Register
581  *
582  */
583 #define SPR_FPCSR_FPEE  0x00000001  /* Floating Point Exception Enable */
584 #define SPR_FPCSR_RM    0x00000006  /* Rounding Mode */
585 #define SPR_FPCSR_OVF   0x00000008  /* Overflow Flag */
586 #define SPR_FPCSR_UNF   0x00000010  /* Underflow Flag */
587 #define SPR_FPCSR_SNF   0x00000020  /* SNAN Flag */
588 #define SPR_FPCSR_QNF   0x00000040  /* QNAN Flag */
589 #define SPR_FPCSR_ZF    0x00000080  /* Zero Flag */
590 #define SPR_FPCSR_IXF   0x00000100  /* Inexact Flag */
591 #define SPR_FPCSR_IVF   0x00000200  /* Invalid Flag */
592 #define SPR_FPCSR_INF   0x00000400  /* Infinity Flag */
593 #define SPR_FPCSR_DZF   0x00000800  /* Divide By Zero Flag */
594 #define SPR_FPCSR_ALLF (SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \
595 			SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF |  \
596 			SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF)
597 
598 #define FPCSR_RM_RN (0<<1)
599 #define FPCSR_RM_RZ (1<<1)
600 #define FPCSR_RM_RIP (2<<1)
601 #define FPCSR_RM_RIN (3<<1)
602 
603 /*
604  * l.nop constants
605  *
606  */
607 #define NOP_NOP          0x0000      /* Normal nop instruction */
608 #define NOP_EXIT         0x0001      /* End of simulation */
609 #define NOP_REPORT       0x0002      /* Simple report */
610 /*#define NOP_PRINTF       0x0003       Simprintf instruction (obsolete)*/
611 #define NOP_PUTC         0x0004      /* JPB: Simputc instruction */
612 #define NOP_CNT_RESET    0x0005	     /* Reset statistics counters */
613 #define NOP_GET_TICKS    0x0006	     /* JPB: Get # ticks running */
614 #define NOP_GET_PS       0x0007      /* JPB: Get picosecs/cycle */
615 #define NOP_REPORT_FIRST 0x0400      /* Report with number */
616 #define NOP_REPORT_LAST  0x03ff      /* Report with number */
617 
618 #endif	/* SPR_DEFS__H */
619