1306e5e50SStefan Kristiansson/dts-v1/; 2306e5e50SStefan Kristiansson/ { 3306e5e50SStefan Kristiansson compatible = "opencores,or1ksim"; 4306e5e50SStefan Kristiansson #address-cells = <1>; 5306e5e50SStefan Kristiansson #size-cells = <1>; 6306e5e50SStefan Kristiansson interrupt-parent = <&pic>; 7306e5e50SStefan Kristiansson 8306e5e50SStefan Kristiansson aliases { 9306e5e50SStefan Kristiansson uart0 = &serial0; 10306e5e50SStefan Kristiansson }; 11306e5e50SStefan Kristiansson 12306e5e50SStefan Kristiansson chosen { 13306e5e50SStefan Kristiansson bootargs = "earlycon"; 14306e5e50SStefan Kristiansson stdout-path = "uart0:115200"; 15306e5e50SStefan Kristiansson }; 16306e5e50SStefan Kristiansson 17306e5e50SStefan Kristiansson memory@0 { 18306e5e50SStefan Kristiansson device_type = "memory"; 19306e5e50SStefan Kristiansson reg = <0x00000000 0x02000000>; 20306e5e50SStefan Kristiansson }; 21306e5e50SStefan Kristiansson 22306e5e50SStefan Kristiansson cpus { 23306e5e50SStefan Kristiansson #address-cells = <1>; 24306e5e50SStefan Kristiansson #size-cells = <0>; 25306e5e50SStefan Kristiansson cpu@0 { 26306e5e50SStefan Kristiansson compatible = "opencores,or1200-rtlsvn481"; 27306e5e50SStefan Kristiansson reg = <0>; 28306e5e50SStefan Kristiansson clock-frequency = <20000000>; 29306e5e50SStefan Kristiansson }; 30306e5e50SStefan Kristiansson cpu@1 { 31306e5e50SStefan Kristiansson compatible = "opencores,or1200-rtlsvn481"; 32306e5e50SStefan Kristiansson reg = <1>; 33306e5e50SStefan Kristiansson clock-frequency = <20000000>; 34306e5e50SStefan Kristiansson }; 35306e5e50SStefan Kristiansson }; 36306e5e50SStefan Kristiansson 37306e5e50SStefan Kristiansson ompic: ompic@98000000 { 38306e5e50SStefan Kristiansson compatible = "openrisc,ompic"; 39306e5e50SStefan Kristiansson reg = <0x98000000 16>; 40306e5e50SStefan Kristiansson interrupt-controller; 41306e5e50SStefan Kristiansson #interrupt-cells = <0>; 42306e5e50SStefan Kristiansson interrupts = <1>; 43306e5e50SStefan Kristiansson }; 44306e5e50SStefan Kristiansson 45306e5e50SStefan Kristiansson /* 46306e5e50SStefan Kristiansson * OR1K PIC is built into CPU and accessed via special purpose 47306e5e50SStefan Kristiansson * registers. It is not addressable and, hence, has no 'reg' 48306e5e50SStefan Kristiansson * property. 49306e5e50SStefan Kristiansson */ 50306e5e50SStefan Kristiansson pic: pic { 51306e5e50SStefan Kristiansson compatible = "opencores,or1k-pic-level"; 52306e5e50SStefan Kristiansson #interrupt-cells = <1>; 53306e5e50SStefan Kristiansson interrupt-controller; 54306e5e50SStefan Kristiansson }; 55306e5e50SStefan Kristiansson 56306e5e50SStefan Kristiansson serial0: serial@90000000 { 57306e5e50SStefan Kristiansson compatible = "opencores,uart16550-rtlsvn105", "ns16550a"; 58306e5e50SStefan Kristiansson reg = <0x90000000 0x100>; 59306e5e50SStefan Kristiansson interrupts = <2>; 60306e5e50SStefan Kristiansson clock-frequency = <20000000>; 61306e5e50SStefan Kristiansson }; 62306e5e50SStefan Kristiansson 63306e5e50SStefan Kristiansson}; 64