1*f81cc5acSFilip Kokosinski// SPDX-License-Identifier: GPL-2.0 2*f81cc5acSFilip Kokosinski/* 3*f81cc5acSFilip Kokosinski * LiteX-based System on Chip 4*f81cc5acSFilip Kokosinski * 5*f81cc5acSFilip Kokosinski * Copyright (C) 2019 Antmicro <www.antmicro.com> 6*f81cc5acSFilip Kokosinski */ 7*f81cc5acSFilip Kokosinski 8*f81cc5acSFilip Kokosinski/dts-v1/; 9*f81cc5acSFilip Kokosinski/ { 10*f81cc5acSFilip Kokosinski compatible = "opencores,or1ksim"; 11*f81cc5acSFilip Kokosinski #address-cells = <1>; 12*f81cc5acSFilip Kokosinski #size-cells = <1>; 13*f81cc5acSFilip Kokosinski interrupt-parent = <&pic>; 14*f81cc5acSFilip Kokosinski 15*f81cc5acSFilip Kokosinski aliases { 16*f81cc5acSFilip Kokosinski serial0 = &serial0; 17*f81cc5acSFilip Kokosinski }; 18*f81cc5acSFilip Kokosinski 19*f81cc5acSFilip Kokosinski chosen { 20*f81cc5acSFilip Kokosinski bootargs = "console=liteuart"; 21*f81cc5acSFilip Kokosinski }; 22*f81cc5acSFilip Kokosinski 23*f81cc5acSFilip Kokosinski memory@0 { 24*f81cc5acSFilip Kokosinski device_type = "memory"; 25*f81cc5acSFilip Kokosinski reg = <0x00000000 0x10000000>; 26*f81cc5acSFilip Kokosinski }; 27*f81cc5acSFilip Kokosinski 28*f81cc5acSFilip Kokosinski cpus { 29*f81cc5acSFilip Kokosinski #address-cells = <1>; 30*f81cc5acSFilip Kokosinski #size-cells = <0>; 31*f81cc5acSFilip Kokosinski cpu@0 { 32*f81cc5acSFilip Kokosinski compatible = "opencores,or1200-rtlsvn481"; 33*f81cc5acSFilip Kokosinski reg = <0>; 34*f81cc5acSFilip Kokosinski clock-frequency = <100000000>; 35*f81cc5acSFilip Kokosinski }; 36*f81cc5acSFilip Kokosinski }; 37*f81cc5acSFilip Kokosinski 38*f81cc5acSFilip Kokosinski pic: pic { 39*f81cc5acSFilip Kokosinski compatible = "opencores,or1k-pic"; 40*f81cc5acSFilip Kokosinski #interrupt-cells = <1>; 41*f81cc5acSFilip Kokosinski interrupt-controller; 42*f81cc5acSFilip Kokosinski }; 43*f81cc5acSFilip Kokosinski 44*f81cc5acSFilip Kokosinski serial0: serial@e0002000 { 45*f81cc5acSFilip Kokosinski device_type = "serial"; 46*f81cc5acSFilip Kokosinski compatible = "litex,liteuart"; 47*f81cc5acSFilip Kokosinski reg = <0xe0002000 0x100>; 48*f81cc5acSFilip Kokosinski }; 49*f81cc5acSFilip Kokosinski 50*f81cc5acSFilip Kokosinski soc_ctrl0: soc_controller@e0000000 { 51*f81cc5acSFilip Kokosinski compatible = "litex,soc-controller"; 52*f81cc5acSFilip Kokosinski reg = <0xe0000000 0xc>; 53*f81cc5acSFilip Kokosinski status = "okay"; 54*f81cc5acSFilip Kokosinski }; 55*f81cc5acSFilip Kokosinski}; 56