1# SPDX-License-Identifier: GPL-2.0 2# 3# For a description of the syntax of this configuration file, 4# see Documentation/kbuild/kconfig-language.txt. 5# 6 7config OPENRISC 8 def_bool y 9 select OF 10 select OF_EARLY_FLATTREE 11 select IRQ_DOMAIN 12 select HANDLE_DOMAIN_IRQ 13 select HAVE_MEMBLOCK 14 select GPIOLIB 15 select HAVE_ARCH_TRACEHOOK 16 select SPARSE_IRQ 17 select GENERIC_IRQ_CHIP 18 select GENERIC_IRQ_PROBE 19 select GENERIC_IRQ_SHOW 20 select GENERIC_IOMAP 21 select GENERIC_CPU_DEVICES 22 select HAVE_UID16 23 select GENERIC_ATOMIC64 24 select GENERIC_CLOCKEVENTS 25 select GENERIC_CLOCKEVENTS_BROADCAST 26 select GENERIC_STRNCPY_FROM_USER 27 select GENERIC_STRNLEN_USER 28 select GENERIC_SMP_IDLE_THREAD 29 select MODULES_USE_ELF_RELA 30 select HAVE_DEBUG_STACKOVERFLOW 31 select OR1K_PIC 32 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 33 select NO_BOOTMEM 34 select ARCH_USE_QUEUED_SPINLOCKS 35 select ARCH_USE_QUEUED_RWLOCKS 36 select OMPIC if SMP 37 select ARCH_WANT_FRAME_POINTERS 38 39config CPU_BIG_ENDIAN 40 def_bool y 41 42config MMU 43 def_bool y 44 45config RWSEM_GENERIC_SPINLOCK 46 def_bool y 47 48config RWSEM_XCHGADD_ALGORITHM 49 def_bool n 50 51config GENERIC_HWEIGHT 52 def_bool y 53 54config NO_IOPORT_MAP 55 def_bool y 56 57config TRACE_IRQFLAGS_SUPPORT 58 def_bool y 59 60# For now, use generic checksum functions 61#These can be reimplemented in assembly later if so inclined 62config GENERIC_CSUM 63 def_bool y 64 65config STACKTRACE_SUPPORT 66 def_bool y 67 68config LOCKDEP_SUPPORT 69 def_bool y 70 71source "init/Kconfig" 72 73source "kernel/Kconfig.freezer" 74 75menu "Processor type and features" 76 77choice 78 prompt "Subarchitecture" 79 default OR1K_1200 80 81config OR1K_1200 82 bool "OR1200" 83 help 84 Generic OpenRISC 1200 architecture 85 86endchoice 87 88config DCACHE_WRITETHROUGH 89 bool "Have write through data caches" 90 default n 91 help 92 Select this if your implementation features write through data caches. 93 Selecting 'N' here will allow the kernel to force flushing of data 94 caches at relevant times. Most OpenRISC implementations support write- 95 through data caches. 96 97 If unsure say N here 98 99config OPENRISC_BUILTIN_DTB 100 string "Builtin DTB" 101 default "" 102 103menu "Class II Instructions" 104 105config OPENRISC_HAVE_INST_FF1 106 bool "Have instruction l.ff1" 107 default y 108 help 109 Select this if your implementation has the Class II instruction l.ff1 110 111config OPENRISC_HAVE_INST_FL1 112 bool "Have instruction l.fl1" 113 default y 114 help 115 Select this if your implementation has the Class II instruction l.fl1 116 117config OPENRISC_HAVE_INST_MUL 118 bool "Have instruction l.mul for hardware multiply" 119 default y 120 help 121 Select this if your implementation has a hardware multiply instruction 122 123config OPENRISC_HAVE_INST_DIV 124 bool "Have instruction l.div for hardware divide" 125 default y 126 help 127 Select this if your implementation has a hardware divide instruction 128endmenu 129 130config NR_CPUS 131 int "Maximum number of CPUs (2-32)" 132 range 2 32 133 depends on SMP 134 default "2" 135 136config SMP 137 bool "Symmetric Multi-Processing support" 138 help 139 This enables support for systems with more than one CPU. If you have 140 a system with only one CPU, say N. If you have a system with more 141 than one CPU, say Y. 142 143 If you don't know what to do here, say N. 144 145source kernel/Kconfig.hz 146source kernel/Kconfig.preempt 147source "mm/Kconfig" 148 149config OPENRISC_NO_SPR_SR_DSX 150 bool "use SPR_SR_DSX software emulation" if OR1K_1200 151 default y 152 help 153 SPR_SR_DSX bit is status register bit indicating whether 154 the last exception has happened in delay slot. 155 156 OpenRISC architecture makes it optional to have it implemented 157 in hardware and the OR1200 does not have it. 158 159 Say N here if you know that your OpenRISC processor has 160 SPR_SR_DSX bit implemented. Say Y if you are unsure. 161 162config OPENRISC_HAVE_SHADOW_GPRS 163 bool "Support for shadow gpr files" if !SMP 164 default y if SMP 165 help 166 Say Y here if your OpenRISC processor features shadowed 167 register files. They will in such case be used as a 168 scratch reg storage on exception entry. 169 170 On SMP systems, this feature is mandatory. 171 On a unicore system it's safe to say N here if you are unsure. 172 173config CMDLINE 174 string "Default kernel command string" 175 default "" 176 help 177 On some architectures there is currently no way for the boot loader 178 to pass arguments to the kernel. For these architectures, you should 179 supply some command-line options at build time by entering them 180 here. 181 182menu "Debugging options" 183 184config JUMP_UPON_UNHANDLED_EXCEPTION 185 bool "Try to die gracefully" 186 default y 187 help 188 Now this puts kernel into infinite loop after first oops. Till 189 your kernel crashes this doesn't have any influence. 190 191 Say Y if you are unsure. 192 193config OPENRISC_ESR_EXCEPTION_BUG_CHECK 194 bool "Check for possible ESR exception bug" 195 default n 196 help 197 This option enables some checks that might expose some problems 198 in kernel. 199 200 Say N if you are unsure. 201 202endmenu 203 204endmenu 205 206menu "Executable file formats" 207 208source "fs/Kconfig.binfmt" 209 210endmenu 211 212source "net/Kconfig" 213 214source "drivers/Kconfig" 215 216source "fs/Kconfig" 217 218source "security/Kconfig" 219 220source "crypto/Kconfig" 221 222source "lib/Kconfig" 223 224menu "Kernel hacking" 225 226source "lib/Kconfig.debug" 227 228endmenu 229