1# SPDX-License-Identifier: GPL-2.0 2# 3# For a description of the syntax of this configuration file, 4# see Documentation/kbuild/kconfig-language.rst. 5# 6 7config OPENRISC 8 def_bool y 9 select ARCH_32BIT_OFF_T 10 select ARCH_HAS_DMA_SET_UNCACHED 11 select ARCH_HAS_DMA_CLEAR_UNCACHED 12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 13 select COMMON_CLK 14 select OF 15 select OF_EARLY_FLATTREE 16 select IRQ_DOMAIN 17 select GPIOLIB 18 select HAVE_ARCH_TRACEHOOK 19 select SPARSE_IRQ 20 select GENERIC_IRQ_CHIP 21 select GENERIC_IRQ_PROBE 22 select GENERIC_IRQ_SHOW 23 select GENERIC_PCI_IOMAP 24 select GENERIC_IOREMAP 25 select GENERIC_CPU_DEVICES 26 select HAVE_PCI 27 select HAVE_UID16 28 select GENERIC_ATOMIC64 29 select GENERIC_CLOCKEVENTS_BROADCAST 30 select GENERIC_SMP_IDLE_THREAD 31 select MODULES_USE_ELF_RELA 32 select HAVE_DEBUG_STACKOVERFLOW 33 select OR1K_PIC 34 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 35 select ARCH_USE_QUEUED_RWLOCKS 36 select OMPIC if SMP 37 select PCI_DOMAINS_GENERIC if PCI 38 select PCI_MSI if PCI 39 select ARCH_WANT_FRAME_POINTERS 40 select GENERIC_IRQ_MULTI_HANDLER 41 select MMU_GATHER_NO_RANGE if MMU 42 select TRACE_IRQFLAGS_SUPPORT 43 44config CPU_BIG_ENDIAN 45 def_bool y 46 47config MMU 48 def_bool y 49 50config GENERIC_HWEIGHT 51 def_bool y 52 53config NO_IOPORT_MAP 54 def_bool y 55 56# For now, use generic checksum functions 57#These can be reimplemented in assembly later if so inclined 58config GENERIC_CSUM 59 def_bool y 60 61config STACKTRACE_SUPPORT 62 def_bool y 63 64config LOCKDEP_SUPPORT 65 def_bool y 66 67config FIX_EARLYCON_MEM 68 def_bool y 69 70menu "Processor type and features" 71 72choice 73 prompt "Subarchitecture" 74 default OR1K_1200 75 76config OR1K_1200 77 bool "OR1200" 78 help 79 Generic OpenRISC 1200 architecture 80 81endchoice 82 83config DCACHE_WRITETHROUGH 84 bool "Have write through data caches" 85 default n 86 help 87 Select this if your implementation features write through data caches. 88 Selecting 'N' here will allow the kernel to force flushing of data 89 caches at relevant times. Most OpenRISC implementations support write- 90 through data caches. 91 92 If unsure say N here 93 94config OPENRISC_BUILTIN_DTB 95 string "Builtin DTB" 96 default "" 97 98menu "Class II Instructions" 99 100config OPENRISC_HAVE_INST_FF1 101 bool "Have instruction l.ff1" 102 default y 103 help 104 Select this if your implementation has the Class II instruction l.ff1 105 106config OPENRISC_HAVE_INST_FL1 107 bool "Have instruction l.fl1" 108 default y 109 help 110 Select this if your implementation has the Class II instruction l.fl1 111 112config OPENRISC_HAVE_INST_MUL 113 bool "Have instruction l.mul for hardware multiply" 114 default y 115 help 116 Select this if your implementation has a hardware multiply instruction 117 118config OPENRISC_HAVE_INST_DIV 119 bool "Have instruction l.div for hardware divide" 120 default y 121 help 122 Select this if your implementation has a hardware divide instruction 123 124config OPENRISC_HAVE_INST_CMOV 125 bool "Have instruction l.cmov for conditional move" 126 default n 127 help 128 This config enables gcc to generate l.cmov instructions when compiling 129 the kernel which in general will improve performance and reduce the 130 binary size. 131 132 Select this if your implementation has support for the Class II 133 l.cmov conistional move instruction. 134 135 Say N if you are unsure. 136 137config OPENRISC_HAVE_INST_ROR 138 bool "Have instruction l.ror for rotate right" 139 default n 140 help 141 This config enables gcc to generate l.ror instructions when compiling 142 the kernel which in general will improve performance and reduce the 143 binary size. 144 145 Select this if your implementation has support for the Class II 146 l.ror rotate right instruction. 147 148 Say N if you are unsure. 149 150config OPENRISC_HAVE_INST_RORI 151 bool "Have instruction l.rori for rotate right with immediate" 152 default n 153 help 154 This config enables gcc to generate l.rori instructions when compiling 155 the kernel which in general will improve performance and reduce the 156 binary size. 157 158 Select this if your implementation has support for the Class II 159 l.rori rotate right with immediate instruction. 160 161 Say N if you are unsure. 162 163config OPENRISC_HAVE_INST_SEXT 164 bool "Have instructions l.ext* for sign extension" 165 default n 166 help 167 This config enables gcc to generate l.ext* instructions when compiling 168 the kernel which in general will improve performance and reduce the 169 binary size. 170 171 Select this if your implementation has support for the Class II 172 l.exths, l.extbs, l.exthz and l.extbz size extend instructions. 173 174 Say N if you are unsure. 175 176endmenu 177 178config NR_CPUS 179 int "Maximum number of CPUs (2-32)" 180 range 2 32 181 depends on SMP 182 default "2" 183 184config SMP 185 bool "Symmetric Multi-Processing support" 186 help 187 This enables support for systems with more than one CPU. If you have 188 a system with only one CPU, say N. If you have a system with more 189 than one CPU, say Y. 190 191 If you don't know what to do here, say N. 192 193source "kernel/Kconfig.hz" 194 195config OPENRISC_NO_SPR_SR_DSX 196 bool "use SPR_SR_DSX software emulation" if OR1K_1200 197 default y 198 help 199 SPR_SR_DSX bit is status register bit indicating whether 200 the last exception has happened in delay slot. 201 202 OpenRISC architecture makes it optional to have it implemented 203 in hardware and the OR1200 does not have it. 204 205 Say N here if you know that your OpenRISC processor has 206 SPR_SR_DSX bit implemented. Say Y if you are unsure. 207 208config OPENRISC_HAVE_SHADOW_GPRS 209 bool "Support for shadow gpr files" if !SMP 210 default y if SMP 211 help 212 Say Y here if your OpenRISC processor features shadowed 213 register files. They will in such case be used as a 214 scratch reg storage on exception entry. 215 216 On SMP systems, this feature is mandatory. 217 On a unicore system it's safe to say N here if you are unsure. 218 219config CMDLINE 220 string "Default kernel command string" 221 default "" 222 help 223 On some architectures there is currently no way for the boot loader 224 to pass arguments to the kernel. For these architectures, you should 225 supply some command-line options at build time by entering them 226 here. 227 228menu "Debugging options" 229 230config JUMP_UPON_UNHANDLED_EXCEPTION 231 bool "Try to die gracefully" 232 default y 233 help 234 Now this puts kernel into infinite loop after first oops. Till 235 your kernel crashes this doesn't have any influence. 236 237 Say Y if you are unsure. 238 239config OPENRISC_ESR_EXCEPTION_BUG_CHECK 240 bool "Check for possible ESR exception bug" 241 default n 242 help 243 This option enables some checks that might expose some problems 244 in kernel. 245 246 Say N if you are unsure. 247 248endmenu 249 250endmenu 251