1# SPDX-License-Identifier: GPL-2.0 2# 3# For a description of the syntax of this configuration file, 4# see Documentation/kbuild/kconfig-language.txt. 5# 6 7config OPENRISC 8 def_bool y 9 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 10 select DMA_NONCOHERENT_OPS 11 select OF 12 select OF_EARLY_FLATTREE 13 select IRQ_DOMAIN 14 select HANDLE_DOMAIN_IRQ 15 select HAVE_MEMBLOCK 16 select GPIOLIB 17 select HAVE_ARCH_TRACEHOOK 18 select SPARSE_IRQ 19 select GENERIC_IRQ_CHIP 20 select GENERIC_IRQ_PROBE 21 select GENERIC_IRQ_SHOW 22 select GENERIC_IOMAP 23 select GENERIC_CPU_DEVICES 24 select HAVE_UID16 25 select GENERIC_ATOMIC64 26 select GENERIC_CLOCKEVENTS 27 select GENERIC_CLOCKEVENTS_BROADCAST 28 select GENERIC_STRNCPY_FROM_USER 29 select GENERIC_STRNLEN_USER 30 select GENERIC_SMP_IDLE_THREAD 31 select MODULES_USE_ELF_RELA 32 select HAVE_DEBUG_STACKOVERFLOW 33 select OR1K_PIC 34 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 35 select NO_BOOTMEM 36 select ARCH_USE_QUEUED_SPINLOCKS 37 select ARCH_USE_QUEUED_RWLOCKS 38 select OMPIC if SMP 39 select ARCH_WANT_FRAME_POINTERS 40 select GENERIC_IRQ_MULTI_HANDLER 41 42config CPU_BIG_ENDIAN 43 def_bool y 44 45config MMU 46 def_bool y 47 48config RWSEM_GENERIC_SPINLOCK 49 def_bool y 50 51config RWSEM_XCHGADD_ALGORITHM 52 def_bool n 53 54config GENERIC_HWEIGHT 55 def_bool y 56 57config NO_IOPORT_MAP 58 def_bool y 59 60config TRACE_IRQFLAGS_SUPPORT 61 def_bool y 62 63# For now, use generic checksum functions 64#These can be reimplemented in assembly later if so inclined 65config GENERIC_CSUM 66 def_bool y 67 68config STACKTRACE_SUPPORT 69 def_bool y 70 71config LOCKDEP_SUPPORT 72 def_bool y 73 74menu "Processor type and features" 75 76choice 77 prompt "Subarchitecture" 78 default OR1K_1200 79 80config OR1K_1200 81 bool "OR1200" 82 help 83 Generic OpenRISC 1200 architecture 84 85endchoice 86 87config DCACHE_WRITETHROUGH 88 bool "Have write through data caches" 89 default n 90 help 91 Select this if your implementation features write through data caches. 92 Selecting 'N' here will allow the kernel to force flushing of data 93 caches at relevant times. Most OpenRISC implementations support write- 94 through data caches. 95 96 If unsure say N here 97 98config OPENRISC_BUILTIN_DTB 99 string "Builtin DTB" 100 default "" 101 102menu "Class II Instructions" 103 104config OPENRISC_HAVE_INST_FF1 105 bool "Have instruction l.ff1" 106 default y 107 help 108 Select this if your implementation has the Class II instruction l.ff1 109 110config OPENRISC_HAVE_INST_FL1 111 bool "Have instruction l.fl1" 112 default y 113 help 114 Select this if your implementation has the Class II instruction l.fl1 115 116config OPENRISC_HAVE_INST_MUL 117 bool "Have instruction l.mul for hardware multiply" 118 default y 119 help 120 Select this if your implementation has a hardware multiply instruction 121 122config OPENRISC_HAVE_INST_DIV 123 bool "Have instruction l.div for hardware divide" 124 default y 125 help 126 Select this if your implementation has a hardware divide instruction 127endmenu 128 129config NR_CPUS 130 int "Maximum number of CPUs (2-32)" 131 range 2 32 132 depends on SMP 133 default "2" 134 135config SMP 136 bool "Symmetric Multi-Processing support" 137 help 138 This enables support for systems with more than one CPU. If you have 139 a system with only one CPU, say N. If you have a system with more 140 than one CPU, say Y. 141 142 If you don't know what to do here, say N. 143 144source kernel/Kconfig.hz 145 146config OPENRISC_NO_SPR_SR_DSX 147 bool "use SPR_SR_DSX software emulation" if OR1K_1200 148 default y 149 help 150 SPR_SR_DSX bit is status register bit indicating whether 151 the last exception has happened in delay slot. 152 153 OpenRISC architecture makes it optional to have it implemented 154 in hardware and the OR1200 does not have it. 155 156 Say N here if you know that your OpenRISC processor has 157 SPR_SR_DSX bit implemented. Say Y if you are unsure. 158 159config OPENRISC_HAVE_SHADOW_GPRS 160 bool "Support for shadow gpr files" if !SMP 161 default y if SMP 162 help 163 Say Y here if your OpenRISC processor features shadowed 164 register files. They will in such case be used as a 165 scratch reg storage on exception entry. 166 167 On SMP systems, this feature is mandatory. 168 On a unicore system it's safe to say N here if you are unsure. 169 170config CMDLINE 171 string "Default kernel command string" 172 default "" 173 help 174 On some architectures there is currently no way for the boot loader 175 to pass arguments to the kernel. For these architectures, you should 176 supply some command-line options at build time by entering them 177 here. 178 179menu "Debugging options" 180 181config JUMP_UPON_UNHANDLED_EXCEPTION 182 bool "Try to die gracefully" 183 default y 184 help 185 Now this puts kernel into infinite loop after first oops. Till 186 your kernel crashes this doesn't have any influence. 187 188 Say Y if you are unsure. 189 190config OPENRISC_ESR_EXCEPTION_BUG_CHECK 191 bool "Check for possible ESR exception bug" 192 default n 193 help 194 This option enables some checks that might expose some problems 195 in kernel. 196 197 Say N if you are unsure. 198 199endmenu 200 201endmenu 202