1# SPDX-License-Identifier: GPL-2.0 2# 3# For a description of the syntax of this configuration file, 4# see Documentation/kbuild/kconfig-language.rst. 5# 6 7config OPENRISC 8 def_bool y 9 select ARCH_32BIT_OFF_T 10 select ARCH_HAS_DMA_SET_UNCACHED 11 select ARCH_HAS_DMA_CLEAR_UNCACHED 12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 13 select OF 14 select OF_EARLY_FLATTREE 15 select IRQ_DOMAIN 16 select HANDLE_DOMAIN_IRQ 17 select GPIOLIB 18 select HAVE_ARCH_TRACEHOOK 19 select SPARSE_IRQ 20 select GENERIC_IRQ_CHIP 21 select GENERIC_IRQ_PROBE 22 select GENERIC_IRQ_SHOW 23 select GENERIC_IOMAP 24 select GENERIC_CPU_DEVICES 25 select HAVE_UID16 26 select GENERIC_ATOMIC64 27 select GENERIC_CLOCKEVENTS_BROADCAST 28 select GENERIC_SMP_IDLE_THREAD 29 select MODULES_USE_ELF_RELA 30 select HAVE_DEBUG_STACKOVERFLOW 31 select OR1K_PIC 32 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 33 select ARCH_USE_QUEUED_SPINLOCKS 34 select ARCH_USE_QUEUED_RWLOCKS 35 select OMPIC if SMP 36 select ARCH_WANT_FRAME_POINTERS 37 select GENERIC_IRQ_MULTI_HANDLER 38 select MMU_GATHER_NO_RANGE if MMU 39 select SET_FS 40 select TRACE_IRQFLAGS_SUPPORT 41 42config CPU_BIG_ENDIAN 43 def_bool y 44 45config MMU 46 def_bool y 47 48config GENERIC_HWEIGHT 49 def_bool y 50 51config NO_IOPORT_MAP 52 def_bool y 53 54# For now, use generic checksum functions 55#These can be reimplemented in assembly later if so inclined 56config GENERIC_CSUM 57 def_bool y 58 59config STACKTRACE_SUPPORT 60 def_bool y 61 62config LOCKDEP_SUPPORT 63 def_bool y 64 65menu "Processor type and features" 66 67choice 68 prompt "Subarchitecture" 69 default OR1K_1200 70 71config OR1K_1200 72 bool "OR1200" 73 help 74 Generic OpenRISC 1200 architecture 75 76endchoice 77 78config DCACHE_WRITETHROUGH 79 bool "Have write through data caches" 80 default n 81 help 82 Select this if your implementation features write through data caches. 83 Selecting 'N' here will allow the kernel to force flushing of data 84 caches at relevant times. Most OpenRISC implementations support write- 85 through data caches. 86 87 If unsure say N here 88 89config OPENRISC_BUILTIN_DTB 90 string "Builtin DTB" 91 default "" 92 93menu "Class II Instructions" 94 95config OPENRISC_HAVE_INST_FF1 96 bool "Have instruction l.ff1" 97 default y 98 help 99 Select this if your implementation has the Class II instruction l.ff1 100 101config OPENRISC_HAVE_INST_FL1 102 bool "Have instruction l.fl1" 103 default y 104 help 105 Select this if your implementation has the Class II instruction l.fl1 106 107config OPENRISC_HAVE_INST_MUL 108 bool "Have instruction l.mul for hardware multiply" 109 default y 110 help 111 Select this if your implementation has a hardware multiply instruction 112 113config OPENRISC_HAVE_INST_DIV 114 bool "Have instruction l.div for hardware divide" 115 default y 116 help 117 Select this if your implementation has a hardware divide instruction 118endmenu 119 120config NR_CPUS 121 int "Maximum number of CPUs (2-32)" 122 range 2 32 123 depends on SMP 124 default "2" 125 126config SMP 127 bool "Symmetric Multi-Processing support" 128 help 129 This enables support for systems with more than one CPU. If you have 130 a system with only one CPU, say N. If you have a system with more 131 than one CPU, say Y. 132 133 If you don't know what to do here, say N. 134 135source "kernel/Kconfig.hz" 136 137config OPENRISC_NO_SPR_SR_DSX 138 bool "use SPR_SR_DSX software emulation" if OR1K_1200 139 default y 140 help 141 SPR_SR_DSX bit is status register bit indicating whether 142 the last exception has happened in delay slot. 143 144 OpenRISC architecture makes it optional to have it implemented 145 in hardware and the OR1200 does not have it. 146 147 Say N here if you know that your OpenRISC processor has 148 SPR_SR_DSX bit implemented. Say Y if you are unsure. 149 150config OPENRISC_HAVE_SHADOW_GPRS 151 bool "Support for shadow gpr files" if !SMP 152 default y if SMP 153 help 154 Say Y here if your OpenRISC processor features shadowed 155 register files. They will in such case be used as a 156 scratch reg storage on exception entry. 157 158 On SMP systems, this feature is mandatory. 159 On a unicore system it's safe to say N here if you are unsure. 160 161config CMDLINE 162 string "Default kernel command string" 163 default "" 164 help 165 On some architectures there is currently no way for the boot loader 166 to pass arguments to the kernel. For these architectures, you should 167 supply some command-line options at build time by entering them 168 here. 169 170menu "Debugging options" 171 172config JUMP_UPON_UNHANDLED_EXCEPTION 173 bool "Try to die gracefully" 174 default y 175 help 176 Now this puts kernel into infinite loop after first oops. Till 177 your kernel crashes this doesn't have any influence. 178 179 Say Y if you are unsure. 180 181config OPENRISC_ESR_EXCEPTION_BUG_CHECK 182 bool "Check for possible ESR exception bug" 183 default n 184 help 185 This option enables some checks that might expose some problems 186 in kernel. 187 188 Say N if you are unsure. 189 190endmenu 191 192endmenu 193