1# SPDX-License-Identifier: GPL-2.0 2# 3# For a description of the syntax of this configuration file, 4# see Documentation/kbuild/kconfig-language.txt. 5# 6 7config OPENRISC 8 def_bool y 9 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 10 select OF 11 select OF_EARLY_FLATTREE 12 select IRQ_DOMAIN 13 select HANDLE_DOMAIN_IRQ 14 select GPIOLIB 15 select HAVE_ARCH_TRACEHOOK 16 select SPARSE_IRQ 17 select GENERIC_IRQ_CHIP 18 select GENERIC_IRQ_PROBE 19 select GENERIC_IRQ_SHOW 20 select GENERIC_IOMAP 21 select GENERIC_CPU_DEVICES 22 select HAVE_UID16 23 select GENERIC_ATOMIC64 24 select GENERIC_CLOCKEVENTS 25 select GENERIC_CLOCKEVENTS_BROADCAST 26 select GENERIC_STRNCPY_FROM_USER 27 select GENERIC_STRNLEN_USER 28 select GENERIC_SMP_IDLE_THREAD 29 select MODULES_USE_ELF_RELA 30 select HAVE_DEBUG_STACKOVERFLOW 31 select OR1K_PIC 32 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 33 select ARCH_USE_QUEUED_SPINLOCKS 34 select ARCH_USE_QUEUED_RWLOCKS 35 select OMPIC if SMP 36 select ARCH_WANT_FRAME_POINTERS 37 select GENERIC_IRQ_MULTI_HANDLER 38 39config CPU_BIG_ENDIAN 40 def_bool y 41 42config MMU 43 def_bool y 44 45config RWSEM_GENERIC_SPINLOCK 46 def_bool y 47 48config RWSEM_XCHGADD_ALGORITHM 49 def_bool n 50 51config GENERIC_HWEIGHT 52 def_bool y 53 54config NO_IOPORT_MAP 55 def_bool y 56 57config TRACE_IRQFLAGS_SUPPORT 58 def_bool y 59 60# For now, use generic checksum functions 61#These can be reimplemented in assembly later if so inclined 62config GENERIC_CSUM 63 def_bool y 64 65config STACKTRACE_SUPPORT 66 def_bool y 67 68config LOCKDEP_SUPPORT 69 def_bool y 70 71menu "Processor type and features" 72 73choice 74 prompt "Subarchitecture" 75 default OR1K_1200 76 77config OR1K_1200 78 bool "OR1200" 79 help 80 Generic OpenRISC 1200 architecture 81 82endchoice 83 84config DCACHE_WRITETHROUGH 85 bool "Have write through data caches" 86 default n 87 help 88 Select this if your implementation features write through data caches. 89 Selecting 'N' here will allow the kernel to force flushing of data 90 caches at relevant times. Most OpenRISC implementations support write- 91 through data caches. 92 93 If unsure say N here 94 95config OPENRISC_BUILTIN_DTB 96 string "Builtin DTB" 97 default "" 98 99menu "Class II Instructions" 100 101config OPENRISC_HAVE_INST_FF1 102 bool "Have instruction l.ff1" 103 default y 104 help 105 Select this if your implementation has the Class II instruction l.ff1 106 107config OPENRISC_HAVE_INST_FL1 108 bool "Have instruction l.fl1" 109 default y 110 help 111 Select this if your implementation has the Class II instruction l.fl1 112 113config OPENRISC_HAVE_INST_MUL 114 bool "Have instruction l.mul for hardware multiply" 115 default y 116 help 117 Select this if your implementation has a hardware multiply instruction 118 119config OPENRISC_HAVE_INST_DIV 120 bool "Have instruction l.div for hardware divide" 121 default y 122 help 123 Select this if your implementation has a hardware divide instruction 124endmenu 125 126config NR_CPUS 127 int "Maximum number of CPUs (2-32)" 128 range 2 32 129 depends on SMP 130 default "2" 131 132config SMP 133 bool "Symmetric Multi-Processing support" 134 help 135 This enables support for systems with more than one CPU. If you have 136 a system with only one CPU, say N. If you have a system with more 137 than one CPU, say Y. 138 139 If you don't know what to do here, say N. 140 141source "kernel/Kconfig.hz" 142 143config OPENRISC_NO_SPR_SR_DSX 144 bool "use SPR_SR_DSX software emulation" if OR1K_1200 145 default y 146 help 147 SPR_SR_DSX bit is status register bit indicating whether 148 the last exception has happened in delay slot. 149 150 OpenRISC architecture makes it optional to have it implemented 151 in hardware and the OR1200 does not have it. 152 153 Say N here if you know that your OpenRISC processor has 154 SPR_SR_DSX bit implemented. Say Y if you are unsure. 155 156config OPENRISC_HAVE_SHADOW_GPRS 157 bool "Support for shadow gpr files" if !SMP 158 default y if SMP 159 help 160 Say Y here if your OpenRISC processor features shadowed 161 register files. They will in such case be used as a 162 scratch reg storage on exception entry. 163 164 On SMP systems, this feature is mandatory. 165 On a unicore system it's safe to say N here if you are unsure. 166 167config CMDLINE 168 string "Default kernel command string" 169 default "" 170 help 171 On some architectures there is currently no way for the boot loader 172 to pass arguments to the kernel. For these architectures, you should 173 supply some command-line options at build time by entering them 174 here. 175 176menu "Debugging options" 177 178config JUMP_UPON_UNHANDLED_EXCEPTION 179 bool "Try to die gracefully" 180 default y 181 help 182 Now this puts kernel into infinite loop after first oops. Till 183 your kernel crashes this doesn't have any influence. 184 185 Say Y if you are unsure. 186 187config OPENRISC_ESR_EXCEPTION_BUG_CHECK 188 bool "Check for possible ESR exception bug" 189 default n 190 help 191 This option enables some checks that might expose some problems 192 in kernel. 193 194 Say N if you are unsure. 195 196endmenu 197 198endmenu 199