1# SPDX-License-Identifier: GPL-2.0 2# 3# For a description of the syntax of this configuration file, 4# see Documentation/kbuild/kconfig-language.txt. 5# 6 7config OPENRISC 8 def_bool y 9 select ARCH_32BIT_OFF_T 10 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 11 select OF 12 select OF_EARLY_FLATTREE 13 select IRQ_DOMAIN 14 select HANDLE_DOMAIN_IRQ 15 select GPIOLIB 16 select HAVE_ARCH_TRACEHOOK 17 select SPARSE_IRQ 18 select GENERIC_IRQ_CHIP 19 select GENERIC_IRQ_PROBE 20 select GENERIC_IRQ_SHOW 21 select GENERIC_IOMAP 22 select GENERIC_CPU_DEVICES 23 select HAVE_UID16 24 select GENERIC_ATOMIC64 25 select GENERIC_CLOCKEVENTS 26 select GENERIC_CLOCKEVENTS_BROADCAST 27 select GENERIC_STRNCPY_FROM_USER 28 select GENERIC_STRNLEN_USER 29 select GENERIC_SMP_IDLE_THREAD 30 select MODULES_USE_ELF_RELA 31 select HAVE_DEBUG_STACKOVERFLOW 32 select OR1K_PIC 33 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 34 select ARCH_USE_QUEUED_SPINLOCKS 35 select ARCH_USE_QUEUED_RWLOCKS 36 select OMPIC if SMP 37 select ARCH_WANT_FRAME_POINTERS 38 select GENERIC_IRQ_MULTI_HANDLER 39 40config CPU_BIG_ENDIAN 41 def_bool y 42 43config MMU 44 def_bool y 45 46config RWSEM_GENERIC_SPINLOCK 47 def_bool y 48 49config RWSEM_XCHGADD_ALGORITHM 50 def_bool n 51 52config GENERIC_HWEIGHT 53 def_bool y 54 55config NO_IOPORT_MAP 56 def_bool y 57 58config TRACE_IRQFLAGS_SUPPORT 59 def_bool y 60 61# For now, use generic checksum functions 62#These can be reimplemented in assembly later if so inclined 63config GENERIC_CSUM 64 def_bool y 65 66config STACKTRACE_SUPPORT 67 def_bool y 68 69config LOCKDEP_SUPPORT 70 def_bool y 71 72menu "Processor type and features" 73 74choice 75 prompt "Subarchitecture" 76 default OR1K_1200 77 78config OR1K_1200 79 bool "OR1200" 80 help 81 Generic OpenRISC 1200 architecture 82 83endchoice 84 85config DCACHE_WRITETHROUGH 86 bool "Have write through data caches" 87 default n 88 help 89 Select this if your implementation features write through data caches. 90 Selecting 'N' here will allow the kernel to force flushing of data 91 caches at relevant times. Most OpenRISC implementations support write- 92 through data caches. 93 94 If unsure say N here 95 96config OPENRISC_BUILTIN_DTB 97 string "Builtin DTB" 98 default "" 99 100menu "Class II Instructions" 101 102config OPENRISC_HAVE_INST_FF1 103 bool "Have instruction l.ff1" 104 default y 105 help 106 Select this if your implementation has the Class II instruction l.ff1 107 108config OPENRISC_HAVE_INST_FL1 109 bool "Have instruction l.fl1" 110 default y 111 help 112 Select this if your implementation has the Class II instruction l.fl1 113 114config OPENRISC_HAVE_INST_MUL 115 bool "Have instruction l.mul for hardware multiply" 116 default y 117 help 118 Select this if your implementation has a hardware multiply instruction 119 120config OPENRISC_HAVE_INST_DIV 121 bool "Have instruction l.div for hardware divide" 122 default y 123 help 124 Select this if your implementation has a hardware divide instruction 125endmenu 126 127config NR_CPUS 128 int "Maximum number of CPUs (2-32)" 129 range 2 32 130 depends on SMP 131 default "2" 132 133config SMP 134 bool "Symmetric Multi-Processing support" 135 help 136 This enables support for systems with more than one CPU. If you have 137 a system with only one CPU, say N. If you have a system with more 138 than one CPU, say Y. 139 140 If you don't know what to do here, say N. 141 142source "kernel/Kconfig.hz" 143 144config OPENRISC_NO_SPR_SR_DSX 145 bool "use SPR_SR_DSX software emulation" if OR1K_1200 146 default y 147 help 148 SPR_SR_DSX bit is status register bit indicating whether 149 the last exception has happened in delay slot. 150 151 OpenRISC architecture makes it optional to have it implemented 152 in hardware and the OR1200 does not have it. 153 154 Say N here if you know that your OpenRISC processor has 155 SPR_SR_DSX bit implemented. Say Y if you are unsure. 156 157config OPENRISC_HAVE_SHADOW_GPRS 158 bool "Support for shadow gpr files" if !SMP 159 default y if SMP 160 help 161 Say Y here if your OpenRISC processor features shadowed 162 register files. They will in such case be used as a 163 scratch reg storage on exception entry. 164 165 On SMP systems, this feature is mandatory. 166 On a unicore system it's safe to say N here if you are unsure. 167 168config CMDLINE 169 string "Default kernel command string" 170 default "" 171 help 172 On some architectures there is currently no way for the boot loader 173 to pass arguments to the kernel. For these architectures, you should 174 supply some command-line options at build time by entering them 175 here. 176 177menu "Debugging options" 178 179config JUMP_UPON_UNHANDLED_EXCEPTION 180 bool "Try to die gracefully" 181 default y 182 help 183 Now this puts kernel into infinite loop after first oops. Till 184 your kernel crashes this doesn't have any influence. 185 186 Say Y if you are unsure. 187 188config OPENRISC_ESR_EXCEPTION_BUG_CHECK 189 bool "Check for possible ESR exception bug" 190 default n 191 help 192 This option enables some checks that might expose some problems 193 in kernel. 194 195 Say N if you are unsure. 196 197endmenu 198 199endmenu 200