1b2441318SGreg Kroah-Hartman# SPDX-License-Identifier: GPL-2.0 2f8c4a270SJonas Bonn# 3f8c4a270SJonas Bonn# For a description of the syntax of this configuration file, 4cd238effSMauro Carvalho Chehab# see Documentation/kbuild/kconfig-language.rst. 5f8c4a270SJonas Bonn# 6f8c4a270SJonas Bonn 7f8c4a270SJonas Bonnconfig OPENRISC 8f8c4a270SJonas Bonn def_bool y 9942fa985SYury Norov select ARCH_32BIT_OFF_T 10a4a4d11aSChristoph Hellwig select ARCH_HAS_DMA_SET_UNCACHED 11a4a4d11aSChristoph Hellwig select ARCH_HAS_DMA_CLEAR_UNCACHED 125600779eSChristoph Hellwig select ARCH_HAS_SYNC_DMA_FOR_DEVICE 13f8c4a270SJonas Bonn select OF 14f8c4a270SJonas Bonn select OF_EARLY_FLATTREE 15b4c4c6eeSJonas Bonn select IRQ_DOMAIN 16d1f6f28fSMarc Zyngier select HANDLE_DOMAIN_IRQ 178636f344SLinus Walleij select GPIOLIB 18f8c4a270SJonas Bonn select HAVE_ARCH_TRACEHOOK 19c0fcaf55SJonas Bonn select SPARSE_IRQ 20f8c4a270SJonas Bonn select GENERIC_IRQ_CHIP 21f8c4a270SJonas Bonn select GENERIC_IRQ_PROBE 22f8c4a270SJonas Bonn select GENERIC_IRQ_SHOW 23f8c4a270SJonas Bonn select GENERIC_IOMAP 249f13a1fdSBen Hutchings select GENERIC_CPU_DEVICES 2504ea1e91SAndrew Morton select HAVE_UID16 260662d33aSRichard Weinberger select GENERIC_ATOMIC64 275bf8f6bfSAnna-Maria Gleixner select GENERIC_CLOCKEVENTS 288e6d08e0SStefan Kristiansson select GENERIC_CLOCKEVENTS_BROADCAST 29603d6637SJonas Bonn select GENERIC_STRNCPY_FROM_USER 30b48b2c3eSJonas Bonn select GENERIC_STRNLEN_USER 318e6d08e0SStefan Kristiansson select GENERIC_SMP_IDLE_THREAD 32786d35d4SDavid Howells select MODULES_USE_ELF_RELA 33d1a1dc0bSDave Hansen select HAVE_DEBUG_STACKOVERFLOW 344db8e6d2SStefan Kristiansson select OR1K_PIC 35fff7fb0bSZhaoxiu Zeng select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 36b5f82176SStafford Horne select ARCH_USE_QUEUED_SPINLOCKS 37b5f82176SStafford Horne select ARCH_USE_QUEUED_RWLOCKS 389b54470aSStafford Horne select OMPIC if SMP 39eecac38bSStafford Horne select ARCH_WANT_FRAME_POINTERS 40c5ca4560SPalmer Dabbelt select GENERIC_IRQ_MULTI_HANDLER 416137fed0SPeter Zijlstra select MMU_GATHER_NO_RANGE if MMU 42f8c4a270SJonas Bonn 434c97a0c8SBabu Mogerconfig CPU_BIG_ENDIAN 444c97a0c8SBabu Moger def_bool y 454c97a0c8SBabu Moger 46f8c4a270SJonas Bonnconfig MMU 47f8c4a270SJonas Bonn def_bool y 48f8c4a270SJonas Bonn 49f8c4a270SJonas Bonnconfig GENERIC_HWEIGHT 50f8c4a270SJonas Bonn def_bool y 51f8c4a270SJonas Bonn 52ce816fa8SUwe Kleine-Königconfig NO_IOPORT_MAP 53f8c4a270SJonas Bonn def_bool y 54f8c4a270SJonas Bonn 55f8c4a270SJonas Bonnconfig TRACE_IRQFLAGS_SUPPORT 56f8c4a270SJonas Bonn def_bool y 57f8c4a270SJonas Bonn 58f8c4a270SJonas Bonn# For now, use generic checksum functions 59f8c4a270SJonas Bonn#These can be reimplemented in assembly later if so inclined 60f8c4a270SJonas Bonnconfig GENERIC_CSUM 61f8c4a270SJonas Bonn def_bool y 62f8c4a270SJonas Bonn 63eecac38bSStafford Horneconfig STACKTRACE_SUPPORT 64eecac38bSStafford Horne def_bool y 65eecac38bSStafford Horne 6678cdfb5cSStafford Horneconfig LOCKDEP_SUPPORT 6778cdfb5cSStafford Horne def_bool y 6878cdfb5cSStafford Horne 69f8c4a270SJonas Bonnmenu "Processor type and features" 70f8c4a270SJonas Bonn 71f8c4a270SJonas Bonnchoice 72f8c4a270SJonas Bonn prompt "Subarchitecture" 73f8c4a270SJonas Bonn default OR1K_1200 74f8c4a270SJonas Bonn 75f8c4a270SJonas Bonnconfig OR1K_1200 76f8c4a270SJonas Bonn bool "OR1200" 77f8c4a270SJonas Bonn help 78f8c4a270SJonas Bonn Generic OpenRISC 1200 architecture 79f8c4a270SJonas Bonn 80f8c4a270SJonas Bonnendchoice 81f8c4a270SJonas Bonn 824ee93d80SJan Henrik Weinstockconfig DCACHE_WRITETHROUGH 834ee93d80SJan Henrik Weinstock bool "Have write through data caches" 844ee93d80SJan Henrik Weinstock default n 854ee93d80SJan Henrik Weinstock help 864ee93d80SJan Henrik Weinstock Select this if your implementation features write through data caches. 874ee93d80SJan Henrik Weinstock Selecting 'N' here will allow the kernel to force flushing of data 884ee93d80SJan Henrik Weinstock caches at relevant times. Most OpenRISC implementations support write- 894ee93d80SJan Henrik Weinstock through data caches. 904ee93d80SJan Henrik Weinstock 914ee93d80SJan Henrik Weinstock If unsure say N here 924ee93d80SJan Henrik Weinstock 93f8c4a270SJonas Bonnconfig OPENRISC_BUILTIN_DTB 94f8c4a270SJonas Bonn string "Builtin DTB" 95f8c4a270SJonas Bonn default "" 96f8c4a270SJonas Bonn 97f8c4a270SJonas Bonnmenu "Class II Instructions" 98f8c4a270SJonas Bonn 99f8c4a270SJonas Bonnconfig OPENRISC_HAVE_INST_FF1 100f8c4a270SJonas Bonn bool "Have instruction l.ff1" 101f8c4a270SJonas Bonn default y 102f8c4a270SJonas Bonn help 103f8c4a270SJonas Bonn Select this if your implementation has the Class II instruction l.ff1 104f8c4a270SJonas Bonn 105f8c4a270SJonas Bonnconfig OPENRISC_HAVE_INST_FL1 106f8c4a270SJonas Bonn bool "Have instruction l.fl1" 107f8c4a270SJonas Bonn default y 108f8c4a270SJonas Bonn help 109f8c4a270SJonas Bonn Select this if your implementation has the Class II instruction l.fl1 110f8c4a270SJonas Bonn 111f8c4a270SJonas Bonnconfig OPENRISC_HAVE_INST_MUL 112f8c4a270SJonas Bonn bool "Have instruction l.mul for hardware multiply" 113f8c4a270SJonas Bonn default y 114f8c4a270SJonas Bonn help 115f8c4a270SJonas Bonn Select this if your implementation has a hardware multiply instruction 116f8c4a270SJonas Bonn 117f8c4a270SJonas Bonnconfig OPENRISC_HAVE_INST_DIV 118f8c4a270SJonas Bonn bool "Have instruction l.div for hardware divide" 119f8c4a270SJonas Bonn default y 120f8c4a270SJonas Bonn help 121f8c4a270SJonas Bonn Select this if your implementation has a hardware divide instruction 122f8c4a270SJonas Bonnendmenu 123f8c4a270SJonas Bonn 12434bbdcdcSStafford Horneconfig NR_CPUS 1258e6d08e0SStefan Kristiansson int "Maximum number of CPUs (2-32)" 1268e6d08e0SStefan Kristiansson range 2 32 1278e6d08e0SStefan Kristiansson depends on SMP 1288e6d08e0SStefan Kristiansson default "2" 1298e6d08e0SStefan Kristiansson 1308e6d08e0SStefan Kristianssonconfig SMP 1318e6d08e0SStefan Kristiansson bool "Symmetric Multi-Processing support" 1328e6d08e0SStefan Kristiansson help 1338e6d08e0SStefan Kristiansson This enables support for systems with more than one CPU. If you have 1348e6d08e0SStefan Kristiansson a system with only one CPU, say N. If you have a system with more 1358e6d08e0SStefan Kristiansson than one CPU, say Y. 1368e6d08e0SStefan Kristiansson 1378e6d08e0SStefan Kristiansson If you don't know what to do here, say N. 138f8c4a270SJonas Bonn 1398636a1f9SMasahiro Yamadasource "kernel/Kconfig.hz" 140f8c4a270SJonas Bonn 141f8c4a270SJonas Bonnconfig OPENRISC_NO_SPR_SR_DSX 142f8c4a270SJonas Bonn bool "use SPR_SR_DSX software emulation" if OR1K_1200 143f8c4a270SJonas Bonn default y 144f8c4a270SJonas Bonn help 145f8c4a270SJonas Bonn SPR_SR_DSX bit is status register bit indicating whether 146f8c4a270SJonas Bonn the last exception has happened in delay slot. 147f8c4a270SJonas Bonn 148f8c4a270SJonas Bonn OpenRISC architecture makes it optional to have it implemented 149f8c4a270SJonas Bonn in hardware and the OR1200 does not have it. 150f8c4a270SJonas Bonn 151f8c4a270SJonas Bonn Say N here if you know that your OpenRISC processor has 152f8c4a270SJonas Bonn SPR_SR_DSX bit implemented. Say Y if you are unsure. 153f8c4a270SJonas Bonn 15491993c8cSStefan Kristianssonconfig OPENRISC_HAVE_SHADOW_GPRS 15591993c8cSStefan Kristiansson bool "Support for shadow gpr files" if !SMP 15691993c8cSStefan Kristiansson default y if SMP 15791993c8cSStefan Kristiansson help 15891993c8cSStefan Kristiansson Say Y here if your OpenRISC processor features shadowed 15991993c8cSStefan Kristiansson register files. They will in such case be used as a 16091993c8cSStefan Kristiansson scratch reg storage on exception entry. 16191993c8cSStefan Kristiansson 16291993c8cSStefan Kristiansson On SMP systems, this feature is mandatory. 16391993c8cSStefan Kristiansson On a unicore system it's safe to say N here if you are unsure. 16491993c8cSStefan Kristiansson 165f8c4a270SJonas Bonnconfig CMDLINE 166f8c4a270SJonas Bonn string "Default kernel command string" 167f8c4a270SJonas Bonn default "" 168f8c4a270SJonas Bonn help 169f8c4a270SJonas Bonn On some architectures there is currently no way for the boot loader 170f8c4a270SJonas Bonn to pass arguments to the kernel. For these architectures, you should 171f8c4a270SJonas Bonn supply some command-line options at build time by entering them 172f8c4a270SJonas Bonn here. 173f8c4a270SJonas Bonn 174f8c4a270SJonas Bonnmenu "Debugging options" 175f8c4a270SJonas Bonn 176f8c4a270SJonas Bonnconfig JUMP_UPON_UNHANDLED_EXCEPTION 177f8c4a270SJonas Bonn bool "Try to die gracefully" 178f8c4a270SJonas Bonn default y 179f8c4a270SJonas Bonn help 180f8c4a270SJonas Bonn Now this puts kernel into infinite loop after first oops. Till 181f8c4a270SJonas Bonn your kernel crashes this doesn't have any influence. 182f8c4a270SJonas Bonn 183f8c4a270SJonas Bonn Say Y if you are unsure. 184f8c4a270SJonas Bonn 185f8c4a270SJonas Bonnconfig OPENRISC_ESR_EXCEPTION_BUG_CHECK 186f8c4a270SJonas Bonn bool "Check for possible ESR exception bug" 187f8c4a270SJonas Bonn default n 188f8c4a270SJonas Bonn help 189f8c4a270SJonas Bonn This option enables some checks that might expose some problems 190f8c4a270SJonas Bonn in kernel. 191f8c4a270SJonas Bonn 192f8c4a270SJonas Bonn Say N if you are unsure. 193f8c4a270SJonas Bonn 194f8c4a270SJonas Bonnendmenu 195f8c4a270SJonas Bonn 196f8c4a270SJonas Bonnendmenu 197