1menu "Platform options" 2 3comment "Memory settings" 4 5config NIOS2_MEM_BASE 6 hex "Memory base address" 7 default "0x00000000" 8 help 9 This is the physical address of the memory that the kernel will run 10 from. This address is used to link the kernel and setup initial memory 11 management. You should take the raw memory address without any MMU 12 or cache bits set. 13 Please not that this address is used directly so you have to manually 14 do address translation if it's connected to a bridge. 15 16comment "Device tree" 17 18config NIOS2_DTB_AT_PHYS_ADDR 19 bool "DTB at physical address" 20 default n 21 help 22 When enabled you can select a physical address to load the dtb from. 23 Normally this address is passed by a bootloader such as u-boot but 24 using this you can use a devicetree without a bootloader. 25 This way you can store a devicetree in NOR flash or an onchip rom. 26 Please note that this address is used directly so you have to manually 27 do address translation if it's connected to a bridge. Also take into 28 account that when using an MMU you'd have to ad 0xC0000000 to your 29 address 30 31config NIOS2_DTB_PHYS_ADDR 32 hex "DTB Address" 33 depends on NIOS2_DTB_AT_PHYS_ADDR 34 default "0xC0000000" 35 help 36 Physical address of a dtb blob. 37 38config NIOS2_DTB_SOURCE_BOOL 39 bool "Compile and link device tree into kernel image" 40 default n 41 help 42 This allows you to specify a dts (device tree source) file 43 which will be compiled and linked into the kernel image. 44 45config NIOS2_DTB_SOURCE 46 string "Device tree source file" 47 depends on NIOS2_DTB_SOURCE_BOOL 48 default "" 49 help 50 Absolute path to the device tree source (dts) file describing your 51 system. 52 53comment "Nios II instructions" 54 55config NIOS2_ARCH_REVISION 56 int "Select Nios II architecture revision" 57 range 1 2 58 default 1 59 help 60 Select between Nios II R1 and Nios II R2 . The architectures 61 are binary incompatible. Default is R1 . 62 63config NIOS2_HW_MUL_SUPPORT 64 bool "Enable MUL instruction" 65 default n 66 help 67 Set to true if you configured the Nios II to include the MUL 68 instruction. This will enable the -mhw-mul compiler flag. 69 70config NIOS2_HW_MULX_SUPPORT 71 bool "Enable MULX instruction" 72 default n 73 help 74 Set to true if you configured the Nios II to include the MULX 75 instruction. Enables the -mhw-mulx compiler flag. 76 77config NIOS2_HW_DIV_SUPPORT 78 bool "Enable DIV instruction" 79 default n 80 help 81 Set to true if you configured the Nios II to include the DIV 82 instruction. Enables the -mhw-div compiler flag. 83 84config NIOS2_FPU_SUPPORT 85 bool "Custom floating point instr support" 86 default n 87 help 88 Enables the -mcustom-fpu-cfg=60-1 compiler flag. 89 90config NIOS2_CI_SWAB_SUPPORT 91 bool "Byteswap custom instruction" 92 default n 93 help 94 Use the byteswap (endian converter) Nios II custom instruction provided 95 by Altera and which can be enabled in QSYS builder. This accelerates 96 endian conversions in the kernel (e.g. ntohs). 97 98config NIOS2_CI_SWAB_NO 99 int "Byteswap custom instruction number" if NIOS2_CI_SWAB_SUPPORT 100 default 0 101 help 102 Number of the instruction as configured in QSYS Builder. 103 104comment "Cache settings" 105 106config CUSTOM_CACHE_SETTINGS 107 bool "Custom cache settings" 108 help 109 This option allows you to tweak the cache settings used during early 110 boot (where the information from device tree is not yet available). 111 There should be no reason to change these values. Linux will work 112 perfectly fine, even if the Nios II is configured with smaller caches. 113 114 Say N here unless you know what you are doing. 115 116config NIOS2_DCACHE_SIZE 117 hex "D-Cache size" if CUSTOM_CACHE_SETTINGS 118 range 0x200 0x10000 119 default "0x800" 120 help 121 Maximum possible data cache size. 122 123config NIOS2_DCACHE_LINE_SIZE 124 hex "D-Cache line size" if CUSTOM_CACHE_SETTINGS 125 range 0x10 0x20 126 default "0x20" 127 help 128 Minimum possible data cache line size. 129 130config NIOS2_ICACHE_SIZE 131 hex "I-Cache size" if CUSTOM_CACHE_SETTINGS 132 range 0x200 0x10000 133 default "0x1000" 134 help 135 Maximum possible instruction cache size. 136 137endmenu 138